[people/ms/u-boot.git] / drivers / mmc / socfpga_dw_mmc.c

/*
 * (C) Copyright 2013 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
#include <dm.h>
#include <dwmmc.h>
#include <errno.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <linux/err.h>
#include <malloc.h>

DECLARE_GLOBAL_DATA_PTR;

static const struct socfpga_clock_manager *clock_manager_base =
		(void *)SOCFPGA_CLKMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
		(void *)SOCFPGA_SYSMGR_ADDRESS;

struct socfpga_dwmci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

/* socfpga implmentation specific driver private data */
struct dwmci_socfpga_priv_data {
	struct dwmci_host	host;
	unsigned int		drvsel;
	unsigned int		smplsel;
};

static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
	struct dwmci_socfpga_priv_data *priv = host->priv;
	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);

	/* Disable SDMMC clock. */
	clrbits_le32(&clock_manager_base->per_pll.en,
		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);

	debug("%s: drvsel %d smplsel %d\n", __func__,
	      priv->drvsel, priv->smplsel);
	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);

	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
		readl(&system_manager_base->sdmmcgrp_ctrl));

	/* Enable SDMMC clock */
	setbits_le32(&clock_manager_base->per_pll.en,
		CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}

static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
	/* FIXME: probe from DT eventually too/ */
	const unsigned long clk = cm_get_mmc_controller_clk_hz();

	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;
	int fifo_depth;

	if (clk == 0) {
		printf("DWMMC: MMC clock is zero!");
		return -EINVAL;
	}

	fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
				    "fifo-depth", 0);
	if (fifo_depth < 0) {
		printf("DWMMC: Can't get FIFO depth\n");
		return -EINVAL;
	}

	host->name = dev->name;
	host->ioaddr = (void *)devfdt_get_addr(dev);
	host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
					"bus-width", 4);
	host->clksel = socfpga_dwmci_clksel;

	/*
	 * TODO(sjg@chromium.org): Remove the need for this hack.
	 * We only have one dwmmc block on gen5 SoCFPGA.
	 */
	host->dev_index = 0;
	/* Fixed clock divide by 4 which due to the SDMMC wrapper */
	host->bus_hz = clk;
	host->fifoth_val = MSIZE(0x2) |
		RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
	priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
				       "drvsel", 3);
	priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
					"smplsel", 0);
	host->priv = priv;

	return 0;
}

static int socfpga_dwmmc_probe(struct udevice *dev)
{
#ifdef CONFIG_BLK
	struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
#endif
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
	struct dwmci_host *host = &priv->host;

#ifdef CONFIG_BLK
	dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
	host->mmc = &plat->mmc;
#else
	int ret;

	ret = add_dwmci(host, host->bus_hz, 400000);
	if (ret)
		return ret;
#endif
	host->mmc->priv = &priv->host;
	upriv->mmc = host->mmc;
	host->mmc->dev = dev;

	return 0;
}

static int socfpga_dwmmc_bind(struct udevice *dev)
{
#ifdef CONFIG_BLK
	struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
	int ret;

	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
	if (ret)
		return ret;
#endif

	return 0;
}

static const struct udevice_id socfpga_dwmmc_ids[] = {
	{ .compatible = "altr,socfpga-dw-mshc" },
	{ }
};

U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
	.name		= "socfpga_dwmmc",
	.id		= UCLASS_MMC,
	.of_match	= socfpga_dwmmc_ids,
	.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
	.ops		= &dm_dwmci_ops,
	.bind		= socfpga_dwmmc_bind,
	.probe		= socfpga_dwmmc_probe,
	.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
	.platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
};
Commit	Line	Data
c5c1af21 CLS	1	/*
	2	* (C) Copyright 2013 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
c5c1af21 CLS	8	#include <asm/arch/clock_manager.h>
c5c1af21 CLS	9	#include <asm/arch/system_manager.h>
c35ed77a MV	10	#include <dm.h>
	11	#include <dwmmc.h>
	12	#include <errno.h>
	13	#include <fdtdec.h>
	14	#include <libfdt.h>
	15	#include <linux/err.h>
	16	#include <malloc.h>
	17
	18	DECLARE_GLOBAL_DATA_PTR;
c5c1af21 CLS	19
	20	static const struct socfpga_clock_manager *clock_manager_base =
	21	(void *)SOCFPGA_CLKMGR_ADDRESS;
	22	static const struct socfpga_system_manager *system_manager_base =
	23	(void *)SOCFPGA_SYSMGR_ADDRESS;
	24
f1a485aa SG	25	struct socfpga_dwmci_plat {
	26	struct mmc_config cfg;
	27	struct mmc mmc;
	28	};
	29
c35ed77a	30	/* socfpga implmentation specific driver private data */
9a41404d	31	struct dwmci_socfpga_priv_data {
c35ed77a MV	32	struct dwmci_host host;
	33	unsigned int drvsel;
	34	unsigned int smplsel;
9a41404d CLS	35	};
	36
	37	static void socfpga_dwmci_clksel(struct dwmci_host *host)
	38	{
	39	struct dwmci_socfpga_priv_data *priv = host->priv;
a1684b61 DN	40	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) \|
a1684b61 DN	41	((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
c5c1af21 CLS	42
c5c1af21 CLS	43	/* Disable SDMMC clock. */
51fb455f	44	clrbits_le32(&clock_manager_base->per_pll.en,
c5c1af21 CLS	45	CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
c5c1af21 CLS	46
9a41404d CLS	47	debug("%s: drvsel %d smplsel %d\n", __func__,
9a41404d CLS	48	priv->drvsel, priv->smplsel);
a1684b61	49	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
c5c1af21 CLS	50
	51	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
	52	readl(&system_manager_base->sdmmcgrp_ctrl));
	53
	54	/* Enable SDMMC clock */
51fb455f	55	setbits_le32(&clock_manager_base->per_pll.en,
c5c1af21 CLS	56	CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
	57	}
	58
c35ed77a	59	static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
c5c1af21	60	{
129adf5b MV	61	/* FIXME: probe from DT eventually too/ */
	62	const unsigned long clk = cm_get_mmc_controller_clk_hz();
	63
c35ed77a MV	64	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
	65	struct dwmci_host *host = &priv->host;
	66	int fifo_depth;
498d1a62 PM	67
498d1a62 PM	68	if (clk == 0) {
c35ed77a	69	printf("DWMMC: MMC clock is zero!");
129adf5b MV	70	return -EINVAL;
	71	}
	72
e160f7d4	73	fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
c35ed77a	74	"fifo-depth", 0);
129adf5b	75	if (fifo_depth < 0) {
c35ed77a	76	printf("DWMMC: Can't get FIFO depth\n");
129adf5b MV	77	return -EINVAL;
	78	}
	79
c35ed77a	80	host->name = dev->name;
a821c4af	81	host->ioaddr = (void *)devfdt_get_addr(dev);
e160f7d4	82	host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
c35ed77a	83	"bus-width", 4);
c5c1af21	84	host->clksel = socfpga_dwmci_clksel;
c35ed77a MV	85
	86	/*
	87	* TODO(sjg@chromium.org): Remove the need for this hack.
	88	* We only have one dwmmc block on gen5 SoCFPGA.
	89	*/
	90	host->dev_index = 0;
129adf5b	91	/* Fixed clock divide by 4 which due to the SDMMC wrapper */
498d1a62	92	host->bus_hz = clk;
c5c1af21	93	host->fifoth_val = MSIZE(0x2) \|
129adf5b	94	RX_WMARK(fifo_depth / 2 - 1) \| TX_WMARK(fifo_depth / 2);
e160f7d4	95	priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
c35ed77a	96	"drvsel", 3);
e160f7d4	97	priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
c35ed77a	98	"smplsel", 0);
9a41404d	99	host->priv = priv;
c5c1af21	100
129adf5b MV	101	return 0;
	102	}
	103
c35ed77a	104	static int socfpga_dwmmc_probe(struct udevice *dev)
129adf5b	105	{
f1a485aa SG	106	#ifdef CONFIG_BLK
	107	struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
	108	#endif
c35ed77a MV	109	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	110	struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
	111	struct dwmci_host *host = &priv->host;
f1a485aa SG	112
f1a485aa SG	113	#ifdef CONFIG_BLK
e5113c33	114	dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
f1a485aa SG	115	host->mmc = &plat->mmc;
f1a485aa SG	116	#else
c35ed77a	117	int ret;
129adf5b	118
c35ed77a MV	119	ret = add_dwmci(host, host->bus_hz, 400000);
	120	if (ret)
	121	return ret;
f1a485aa SG	122	#endif
f1a485aa SG	123	host->mmc->priv = &priv->host;
c35ed77a	124	upriv->mmc = host->mmc;
cffe5d86	125	host->mmc->dev = dev;
129adf5b	126
c35ed77a	127	return 0;
129adf5b	128	}
c35ed77a	129
f1a485aa SG	130	static int socfpga_dwmmc_bind(struct udevice *dev)
	131	{
	132	#ifdef CONFIG_BLK
	133	struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
	134	int ret;
	135
	136	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
	137	if (ret)
	138	return ret;
	139	#endif
	140
	141	return 0;
	142	}
	143
c35ed77a MV	144	static const struct udevice_id socfpga_dwmmc_ids[] = {
	145	{ .compatible = "altr,socfpga-dw-mshc" },
	146	{ }
	147	};
	148
	149	U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
	150	.name = "socfpga_dwmmc",
	151	.id = UCLASS_MMC,
	152	.of_match = socfpga_dwmmc_ids,
	153	.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
f55ae197	154	.ops = &dm_dwmci_ops,
f1a485aa	155	.bind = socfpga_dwmmc_bind,
c35ed77a MV	156	.probe = socfpga_dwmmc_probe,
c35ed77a MV	157	.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
f55ae197	158	.platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
c35ed77a	159	};