[people/ms/u-boot.git] / drivers / mmc / zynq_sdhci.c

/*
 * (C) Copyright 2013 - 2015 Xilinx, Inc.
 *
 * Xilinx Zynq SD Host Controller Interface
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
# define CONFIG_ZYNQ_SDHCI_MIN_FREQ	0
#endif

struct arasan_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
	unsigned int f_max;
};

static int arasan_sdhci_probe(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	struct clk clk;
	unsigned long clock;
	int ret;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return ret;
	}

	clock = clk_get_rate(&clk);
	if (IS_ERR_VALUE(clock)) {
		dev_err(dev, "failed to get rate\n");
		return clock;
	}
	debug("%s: CLK %ld\n", __func__, clock);

	ret = clk_enable(&clk);
	if (ret && ret != -ENOSYS) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
		       SDHCI_QUIRK_BROKEN_R1B;

#ifdef CONFIG_ZYNQ_HISPD_BROKEN
	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif

	host->max_clk = clock;

	ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
			      CONFIG_ZYNQ_SDHCI_MIN_FREQ);
	host->mmc = &plat->mmc;
	if (ret)
		return ret;
	host->mmc->priv = host;
	host->mmc->dev = dev;
	upriv->mmc = host->mmc;

	return sdhci_probe(dev);
}

static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
	struct sdhci_host *host = dev_get_priv(dev);

	host->name = dev->name;
	host->ioaddr = (void *)devfdt_get_addr(dev);

	plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
				"max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);

	return 0;
}

static int arasan_sdhci_bind(struct udevice *dev)
{
	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id arasan_sdhci_ids[] = {
	{ .compatible = "arasan,sdhci-8.9a" },
	{ }
};

U_BOOT_DRIVER(arasan_sdhci_drv) = {
	.name		= "arasan_sdhci",
	.id		= UCLASS_MMC,
	.of_match	= arasan_sdhci_ids,
	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
	.ops		= &sdhci_ops,
	.bind		= arasan_sdhci_bind,
	.probe		= arasan_sdhci_probe,
	.priv_auto_alloc_size = sizeof(struct sdhci_host),
	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
};
Commit	Line	Data
293eb33f	1	/*
d9ae52c8	2	* (C) Copyright 2013 - 2015 Xilinx, Inc.
293eb33f MS	3	*
	4	* Xilinx Zynq SD Host Controller Interface
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
293eb33f MS	7	*/
293eb33f MS	8
e0f4de1a	9	#include <clk.h>
293eb33f	10	#include <common.h>
d9ae52c8	11	#include <dm.h>
345d3c0f MS	12	#include <fdtdec.h>
345d3c0f MS	13	#include <libfdt.h>
293eb33f MS	14	#include <malloc.h>
293eb33f MS	15	#include <sdhci.h>
293eb33f	16
61e745d1 SH	17	DECLARE_GLOBAL_DATA_PTR;
61e745d1 SH	18
a57a4a5d SDPP	19	#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
	20	# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
	21	#endif
	22
329a449f SG	23	struct arasan_sdhci_plat {
	24	struct mmc_config cfg;
	25	struct mmc mmc;
61e745d1	26	unsigned int f_max;
329a449f SG	27	};
329a449f SG	28
d9ae52c8	29	static int arasan_sdhci_probe(struct udevice *dev)
293eb33f	30	{
329a449f	31	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
d9ae52c8 MS	32	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
d9ae52c8 MS	33	struct sdhci_host *host = dev_get_priv(dev);
e0f4de1a SH	34	struct clk clk;
e0f4de1a SH	35	unsigned long clock;
329a449f	36	int ret;
293eb33f	37
e0f4de1a SH	38	ret = clk_get_by_index(dev, 0, &clk);
	39	if (ret < 0) {
	40	dev_err(dev, "failed to get clock\n");
	41	return ret;
	42	}
	43
	44	clock = clk_get_rate(&clk);
	45	if (IS_ERR_VALUE(clock)) {
	46	dev_err(dev, "failed to get rate\n");
	47	return clock;
	48	}
	49	debug("%s: CLK %ld\n", __func__, clock);
	50
	51	ret = clk_enable(&clk);
	52	if (ret && ret != -ENOSYS) {
	53	dev_err(dev, "failed to enable clock\n");
	54	return ret;
	55	}
	56
eddabd16	57	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD \|
f9ec45d1	58	SDHCI_QUIRK_BROKEN_R1B;
b2156146 SDPP	59
	60	#ifdef CONFIG_ZYNQ_HISPD_BROKEN
	61	host->quirks \|= SDHCI_QUIRK_NO_HISPD_BIT;
	62	#endif
	63
e0f4de1a	64	host->max_clk = clock;
6d0e34bf	65
61e745d1	66	ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
14bed52d	67	CONFIG_ZYNQ_SDHCI_MIN_FREQ);
329a449f SG	68	host->mmc = &plat->mmc;
	69	if (ret)
	70	return ret;
	71	host->mmc->priv = host;
cffe5d86	72	host->mmc->dev = dev;
329a449f	73	upriv->mmc = host->mmc;
d9ae52c8	74
329a449f	75	return sdhci_probe(dev);
293eb33f	76	}
d9ae52c8 MS	77
	78	static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
	79	{
61e745d1	80	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
d9ae52c8 MS	81	struct sdhci_host *host = dev_get_priv(dev);
d9ae52c8 MS	82
cacd1d2f	83	host->name = dev->name;
a821c4af	84	host->ioaddr = (void *)devfdt_get_addr(dev);
d9ae52c8	85
da409ccc	86	plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
61e745d1 SH	87	"max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
61e745d1 SH	88
d9ae52c8 MS	89	return 0;
	90	}
	91
329a449f SG	92	static int arasan_sdhci_bind(struct udevice *dev)
	93	{
	94	struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
329a449f	95
24f5aec3	96	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
329a449f SG	97	}
329a449f SG	98
d9ae52c8 MS	99	static const struct udevice_id arasan_sdhci_ids[] = {
	100	{ .compatible = "arasan,sdhci-8.9a" },
	101	{ }
	102	};
	103
	104	U_BOOT_DRIVER(arasan_sdhci_drv) = {
	105	.name = "arasan_sdhci",
	106	.id = UCLASS_MMC,
	107	.of_match = arasan_sdhci_ids,
	108	.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
329a449f SG	109	.ops = &sdhci_ops,
329a449f SG	110	.bind = arasan_sdhci_bind,
d9ae52c8 MS	111	.probe = arasan_sdhci_probe,
d9ae52c8 MS	112	.priv_auto_alloc_size = sizeof(struct sdhci_host),
329a449f	113	.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
d9ae52c8	114	};