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Commit | Line | Data |
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4b0abf9f MY |
1 | menu "NAND Device Support" |
2 | ||
65e4145a MY |
3 | config SYS_NAND_SELF_INIT |
4 | bool | |
5 | help | |
6 | This option, if enabled, provides more flexible and linux-like | |
7 | NAND initialization process. | |
8 | ||
4b0abf9f MY |
9 | config NAND_DENALI |
10 | bool "Support Denali NAND controller" | |
65e4145a | 11 | select SYS_NAND_SELF_INIT |
4b0abf9f MY |
12 | help |
13 | Enable support for the Denali NAND controller. | |
14 | ||
15 | config SYS_NAND_DENALI_64BIT | |
16 | bool "Use 64-bit variant of Denali NAND controller" | |
17 | depends on NAND_DENALI | |
18 | help | |
19 | The Denali NAND controller IP has some variations in terms of | |
20 | the bus interface. The DMA setup sequence is completely differenct | |
21 | between 32bit / 64bit AXI bus variants. | |
22 | ||
23 | If your Denali NAND controller is the 64-bit variant, say Y. | |
24 | Otherwise (32 bit), say N. | |
25 | ||
26 | config NAND_DENALI_SPARE_AREA_SKIP_BYTES | |
27 | int "Number of bytes skipped in OOB area" | |
28 | depends on NAND_DENALI | |
29 | range 0 63 | |
30 | help | |
31 | This option specifies the number of bytes to skip from the beginning | |
32 | of OOB area before last ECC sector data starts. This is potentially | |
33 | used to preserve the bad block marker in the OOB area. | |
34 | ||
5519194d SA |
35 | config NAND_VF610_NFC |
36 | bool "Support for Freescale NFC for VF610/MPC5125" | |
37 | select SYS_NAND_SELF_INIT | |
38 | help | |
39 | Enables support for NAND Flash Controller on some Freescale | |
40 | processors like the VF610, MPC5125, MCF54418 or Kinetis K70. | |
41 | The driver supports a maximum 2k page size. The driver | |
42 | currently does not support hardware ECC. | |
43 | ||
080a71e8 SA |
44 | choice |
45 | prompt "Hardware ECC strength" | |
46 | depends on NAND_VF610_NFC | |
47 | default SYS_NAND_VF610_NFC_45_ECC_BYTES | |
48 | help | |
49 | Select the ECC strength used in the hardware BCH ECC block. | |
50 | ||
51 | config SYS_NAND_VF610_NFC_45_ECC_BYTES | |
52 | bool "24-error correction (45 ECC bytes)" | |
53 | ||
54 | config SYS_NAND_VF610_NFC_60_ECC_BYTES | |
55 | bool "32-error correction (60 ECC bytes)" | |
56 | ||
57 | endchoice | |
58 | ||
873960c8 SR |
59 | config NAND_PXA3XX |
60 | bool "Support for NAND on PXA3xx and Armada 370/XP/38x" | |
61 | select SYS_NAND_SELF_INIT | |
62 | help | |
63 | This enables the driver for the NAND flash device found on | |
64 | PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). | |
65 | ||
e5268616 | 66 | config NAND_SUNXI |
4ccae81c | 67 | bool "Support for NAND on Allwinner SoCs" |
e5268616 HG |
68 | depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
69 | select SYS_NAND_SELF_INIT | |
70 | ---help--- | |
4ccae81c BB |
71 | Enable support for NAND. This option enables the standard and |
72 | SPL drivers. | |
73 | The SPL driver only supports reading from the NAND using DMA | |
74 | transfers. | |
e5268616 | 75 | |
78cb965a SDPP |
76 | config NAND_ARASAN |
77 | bool "Configure Arasan Nand" | |
78 | help | |
79 | This enables Nand driver support for Arasan nand flash | |
80 | controller. This uses the hardware ECC for read and | |
81 | write operations. | |
82 | ||
df10a850 JT |
83 | config NAND_MXS |
84 | bool "MXS NAND support" | |
85 | depends on MX6 | |
86 | help | |
87 | This enables NAND driver for the NAND flash controller on the | |
88 | MXS processors. | |
89 | ||
5519194d SA |
90 | comment "Generic NAND options" |
91 | ||
92 | # Enhance depends when converting drivers to Kconfig which use this config | |
93 | # option (mxc_nand, ndfc, omap_gpmc). | |
94 | config SYS_NAND_BUSWIDTH_16BIT | |
95 | bool "Use 16-bit NAND interface" | |
96 | depends on NAND_VF610_NFC | |
97 | help | |
98 | Indicates that NAND device has 16-bit wide data-bus. In absence of this | |
99 | config, bus-width of NAND device is assumed to be either 8-bit and later | |
100 | determined by reading ONFI params. | |
101 | Above config is useful when NAND device's bus-width information cannot | |
102 | be determined from on-chip ONFI params, like in following scenarios: | |
103 | - SPL boot does not support reading of ONFI parameters. This is done to | |
104 | keep SPL code foot-print small. | |
105 | - In current U-Boot flow using nand_init(), driver initialization | |
106 | happens in board_nand_init() which is called before any device probe | |
107 | (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are | |
108 | not available while configuring controller. So a static CONFIG_NAND_xx | |
109 | is needed to know the device's bus-width in advance. | |
110 | ||
494e1086 BB |
111 | if SPL |
112 | ||
113 | config SYS_NAND_U_BOOT_LOCATIONS | |
114 | bool "Define U-boot binaries locations in NAND" | |
115 | help | |
116 | Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. | |
117 | This option should not be enabled when compiling U-boot for boards | |
118 | defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h | |
119 | file. | |
120 | ||
d90ba790 HG |
121 | config SYS_NAND_U_BOOT_OFFS |
122 | hex "Location in NAND to read U-Boot from" | |
123 | default 0x8000 if NAND_SUNXI | |
494e1086 | 124 | depends on SYS_NAND_U_BOOT_LOCATIONS |
d90ba790 HG |
125 | help |
126 | Set the offset from the start of the nand where u-boot should be | |
127 | loaded from. | |
128 | ||
80ef700f BB |
129 | config SYS_NAND_U_BOOT_OFFS_REDUND |
130 | hex "Location in NAND to read U-Boot from" | |
131 | default SYS_NAND_U_BOOT_OFFS | |
132 | depends on SYS_NAND_U_BOOT_LOCATIONS | |
133 | help | |
134 | Set the offset from the start of the nand where the redundant u-boot | |
135 | should be loaded from. | |
136 | ||
845034e6 MY |
137 | config SPL_NAND_DENALI |
138 | bool "Support Denali NAND controller for SPL" | |
139 | help | |
140 | This is a small implementation of the Denali NAND controller | |
141 | for use on SPL. | |
142 | ||
143 | endif | |
144 | ||
4b0abf9f | 145 | endmenu |