[people/ms/u-boot.git] / drivers / mtd / nand / davinci_nand.c

/*
 * NAND driver for TI DaVinci based boards.
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
 */

/*
 *
 * linux/drivers/mtd/nand/nand_davinci.c
 *
 * NAND Flash Driver
 *
 * Copyright (C) 2006 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   DaVinci board which utilizes the Samsung k9k2g08 part.
 *
 Modifications:
 ver. 1.0: Feb 2005, Vinod/Sudhakar
 -
 *
 */

#include <common.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>

/* Definitions for 4-bit hardware ECC */
#define NAND_TIMEOUT			10240
#define NAND_ECC_BUSY			0xC
#define NAND_4BITECC_MASK		0x03FF03FF
#define EMIF_NANDFSR_ECC_STATE_MASK  	0x00000F00
#define ECC_STATE_NO_ERR		0x0
#define ECC_STATE_TOO_MANY_ERRS		0x1
#define ECC_STATE_ERR_CORR_COMP_P	0x2
#define ECC_STATE_ERR_CORR_COMP_N	0x3

static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct		nand_chip *this = mtd->priv;
	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;

	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);

	if (ctrl & NAND_CTRL_CHANGE) {
		if ( ctrl & NAND_CLE )
			IO_ADDR_W |= MASK_CLE;
		if ( ctrl & NAND_ALE )
			IO_ADDR_W |= MASK_ALE;
		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
	}

	if (cmd != NAND_CMD_NONE)
		writeb(cmd, this->IO_ADDR_W);
}

#ifdef CONFIG_SYS_NAND_HW_ECC

static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u_int32_t	val;

	(void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));

	val = readl(&emif_regs->NANDFCR);
	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
	writel(val, &emif_regs->NANDFCR);
}

static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
{
	u_int32_t	ecc = 0;

	ecc = readl(&(emif_regs->NANDFECC[region - 1]));

	return(ecc);
}

static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
{
	u_int32_t		tmp;
	const int region = 1;

	tmp = nand_davinci_readecc(mtd, region);

	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);

	/* Invert so that erased block ECC is correct */
	tmp = ~tmp;

	*ecc_code++ = tmp;
	*ecc_code++ = tmp >>  8;
	*ecc_code++ = tmp >> 16;

	/* NOTE:  the above code matches mainline Linux:
	 *	.PQR.stu ==> ~PQRstu
	 *
	 * MontaVista/TI kernels encode those bytes differently, use
	 * complicated (and allegedly sometimes-wrong) correction code,
	 * and usually shipped with U-Boot that uses software ECC:
	 *	.PQR.stu ==> PsQRtu
	 *
	 * If you need MV/TI compatible NAND I/O in U-Boot, it should
	 * be possible to (a) change the mangling above, (b) reverse
	 * that mangling in nand_davinci_correct_data() below.
	 */

	return 0;
}

static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
{
	struct nand_chip *this = mtd->priv;
	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
					  (read_ecc[2] << 16);
	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
					  (calc_ecc[2] << 16);
	u_int32_t diff = ecc_calc ^ ecc_nand;

	if (diff) {
		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
			/* Correctable error */
			if ((diff >> (12 + 3)) < this->ecc.size) {
				uint8_t find_bit = 1 << ((diff >> 12) & 7);
				uint32_t find_byte = diff >> (12 + 3);

				dat[find_byte] ^= find_bit;
				MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
					 "bit ECC error at offset: %d, bit: "
					 "%d\n", find_byte, find_bit);
				return 1;
			} else {
				return -1;
			}
		} else if (!(diff & (diff - 1))) {
			/* Single bit ECC error in the ECC itself,
			   nothing to fix */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
				 "ECC.\n");
			return 1;
		} else {
			/* Uncorrectable error */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
			return -1;
		}
	}
	return(0);
}
#endif /* CONFIG_SYS_NAND_HW_ECC */

#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
#if defined(CONFIG_SYS_NAND_PAGE_2K)
	.eccbytes = 40,
	.eccpos = {
		24, 25, 26, 27, 28,
		29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
		39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
		49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
		59, 60, 61, 62, 63,
		},
	.oobfree = {
		{.offset = 2, .length = 22, },
	},
#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	.eccbytes = 80,
	.eccpos = {
		48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
		58, 59, 60, 61, 62, 63,	64, 65, 66, 67,
		68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
		78, 79,	80, 81, 82, 83,	84, 85, 86, 87,
		88, 89, 90, 91, 92, 93,	94, 95, 96, 97,
		98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
		108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
		},
	.oobfree = {
		{.offset = 2, .length = 46, },
	},
#endif
};

static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u32 val;

	switch (mode) {
	case NAND_ECC_WRITE:
	case NAND_ECC_READ:
		/*
		 * Start a new ECC calculation for reading or writing 512 bytes
		 * of data.
		 */
		val = readl(&emif_regs->NANDFCR);
		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
		writel(val, &emif_regs->NANDFCR);
		break;
	case NAND_ECC_READSYN:
		val = emif_regs->NAND4BITECC1;
		break;
	default:
		break;
	}
}

static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
{
	ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
	ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
	ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
	ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;

	return 0;
}

static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
					   const uint8_t *dat,
					   uint8_t *ecc_code)
{
	unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
	unsigned int const1 = 0, const2 = 0;
	unsigned char count1 = 0;

	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	/*Convert 10 bit ecc value to 8 bit */
	for (count1 = 0; count1 < 2; count1++) {
		const2 = count1 * 5;
		const1 = count1 * 2;

		/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
		ecc_code[const2] = hw_4ecc[const1] & 0xFF;

		/*
		 * Take 2 bits as LSB bits from val1 (count1=0) or val5
		 * (count1=1) and 6 bits from val2 (count1=0) or
		 * val5 (count1=1)
		 */
		ecc_code[const2 + 1] =
		    ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
						      0xFC);

		/*
		 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
		 * 4 bits from val3 (count1=0) or val6 (count1=1)
		 */
		ecc_code[const2 + 2] =
		    ((hw_4ecc[const1] >> 22) & 0xF) |
		    ((hw_4ecc[const1 + 1] << 4) & 0xF0);

		/*
		 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
		 * 2 bits from val4 (count1=0) or  val7 (count1=1)
		 */
		ecc_code[const2 + 3] =
		    ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
		    ((hw_4ecc[const1 + 1] >> 10) & 0xC0);

		/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
		ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
	}
	return 0;
}


static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
					  uint8_t *read_ecc, uint8_t *calc_ecc)
{
	unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
	int i;
	unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
	unsigned short *pspare = NULL, *pspare1 = NULL;
	unsigned int numerrors, erroraddress, errorvalue;
	u32 val;

	/*
	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we
	 * will assume we are looking at an erased page and we should ignore
	 * the ECC.
	 */
	for (i = 0; i < 10; i++) {
		if (read_ecc[i] != 0xFF)
			break;
	}
	if (i == 10)
		return 0;

	/* Convert 8 bit in to 10 bit */
	pspare = (unsigned short *)&read_ecc[2];
	pspare1 = (unsigned short *)&read_ecc[0];

	/* Take 10 bits from 0th and 1st bytes */
	ecc_10bit[0] = (*pspare1) & 0x3FF;

	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
	ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
	    | (((pspare[0]) << 6) & 0x3C0);

	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
	ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;

	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
	ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
	    | ((((pspare[1])) << 2) & 0x3FC);

	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
	ecc_10bit[4] = ((pspare[1]) >> 8)
	    | ((((pspare[2])) << 8) & 0x300);

	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
	ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;

	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
	ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
	    | ((((pspare[3])) << 4) & 0x3F0);

	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
	ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;

	/*
	 * Write the parity values in the NAND Flash 4-bit ECC Load register.
	 * Write each parity value one at a time starting from 4bit_ecc_val8
	 * to 4bit_ecc_val1.
	 */
	for (i = 7; i >= 0; i--)
		emif_regs->NAND4BITECCLOAD = ecc_10bit[i];

	/*
	 * Perform a dummy read to the EMIF Revision Code and Status register.
	 * This is required to ensure time for syndrome calculation after
	 * writing the ECC values in previous step.
	 */

	val = emif_regs->NANDFSR;

	/*
	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
	 * A syndrome value of 0 means no bit errors. If the syndrome is
	 * non-zero then go further otherwise return.
	 */
	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
	    hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
		return 0;

	/*
	 * Clear any previous address calculation by doing a dummy read of an
	 * error address register.
	 */
	val = emif_regs->NANDERRADD1;

	/*
	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
	 * register to 1.
	 */
	emif_regs->NANDFCR |= 1 << 13;

	/*
	 * Wait for the corr_state field (bits 8 to 11)in the
	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
	 */
	i = NAND_TIMEOUT;
	do {
		val = emif_regs->NANDFSR;
		val &= 0xc00;
		i--;
	} while ((i > 0) && val);

	iserror = emif_regs->NANDFSR;
	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
	iserror = iserror >> 8;

	/*
	 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
	 * corrected (five or more errors).  The number of errors
	 * calculated (err_num field) differs from the number of errors
	 * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
	 * correction complete (errors on bit 8 or 9).
	 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
	 * complete (error exists).
	 */

	if (iserror == ECC_STATE_NO_ERR) {
		val = emif_regs->NANDERRVAL1;
		return 0;
	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
		val = emif_regs->NANDERRVAL1;
		return -1;
	}

	numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;

	/* Read the error address, error value and correct */
	for (i = 0; i < numerrors; i++) {
		if (i > 1) {
			erroraddress =
			    ((emif_regs->NANDERRADD2 >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((emif_regs->NANDERRVAL2 >>
			      (16 * (i & 1))) & 0xFF);
		} else {
			erroraddress =
			    ((emif_regs->NANDERRADD1 >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((emif_regs->NANDERRVAL1 >>
			      (16 * (i & 1))) & 0xFF);
		}
		/* xor the corrupt data with error value */
		if (erroraddress < 512)
			dat[erroraddress] ^= errorvalue;
	}

	return numerrors;
}
#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */

static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
	return emif_regs->NANDFSR & 0x1;
}

static void nand_flash_init(void)
{
	/* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
	 * Instead, have your board_init() set EMIF timings, based on its
	 * knowledge of the clocks and what devices are hooked up ... and
	 * don't even do that unless no UBL handled it.
	 */
#ifdef CONFIG_SOC_DM644X
	u_int32_t	acfg1 = 0x3ffffffc;

	/*------------------------------------------------------------------*
	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
	 *                                                                  *
	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
	 *                                                                  *
	 *------------------------------------------------------------------*/
	 acfg1 = 0
		| (0 << 31 )	/* selectStrobe */
		| (0 << 30 )	/* extWait */
		| (1 << 26 )	/* writeSetup	10 ns */
		| (3 << 20 )	/* writeStrobe	40 ns */
		| (1 << 17 )	/* writeHold	10 ns */
		| (1 << 13 )	/* readSetup	10 ns */
		| (5 << 7 )	/* readStrobe	60 ns */
		| (1 << 4 )	/* readHold	10 ns */
		| (3 << 2 )	/* turnAround	?? ns */
		| (0 << 0 )	/* asyncSize	8-bit bus */
		;

	emif_regs->AB1CR = acfg1; /* CS2 */

	emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
#endif
}

void davinci_nand_init(struct nand_chip *nand)
{
	nand->chip_delay  = 0;
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
	nand->options	  |= NAND_USE_FLASH_BBT;
#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
	nand->ecc.mode = NAND_ECC_HW;
	nand->ecc.size = 512;
	nand->ecc.bytes = 3;
	nand->ecc.calculate = nand_davinci_calculate_ecc;
	nand->ecc.correct  = nand_davinci_correct_data;
	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
#else
	nand->ecc.mode = NAND_ECC_SOFT;
#endif /* CONFIG_SYS_NAND_HW_ECC */
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	nand->ecc.size = 512;
	nand->ecc.bytes = 10;
	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	nand->ecc.correct = nand_davinci_4bit_correct_data;
	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
#endif
	/* Set address of hardware control function */
	nand->cmd_ctrl = nand_davinci_hwcontrol;

	nand->dev_ready = nand_davinci_dev_ready;

	nand_flash_init();
}

int board_nand_init(struct nand_chip *chip) __attribute__((weak));

int board_nand_init(struct nand_chip *chip)
{
	davinci_nand_init(chip);
	return 0;
}
Commit	Line	Data
c74b2108 SK	1	/*
	2	* NAND driver for TI DaVinci based boards.
	3	*
	4	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	5	*
	6	* Based on Linux DaVinci NAND driver by TI. Original copyright follows:
	7	*/
	8
	9	/*
	10	*
	11	* linux/drivers/mtd/nand/nand_davinci.c
	12	*
	13	* NAND Flash Driver
	14	*
	15	* Copyright (C) 2006 Texas Instruments.
	16	*
	17	* ----------------------------------------------------------------------------
	18	*
	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License as published by
	21	* the Free Software Foundation; either version 2 of the License, or
	22	* (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	32	* ----------------------------------------------------------------------------
	33	*
	34	* Overview:
	35	* This is a device driver for the NAND flash device found on the
	36	* DaVinci board which utilizes the Samsung k9k2g08 part.
	37	*
	38	Modifications:
	39	ver. 1.0: Feb 2005, Vinod/Sudhakar
	40	-
	41	*
	42	*/
	43
	44	#include <common.h>
cfa460ad	45	#include <asm/io.h>
c74b2108 SK	46	#include <nand.h>
	47	#include <asm/arch/nand_defs.h>
	48	#include <asm/arch/emif_defs.h>
	49
77b351cd SP	50	/* Definitions for 4-bit hardware ECC */
	51	#define NAND_TIMEOUT 10240
	52	#define NAND_ECC_BUSY 0xC
	53	#define NAND_4BITECC_MASK 0x03FF03FF
	54	#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
	55	#define ECC_STATE_NO_ERR 0x0
	56	#define ECC_STATE_TOO_MANY_ERRS 0x1
	57	#define ECC_STATE_ERR_CORR_COMP_P 0x2
	58	#define ECC_STATE_ERR_CORR_COMP_N 0x3
	59
fcb77477 DB	60	static emif_registers const emif_regs = (void ) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
fcb77477 DB	61
cfa460ad	62	static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
c74b2108 SK	63	{
	64	struct nand_chip *this = mtd->priv;
	65	u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
	66
	67	IO_ADDR_W &= ~(MASK_ALE\|MASK_CLE);
	68
cfa460ad WJ	69	if (ctrl & NAND_CTRL_CHANGE) {
cfa460ad WJ	70	if ( ctrl & NAND_CLE )
c74b2108	71	IO_ADDR_W \|= MASK_CLE;
cfa460ad	72	if ( ctrl & NAND_ALE )
c74b2108	73	IO_ADDR_W \|= MASK_ALE;
cfa460ad	74	this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
c74b2108 SK	75	}
c74b2108 SK	76
5e1dae5c	77	if (cmd != NAND_CMD_NONE)
cfa460ad	78	writeb(cmd, this->IO_ADDR_W);
c74b2108 SK	79	}
c74b2108 SK	80
6d0f6bcf	81	#ifdef CONFIG_SYS_NAND_HW_ECC
c74b2108 SK	82
	83	static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
	84	{
97f4eb8c	85	u_int32_t val;
c74b2108	86
97f4eb8c	87	(void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2]));
c74b2108	88
97f4eb8c NT	89	val = readl(&emif_regs->NANDFCR);
	90	val \|= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
	91	writel(val, &emif_regs->NANDFCR);
c74b2108 SK	92	}
	93
	94	static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
	95	{
	96	u_int32_t ecc = 0;
c74b2108	97
97f4eb8c	98	ecc = readl(&(emif_regs->NANDFECC[region - 1]));
c74b2108 SK	99
	100	return(ecc);
	101	}
	102
	103	static int nand_davinci_calculate_ecc(struct mtd_info mtd, const u_char dat, u_char *ecc_code)
	104	{
	105	u_int32_t tmp;
9b05aa78 HV	106	const int region = 1;
	107
	108	tmp = nand_davinci_readecc(mtd, region);
	109
	110	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	111	* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	112	tmp = (tmp & 0x00000fff) \| ((tmp & 0x0fff0000) >> 4);
	113
	114	/* Invert so that erased block ECC is correct */
	115	tmp = ~tmp;
	116
	117	*ecc_code++ = tmp;
	118	*ecc_code++ = tmp >> 8;
	119	*ecc_code++ = tmp >> 16;
c74b2108	120
6e29ed8e DB	121	/* NOTE: the above code matches mainline Linux:
	122	* .PQR.stu ==> ~PQRstu
	123	*
	124	* MontaVista/TI kernels encode those bytes differently, use
	125	* complicated (and allegedly sometimes-wrong) correction code,
	126	* and usually shipped with U-Boot that uses software ECC:
	127	* .PQR.stu ==> PsQRtu
	128	*
	129	* If you need MV/TI compatible NAND I/O in U-Boot, it should
	130	* be possible to (a) change the mangling above, (b) reverse
	131	* that mangling in nand_davinci_correct_data() below.
	132	*/
c74b2108	133
6e29ed8e	134	return 0;
c74b2108 SK	135	}
	136
	137	static int nand_davinci_correct_data(struct mtd_info mtd, u_char dat, u_char read_ecc, u_char calc_ecc)
	138	{
9b05aa78	139	struct nand_chip *this = mtd->priv;
9b05aa78 HV	140	u_int32_t ecc_nand = read_ecc[0] \| (read_ecc[1] << 8) \|
	141	(read_ecc[2] << 16);
	142	u_int32_t ecc_calc = calc_ecc[0] \| (calc_ecc[1] << 8) \|
	143	(calc_ecc[2] << 16);
	144	u_int32_t diff = ecc_calc ^ ecc_nand;
	145
	146	if (diff) {
	147	if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
	148	/* Correctable error */
	149	if ((diff >> (12 + 3)) < this->ecc.size) {
	150	uint8_t find_bit = 1 << ((diff >> 12) & 7);
	151	uint32_t find_byte = diff >> (12 + 3);
	152
	153	dat[find_byte] ^= find_bit;
	154	MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
	155	"bit ECC error at offset: %d, bit: "
	156	"%d\n", find_byte, find_bit);
	157	return 1;
	158	} else {
	159	return -1;
	160	}
	161	} else if (!(diff & (diff - 1))) {
	162	/* Single bit ECC error in the ECC itself,
	163	nothing to fix */
	164	MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
	165	"ECC.\n");
	166	return 1;
	167	} else {
	168	/* Uncorrectable error */
	169	MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
	170	return -1;
	171	}
	172	}
c74b2108 SK	173	return(0);
c74b2108 SK	174	}
6d0f6bcf	175	#endif /* CONFIG_SYS_NAND_HW_ECC */
c74b2108	176
77b351cd SP	177	#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
77b351cd SP	178	static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
10a5a799	179	#if defined(CONFIG_SYS_NAND_PAGE_2K)
77b351cd SP	180	.eccbytes = 40,
	181	.eccpos = {
	182	24, 25, 26, 27, 28,
	183	29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
	184	39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
	185	49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
	186	59, 60, 61, 62, 63,
	187	},
	188	.oobfree = {
	189	{.offset = 2, .length = 22, },
	190	},
10a5a799 SP	191	#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	192	.eccbytes = 80,
	193	.eccpos = {
	194	48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
	195	58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
	196	68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
	197	78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
	198	88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
	199	98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
	200	108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
	201	118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
	202	},
	203	.oobfree = {
	204	{.offset = 2, .length = 46, },
	205	},
77b351cd SP	206	#endif
77b351cd SP	207	};
77b351cd SP	208
	209	static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
	210	{
	211	u32 val;
	212
	213	switch (mode) {
	214	case NAND_ECC_WRITE:
	215	case NAND_ECC_READ:
	216	/*
	217	* Start a new ECC calculation for reading or writing 512 bytes
	218	* of data.
	219	*/
97f4eb8c NT	220	val = readl(&emif_regs->NANDFCR);
	221	val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
	222	val \|= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
	223	val \|= DAVINCI_NANDFCR_4BIT_ECC_START;
	224	writel(val, &emif_regs->NANDFCR);
77b351cd SP	225	break;
	226	case NAND_ECC_READSYN:
	227	val = emif_regs->NAND4BITECC1;
	228	break;
	229	default:
	230	break;
	231	}
	232	}
	233
	234	static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
	235	{
	236	ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
	237	ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
	238	ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
	239	ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
	240
	241	return 0;
	242	}
	243
	244	static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
	245	const uint8_t *dat,
	246	uint8_t *ecc_code)
	247	{
	248	unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
	249	unsigned int const1 = 0, const2 = 0;
	250	unsigned char count1 = 0;
	251
	252	nand_davinci_4bit_readecc(mtd, hw_4ecc);
	253
	254	/Convert 10 bit ecc value to 8 bit /
	255	for (count1 = 0; count1 < 2; count1++) {
	256	const2 = count1 * 5;
	257	const1 = count1 * 2;
	258
	259	/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
	260	ecc_code[const2] = hw_4ecc[const1] & 0xFF;
	261
	262	/*
	263	* Take 2 bits as LSB bits from val1 (count1=0) or val5
	264	* (count1=1) and 6 bits from val2 (count1=0) or
	265	* val5 (count1=1)
	266	*/
	267	ecc_code[const2 + 1] =
	268	((hw_4ecc[const1] >> 8) & 0x3) \| ((hw_4ecc[const1] >> 14) &
	269	0xFC);
	270
	271	/*
	272	* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
	273	* 4 bits from val3 (count1=0) or val6 (count1=1)
	274	*/
	275	ecc_code[const2 + 2] =
	276	((hw_4ecc[const1] >> 22) & 0xF) \|
	277	((hw_4ecc[const1 + 1] << 4) & 0xF0);
	278
	279	/*
	280	* Take 6 bits from val3(count1=0) or val6 (count1=1) and
	281	* 2 bits from val4 (count1=0) or val7 (count1=1)
	282	*/
	283	ecc_code[const2 + 3] =
	284	((hw_4ecc[const1 + 1] >> 4) & 0x3F) \|
	285	((hw_4ecc[const1 + 1] >> 10) & 0xC0);
	286
	287	/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
	288	ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
289	}
290	return 0;
291	}
292
293
294	static int nand_davinci_4bit_correct_data(struct mtd_info mtd, uint8_t dat,
295	uint8_t read_ecc, uint8_t calc_ecc)
296	{
77b351cd SP	297	unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
	298	int i;
	299	unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
	300	unsigned short pspare = NULL, pspare1 = NULL;
	301	unsigned int numerrors, erroraddress, errorvalue;
	302	u32 val;
	303
	304	/*
	305	* Check for an ECC where all bytes are 0xFF. If this is the case, we
	306	* will assume we are looking at an erased page and we should ignore
	307	* the ECC.
	308	*/
	309	for (i = 0; i < 10; i++) {
	310	if (read_ecc[i] != 0xFF)
	311	break;
	312	}
	313	if (i == 10)
	314	return 0;
	315
	316	/* Convert 8 bit in to 10 bit */
	317	pspare = (unsigned short *)&read_ecc[2];
	318	pspare1 = (unsigned short *)&read_ecc[0];
	319
	320	/* Take 10 bits from 0th and 1st bytes */
	321	ecc_10bit[0] = (*pspare1) & 0x3FF;
	322
	323	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
	324	ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
	325	\| (((pspare[0]) << 6) & 0x3C0);
	326
	327	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
	328	ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
	329
	330	/Take 2 bits from 3rd byte and 8 bits from 4th byte /
	331	ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
	332	\| ((((pspare[1])) << 2) & 0x3FC);
	333
	334	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
	335	ecc_10bit[4] = ((pspare[1]) >> 8)
	336	\| ((((pspare[2])) << 8) & 0x300);
	337
	338	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
	339	ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
	340
	341	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
	342	ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
	343	\| ((((pspare[3])) << 4) & 0x3F0);
	344
	345	/Take 2 bits from 8th byte and 8 bits from 9th byte /
	346	ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
	347
	348	/*
	349	* Write the parity values in the NAND Flash 4-bit ECC Load register.
	350	* Write each parity value one at a time starting from 4bit_ecc_val8
	351	* to 4bit_ecc_val1.
	352	*/
	353	for (i = 7; i >= 0; i--)
	354	emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
	355
	356	/*
	357	* Perform a dummy read to the EMIF Revision Code and Status register.
	358	* This is required to ensure time for syndrome calculation after
	359	* writing the ECC values in previous step.
	360	*/
361
362	val = emif_regs->NANDFSR;
363
364	/*
365	* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
366	* A syndrome value of 0 means no bit errors. If the syndrome is
367	* non-zero then go further otherwise return.
368	*/
369	nand_davinci_4bit_readecc(mtd, hw_4ecc);
370
371	if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
372	hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
373	return 0;
374
375	/*
376	* Clear any previous address calculation by doing a dummy read of an
377	* error address register.
378	*/
379	val = emif_regs->NANDERRADD1;
380
381	/*
382	* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
383	* register to 1.
384	*/
385	emif_regs->NANDFCR \|= 1 << 13;
386
387	/*
388	* Wait for the corr_state field (bits 8 to 11)in the
389	* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
390	*/
391	i = NAND_TIMEOUT;
392	do {
393	val = emif_regs->NANDFSR;
394	val &= 0xc00;
395	i--;
396	} while ((i > 0) && val);
397
398	iserror = emif_regs->NANDFSR;
399	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
400	iserror = iserror >> 8;
401
402	/*
403	* ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
404	* corrected (five or more errors). The number of errors
405	* calculated (err_num field) differs from the number of errors
406	* searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
407	* correction complete (errors on bit 8 or 9).
408	* ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
409	* complete (error exists).
410	*/
411
412	if (iserror == ECC_STATE_NO_ERR) {
413	val = emif_regs->NANDERRVAL1;
414	return 0;
415	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
416	val = emif_regs->NANDERRVAL1;
417	return -1;
418	}
419
420	numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
421
422	/* Read the error address, error value and correct */
423	for (i = 0; i < numerrors; i++) {
424	if (i > 1) {
425	erroraddress =
426	((emif_regs->NANDERRADD2 >>
427	(16 * (i & 1))) & 0x3FF);
428	erroraddress = ((512 + 7) - erroraddress);
429	errorvalue =
430	((emif_regs->NANDERRVAL2 >>
431	(16 * (i & 1))) & 0xFF);
432	} else {
433	erroraddress =
434	((emif_regs->NANDERRADD1 >>
435	(16 * (i & 1))) & 0x3FF);
436	erroraddress = ((512 + 7) - erroraddress);
437	errorvalue =
438	((emif_regs->NANDERRVAL1 >>
439	(16 * (i & 1))) & 0xFF);
440	}
441	/* xor the corrupt data with error value */
442	if (erroraddress < 512)
443	dat[erroraddress] ^= errorvalue;
444	}
445
446	return numerrors;
447	}
d44e9c17	448	#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
77b351cd	449
c74b2108 SK	450	static int nand_davinci_dev_ready(struct mtd_info *mtd)
c74b2108 SK	451	{
fcb77477	452	return emif_regs->NANDFSR & 0x1;
c74b2108 SK	453	}
	454
	455	static void nand_flash_init(void)
	456	{
fcb77477 DB	457	/* This is for DM6446 EVM and very similar. DO NOT GROW THIS!
	458	* Instead, have your board_init() set EMIF timings, based on its
	459	* knowledge of the clocks and what devices are hooked up ... and
	460	* don't even do that unless no UBL handled it.
	461	*/
ed727d39	462	#ifdef CONFIG_SOC_DM644X
950a3924	463	u_int32_t acfg1 = 0x3ffffffc;
950a3924 WD	464
	465	/------------------------------------------------------------------
	466	* NAND FLASH CHIP TIMEOUT @ 459 MHz *
	467	* *
	468	* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
	469	* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
	470	* *
	471	------------------------------------------------------------------/
	472	acfg1 = 0
53677ef1 WD	473	\| (0 << 31 ) /* selectStrobe */
	474	\| (0 << 30 ) /* extWait */
	475	\| (1 << 26 ) /* writeSetup 10 ns */
	476	\| (3 << 20 ) /* writeStrobe 40 ns */
	477	\| (1 << 17 ) /* writeHold 10 ns */
	478	\| (1 << 13 ) /* readSetup 10 ns */
	479	\| (5 << 7 ) /* readStrobe 60 ns */
	480	\| (1 << 4 ) /* readHold 10 ns */
	481	\| (3 << 2 ) /* turnAround ?? ns */
	482	\| (0 << 0 ) /* asyncSize 8-bit bus */
	483	;
950a3924	484
d583ef51 TL	485	emif_regs->AB1CR = acfg1; /* CS2 */
	486
	487	emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
fcb77477	488	#endif
c74b2108 SK	489	}
c74b2108 SK	490
154b5484	491	void davinci_nand_init(struct nand_chip *nand)
c74b2108	492	{
c74b2108	493	nand->chip_delay = 0;
6d0f6bcf	494	#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
77b351cd	495	nand->options \|= NAND_USE_FLASH_BBT;
c74b2108	496	#endif
6d0f6bcf	497	#ifdef CONFIG_SYS_NAND_HW_ECC
5e1dae5c	498	nand->ecc.mode = NAND_ECC_HW;
9b05aa78 HV	499	nand->ecc.size = 512;
9b05aa78 HV	500	nand->ecc.bytes = 3;
cfa460ad WJ	501	nand->ecc.calculate = nand_davinci_calculate_ecc;
cfa460ad WJ	502	nand->ecc.correct = nand_davinci_correct_data;
4cbb651b	503	nand->ecc.hwctl = nand_davinci_enable_hwecc;
c74b2108	504	#else
5e1dae5c	505	nand->ecc.mode = NAND_ECC_SOFT;
6d0f6bcf	506	#endif /* CONFIG_SYS_NAND_HW_ECC */
77b351cd SP	507	#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	508	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	509	nand->ecc.size = 512;
	510	nand->ecc.bytes = 10;
	511	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	512	nand->ecc.correct = nand_davinci_4bit_correct_data;
	513	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	514	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
	515	#endif
c74b2108	516	/* Set address of hardware control function */
cfa460ad	517	nand->cmd_ctrl = nand_davinci_hwcontrol;
c74b2108 SK	518
c74b2108 SK	519	nand->dev_ready = nand_davinci_dev_ready;
c74b2108 SK	520
c74b2108 SK	521	nand_flash_init();
154b5484	522	}
c74b2108	523
154b5484 DB	524	int board_nand_init(struct nand_chip *chip) __attribute__((weak));
	525
	526	int board_nand_init(struct nand_chip *chip)
	527	{
	528	davinci_nand_init(chip);
	529	return 0;
c74b2108	530	}