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Commit | Line | Data |
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3eb3e72a CLS |
1 | /* |
2 | * Copyright (C) 2014 Panasonic Corporation | |
3 | * Copyright (C) 2013-2014, Altera Corporation <www.altera.com> | |
4 | * Copyright (C) 2009-2010, Intel Corporation and its suppliers. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <malloc.h> | |
11 | #include <nand.h> | |
12 | #include <asm/errno.h> | |
13 | #include <asm/io.h> | |
14 | ||
15 | #include "denali.h" | |
16 | ||
17 | #define NAND_DEFAULT_TIMINGS -1 | |
18 | ||
19 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | |
20 | ||
d3963721 SW |
21 | /* |
22 | * We define a macro here that combines all interrupts this driver uses into | |
23 | * a single constant value, for convenience. | |
24 | */ | |
3eb3e72a CLS |
25 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
26 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | |
27 | INTR_STATUS__ECC_ERR | \ | |
28 | INTR_STATUS__PROGRAM_FAIL | \ | |
29 | INTR_STATUS__LOAD_COMP | \ | |
30 | INTR_STATUS__PROGRAM_COMP | \ | |
31 | INTR_STATUS__TIME_OUT | \ | |
32 | INTR_STATUS__ERASE_FAIL | \ | |
33 | INTR_STATUS__RST_COMP | \ | |
34 | INTR_STATUS__ERASE_COMP | \ | |
35 | INTR_STATUS__ECC_UNCOR_ERR | \ | |
36 | INTR_STATUS__INT_ACT | \ | |
37 | INTR_STATUS__LOCKED_BLK) | |
38 | ||
d3963721 SW |
39 | /* |
40 | * indicates whether or not the internal value for the flash bank is | |
41 | * valid or not | |
42 | */ | |
3eb3e72a CLS |
43 | #define CHIP_SELECT_INVALID -1 |
44 | ||
45 | #define SUPPORT_8BITECC 1 | |
46 | ||
47 | /* | |
48 | * this macro allows us to convert from an MTD structure to our own | |
49 | * device context (denali) structure. | |
50 | */ | |
17cb4b8f SW |
51 | #define mtd_to_denali(m) \ |
52 | container_of(mtd_to_nand(m), struct denali_nand_info, nand) | |
3eb3e72a | 53 | |
d3963721 SW |
54 | /* |
55 | * These constants are defined by the driver to enable common driver | |
56 | * configuration options. | |
57 | */ | |
3eb3e72a CLS |
58 | #define SPARE_ACCESS 0x41 |
59 | #define MAIN_ACCESS 0x42 | |
60 | #define MAIN_SPARE_ACCESS 0x43 | |
d3963721 | 61 | #define PIPELINE_ACCESS 0x2000 |
3eb3e72a CLS |
62 | |
63 | #define DENALI_UNLOCK_START 0x10 | |
64 | #define DENALI_UNLOCK_END 0x11 | |
65 | #define DENALI_LOCK 0x21 | |
66 | #define DENALI_LOCK_TIGHT 0x31 | |
67 | #define DENALI_BUFFER_LOAD 0x60 | |
68 | #define DENALI_BUFFER_WRITE 0x62 | |
69 | ||
70 | #define DENALI_READ 0 | |
71 | #define DENALI_WRITE 0x100 | |
72 | ||
73 | /* types of device accesses. We can issue commands and get status */ | |
74 | #define COMMAND_CYCLE 0 | |
75 | #define ADDR_CYCLE 1 | |
76 | #define STATUS_CYCLE 2 | |
77 | ||
d3963721 SW |
78 | /* |
79 | * this is a helper macro that allows us to | |
80 | * format the bank into the proper bits for the controller | |
81 | */ | |
3eb3e72a CLS |
82 | #define BANK(x) ((x) << 24) |
83 | ||
84 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | |
85 | static inline void clear_interrupt(struct denali_nand_info *denali, | |
86 | uint32_t irq_mask) | |
87 | { | |
88 | uint32_t intr_status_reg; | |
89 | ||
90 | intr_status_reg = INTR_STATUS(denali->flash_bank); | |
91 | ||
92 | writel(irq_mask, denali->flash_reg + intr_status_reg); | |
93 | } | |
94 | ||
95 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | |
96 | { | |
97 | uint32_t intr_status_reg; | |
98 | ||
99 | intr_status_reg = INTR_STATUS(denali->flash_bank); | |
100 | ||
101 | return readl(denali->flash_reg + intr_status_reg); | |
102 | } | |
103 | ||
104 | static void clear_interrupts(struct denali_nand_info *denali) | |
105 | { | |
106 | uint32_t status; | |
107 | ||
108 | status = read_interrupt_status(denali); | |
109 | clear_interrupt(denali, status); | |
110 | ||
111 | denali->irq_status = 0; | |
112 | } | |
113 | ||
114 | static void denali_irq_enable(struct denali_nand_info *denali, | |
115 | uint32_t int_mask) | |
116 | { | |
117 | int i; | |
118 | ||
119 | for (i = 0; i < denali->max_banks; ++i) | |
120 | writel(int_mask, denali->flash_reg + INTR_EN(i)); | |
121 | } | |
122 | ||
123 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |
124 | { | |
125 | unsigned long timeout = 1000000; | |
126 | uint32_t intr_status; | |
127 | ||
128 | do { | |
129 | intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL; | |
130 | if (intr_status & irq_mask) { | |
131 | denali->irq_status &= ~irq_mask; | |
132 | /* our interrupt was detected */ | |
133 | break; | |
134 | } | |
135 | udelay(1); | |
136 | timeout--; | |
137 | } while (timeout != 0); | |
138 | ||
139 | if (timeout == 0) { | |
140 | /* timeout */ | |
141 | printf("Denali timeout with interrupt status %08x\n", | |
142 | read_interrupt_status(denali)); | |
143 | intr_status = 0; | |
144 | } | |
145 | return intr_status; | |
146 | } | |
147 | ||
148 | /* | |
149 | * Certain operations for the denali NAND controller use an indexed mode to | |
150 | * read/write data. The operation is performed by writing the address value | |
151 | * of the command to the device memory followed by the data. This function | |
152 | * abstracts this common operation. | |
d3963721 | 153 | */ |
3eb3e72a CLS |
154 | static void index_addr(struct denali_nand_info *denali, |
155 | uint32_t address, uint32_t data) | |
156 | { | |
157 | writel(address, denali->flash_mem + INDEX_CTRL_REG); | |
158 | writel(data, denali->flash_mem + INDEX_DATA_REG); | |
159 | } | |
160 | ||
161 | /* Perform an indexed read of the device */ | |
162 | static void index_addr_read_data(struct denali_nand_info *denali, | |
163 | uint32_t address, uint32_t *pdata) | |
164 | { | |
165 | writel(address, denali->flash_mem + INDEX_CTRL_REG); | |
166 | *pdata = readl(denali->flash_mem + INDEX_DATA_REG); | |
167 | } | |
168 | ||
d3963721 SW |
169 | /* |
170 | * We need to buffer some data for some of the NAND core routines. | |
171 | * The operations manage buffering that data. | |
172 | */ | |
3eb3e72a CLS |
173 | static void reset_buf(struct denali_nand_info *denali) |
174 | { | |
175 | denali->buf.head = 0; | |
176 | denali->buf.tail = 0; | |
177 | } | |
178 | ||
179 | static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |
180 | { | |
181 | denali->buf.buf[denali->buf.tail++] = byte; | |
182 | } | |
183 | ||
184 | /* resets a specific device connected to the core */ | |
185 | static void reset_bank(struct denali_nand_info *denali) | |
186 | { | |
187 | uint32_t irq_status; | |
d3963721 | 188 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
3eb3e72a CLS |
189 | |
190 | clear_interrupts(denali); | |
191 | ||
192 | writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET); | |
193 | ||
194 | irq_status = wait_for_irq(denali, irq_mask); | |
195 | if (irq_status & INTR_STATUS__TIME_OUT) | |
196 | debug("reset bank failed.\n"); | |
197 | } | |
198 | ||
199 | /* Reset the flash controller */ | |
200 | static uint32_t denali_nand_reset(struct denali_nand_info *denali) | |
201 | { | |
d3963721 | 202 | int i; |
3eb3e72a CLS |
203 | |
204 | for (i = 0; i < denali->max_banks; i++) | |
205 | writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, | |
206 | denali->flash_reg + INTR_STATUS(i)); | |
207 | ||
208 | for (i = 0; i < denali->max_banks; i++) { | |
209 | writel(1 << i, denali->flash_reg + DEVICE_RESET); | |
210 | while (!(readl(denali->flash_reg + INTR_STATUS(i)) & | |
211 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) | |
212 | if (readl(denali->flash_reg + INTR_STATUS(i)) & | |
213 | INTR_STATUS__TIME_OUT) | |
214 | debug("NAND Reset operation timed out on bank" | |
215 | " %d\n", i); | |
216 | } | |
217 | ||
218 | for (i = 0; i < denali->max_banks; i++) | |
219 | writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, | |
220 | denali->flash_reg + INTR_STATUS(i)); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | /* | |
226 | * this routine calculates the ONFI timing values for a given mode and | |
227 | * programs the clocking register accordingly. The mode is determined by | |
228 | * the get_onfi_nand_para routine. | |
229 | */ | |
230 | static void nand_onfi_timing_set(struct denali_nand_info *denali, | |
231 | uint16_t mode) | |
232 | { | |
233 | uint32_t trea[6] = {40, 30, 25, 20, 20, 16}; | |
234 | uint32_t trp[6] = {50, 25, 17, 15, 12, 10}; | |
235 | uint32_t treh[6] = {30, 15, 15, 10, 10, 7}; | |
236 | uint32_t trc[6] = {100, 50, 35, 30, 25, 20}; | |
237 | uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15}; | |
238 | uint32_t trloh[6] = {0, 0, 0, 0, 5, 5}; | |
239 | uint32_t tcea[6] = {100, 45, 30, 25, 25, 25}; | |
240 | uint32_t tadl[6] = {200, 100, 100, 100, 70, 70}; | |
241 | uint32_t trhw[6] = {200, 100, 100, 100, 100, 100}; | |
242 | uint32_t trhz[6] = {200, 100, 100, 100, 100, 100}; | |
243 | uint32_t twhr[6] = {120, 80, 80, 60, 60, 60}; | |
244 | uint32_t tcs[6] = {70, 35, 25, 25, 20, 15}; | |
245 | ||
3eb3e72a CLS |
246 | uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid; |
247 | uint32_t dv_window = 0; | |
248 | uint32_t en_lo, en_hi; | |
249 | uint32_t acc_clks; | |
250 | uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | |
251 | ||
252 | en_lo = DIV_ROUND_UP(trp[mode], CLK_X); | |
253 | en_hi = DIV_ROUND_UP(treh[mode], CLK_X); | |
254 | if ((en_hi * CLK_X) < (treh[mode] + 2)) | |
255 | en_hi++; | |
256 | ||
257 | if ((en_lo + en_hi) * CLK_X < trc[mode]) | |
258 | en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X), | |
259 | CLK_X); | |
260 | ||
261 | if ((en_lo + en_hi) < CLK_MULTI) | |
262 | en_lo += CLK_MULTI - en_lo - en_hi; | |
263 | ||
264 | while (dv_window < 8) { | |
265 | data_invalid_rhoh = en_lo * CLK_X + trhoh[mode]; | |
266 | ||
267 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode]; | |
268 | ||
d3963721 SW |
269 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
270 | data_invalid_rhoh : data_invalid_rloh; | |
3eb3e72a CLS |
271 | |
272 | dv_window = data_invalid - trea[mode]; | |
273 | ||
274 | if (dv_window < 8) | |
275 | en_lo++; | |
276 | } | |
277 | ||
278 | acc_clks = DIV_ROUND_UP(trea[mode], CLK_X); | |
279 | ||
d3963721 | 280 | while (acc_clks * CLK_X - trea[mode] < 3) |
3eb3e72a CLS |
281 | acc_clks++; |
282 | ||
d3963721 | 283 | if (data_invalid - acc_clks * CLK_X < 2) |
3eb3e72a CLS |
284 | debug("%s, Line %d: Warning!\n", __FILE__, __LINE__); |
285 | ||
286 | addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X); | |
287 | re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X); | |
288 | re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X); | |
289 | we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X); | |
290 | cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X); | |
3eb3e72a CLS |
291 | if (cs_cnt == 0) |
292 | cs_cnt = 1; | |
293 | ||
294 | if (tcea[mode]) { | |
d3963721 | 295 | while (cs_cnt * CLK_X + trea[mode] < tcea[mode]) |
3eb3e72a CLS |
296 | cs_cnt++; |
297 | } | |
298 | ||
299 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | |
d3963721 SW |
300 | if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 && |
301 | readl(denali->flash_reg + DEVICE_ID) == 0x88) | |
3eb3e72a CLS |
302 | acc_clks = 6; |
303 | ||
304 | writel(acc_clks, denali->flash_reg + ACC_CLKS); | |
305 | writel(re_2_we, denali->flash_reg + RE_2_WE); | |
306 | writel(re_2_re, denali->flash_reg + RE_2_RE); | |
307 | writel(we_2_re, denali->flash_reg + WE_2_RE); | |
308 | writel(addr_2_data, denali->flash_reg + ADDR_2_DATA); | |
309 | writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT); | |
310 | writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT); | |
311 | writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT); | |
312 | } | |
313 | ||
314 | /* queries the NAND device to see what ONFI modes it supports. */ | |
315 | static uint32_t get_onfi_nand_para(struct denali_nand_info *denali) | |
316 | { | |
317 | int i; | |
d3963721 | 318 | |
3eb3e72a CLS |
319 | /* |
320 | * we needn't to do a reset here because driver has already | |
321 | * reset all the banks before | |
322 | */ | |
323 | if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) & | |
324 | ONFI_TIMING_MODE__VALUE)) | |
325 | return -EIO; | |
326 | ||
327 | for (i = 5; i > 0; i--) { | |
328 | if (readl(denali->flash_reg + ONFI_TIMING_MODE) & | |
329 | (0x01 << i)) | |
330 | break; | |
331 | } | |
332 | ||
333 | nand_onfi_timing_set(denali, i); | |
334 | ||
d3963721 SW |
335 | /* |
336 | * By now, all the ONFI devices we know support the page cache | |
337 | * rw feature. So here we enable the pipeline_rw_ahead feature | |
338 | */ | |
339 | ||
3eb3e72a CLS |
340 | return 0; |
341 | } | |
342 | ||
343 | static void get_samsung_nand_para(struct denali_nand_info *denali, | |
344 | uint8_t device_id) | |
345 | { | |
346 | if (device_id == 0xd3) { /* Samsung K9WAG08U1A */ | |
347 | /* Set timing register values according to datasheet */ | |
348 | writel(5, denali->flash_reg + ACC_CLKS); | |
349 | writel(20, denali->flash_reg + RE_2_WE); | |
350 | writel(12, denali->flash_reg + WE_2_RE); | |
351 | writel(14, denali->flash_reg + ADDR_2_DATA); | |
352 | writel(3, denali->flash_reg + RDWR_EN_LO_CNT); | |
353 | writel(2, denali->flash_reg + RDWR_EN_HI_CNT); | |
354 | writel(2, denali->flash_reg + CS_SETUP_CNT); | |
355 | } | |
356 | } | |
357 | ||
358 | static void get_toshiba_nand_para(struct denali_nand_info *denali) | |
359 | { | |
360 | uint32_t tmp; | |
361 | ||
d3963721 SW |
362 | /* |
363 | * Workaround to fix a controller bug which reports a wrong | |
364 | * spare area size for some kind of Toshiba NAND device | |
365 | */ | |
3eb3e72a CLS |
366 | if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
367 | (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | |
368 | writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
369 | tmp = readl(denali->flash_reg + DEVICES_CONNECTED) * | |
370 | readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
371 | writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); | |
372 | } | |
373 | } | |
374 | ||
375 | static void get_hynix_nand_para(struct denali_nand_info *denali, | |
376 | uint8_t device_id) | |
377 | { | |
378 | uint32_t main_size, spare_size; | |
379 | ||
380 | switch (device_id) { | |
381 | case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */ | |
382 | case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */ | |
383 | writel(128, denali->flash_reg + PAGES_PER_BLOCK); | |
384 | writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
385 | writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
386 | main_size = 4096 * | |
387 | readl(denali->flash_reg + DEVICES_CONNECTED); | |
388 | spare_size = 224 * | |
389 | readl(denali->flash_reg + DEVICES_CONNECTED); | |
390 | writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); | |
391 | writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); | |
392 | writel(0, denali->flash_reg + DEVICE_WIDTH); | |
393 | break; | |
394 | default: | |
d3963721 | 395 | debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n" |
3eb3e72a CLS |
396 | "Will use default parameter values instead.\n", |
397 | device_id); | |
398 | } | |
399 | } | |
400 | ||
401 | /* | |
402 | * determines how many NAND chips are connected to the controller. Note for | |
403 | * Intel CE4100 devices we don't support more than one device. | |
404 | */ | |
405 | static void find_valid_banks(struct denali_nand_info *denali) | |
406 | { | |
407 | uint32_t id[denali->max_banks]; | |
408 | int i; | |
409 | ||
410 | denali->total_used_banks = 1; | |
411 | for (i = 0; i < denali->max_banks; i++) { | |
d3963721 SW |
412 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
413 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); | |
414 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); | |
3eb3e72a CLS |
415 | |
416 | if (i == 0) { | |
417 | if (!(id[i] & 0x0ff)) | |
418 | break; | |
419 | } else { | |
420 | if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) | |
421 | denali->total_used_banks++; | |
422 | else | |
423 | break; | |
424 | } | |
425 | } | |
426 | } | |
427 | ||
428 | /* | |
429 | * Use the configuration feature register to determine the maximum number of | |
430 | * banks that the hardware supports. | |
431 | */ | |
432 | static void detect_max_banks(struct denali_nand_info *denali) | |
433 | { | |
434 | uint32_t features = readl(denali->flash_reg + FEATURES); | |
15305c2f GM |
435 | /* |
436 | * Read the revision register, so we can calculate the max_banks | |
437 | * properly: the encoding changed from rev 5.0 to 5.1 | |
438 | */ | |
439 | u32 revision = MAKE_COMPARABLE_REVISION( | |
440 | readl(denali->flash_reg + REVISION)); | |
441 | if (revision < REVISION_5_1) | |
442 | denali->max_banks = 2 << (features & FEATURES__N_BANKS); | |
443 | else | |
444 | denali->max_banks = 1 << (features & FEATURES__N_BANKS); | |
3eb3e72a CLS |
445 | } |
446 | ||
447 | static void detect_partition_feature(struct denali_nand_info *denali) | |
448 | { | |
449 | /* | |
450 | * For MRST platform, denali->fwblks represent the | |
451 | * number of blocks firmware is taken, | |
452 | * FW is in protect partition and MTD driver has no | |
453 | * permission to access it. So let driver know how many | |
454 | * blocks it can't touch. | |
455 | */ | |
456 | if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { | |
457 | if ((readl(denali->flash_reg + PERM_SRC_ID(1)) & | |
458 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | |
459 | denali->fwblks = | |
460 | ((readl(denali->flash_reg + MIN_MAX_BANK(1)) & | |
461 | MIN_MAX_BANK__MIN_VALUE) * | |
462 | denali->blksperchip) | |
463 | + | |
464 | (readl(denali->flash_reg + MIN_BLK_ADDR(1)) & | |
465 | MIN_BLK_ADDR__VALUE); | |
466 | } else { | |
467 | denali->fwblks = SPECTRA_START_BLOCK; | |
468 | } | |
469 | } else { | |
470 | denali->fwblks = SPECTRA_START_BLOCK; | |
471 | } | |
472 | } | |
473 | ||
474 | static uint32_t denali_nand_timing_set(struct denali_nand_info *denali) | |
475 | { | |
d3963721 SW |
476 | uint32_t id_bytes[8], addr; |
477 | uint8_t maf_id, device_id; | |
478 | int i; | |
479 | ||
480 | /* | |
481 | * Use read id method to get device ID and other params. | |
482 | * For some NAND chips, controller can't report the correct | |
483 | * device ID by reading from DEVICE_ID register | |
484 | */ | |
485 | addr = MODE_11 | BANK(denali->flash_bank); | |
486 | index_addr(denali, addr | 0, 0x90); | |
487 | index_addr(denali, addr | 1, 0); | |
488 | for (i = 0; i < 8; i++) | |
3eb3e72a CLS |
489 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
490 | maf_id = id_bytes[0]; | |
491 | device_id = id_bytes[1]; | |
492 | ||
493 | if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & | |
494 | ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ | |
495 | if (get_onfi_nand_para(denali)) | |
496 | return -EIO; | |
497 | } else if (maf_id == 0xEC) { /* Samsung NAND */ | |
498 | get_samsung_nand_para(denali, device_id); | |
499 | } else if (maf_id == 0x98) { /* Toshiba NAND */ | |
500 | get_toshiba_nand_para(denali); | |
501 | } else if (maf_id == 0xAD) { /* Hynix NAND */ | |
502 | get_hynix_nand_para(denali, device_id); | |
503 | } | |
504 | ||
505 | find_valid_banks(denali); | |
506 | ||
507 | detect_partition_feature(denali); | |
508 | ||
d3963721 SW |
509 | /* |
510 | * If the user specified to override the default timings | |
3eb3e72a CLS |
511 | * with a specific ONFI mode, we apply those changes here. |
512 | */ | |
513 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | |
514 | nand_onfi_timing_set(denali, onfi_timing_mode); | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
d3963721 SW |
519 | /* |
520 | * validation function to verify that the controlling software is making | |
3eb3e72a CLS |
521 | * a valid request |
522 | */ | |
523 | static inline bool is_flash_bank_valid(int flash_bank) | |
524 | { | |
525 | return flash_bank >= 0 && flash_bank < 4; | |
526 | } | |
527 | ||
528 | static void denali_irq_init(struct denali_nand_info *denali) | |
529 | { | |
d3963721 | 530 | uint32_t int_mask; |
3eb3e72a CLS |
531 | int i; |
532 | ||
533 | /* Disable global interrupts */ | |
534 | writel(0, denali->flash_reg + GLOBAL_INT_ENABLE); | |
535 | ||
536 | int_mask = DENALI_IRQ_ALL; | |
537 | ||
538 | /* Clear all status bits */ | |
539 | for (i = 0; i < denali->max_banks; ++i) | |
540 | writel(0xFFFF, denali->flash_reg + INTR_STATUS(i)); | |
541 | ||
542 | denali_irq_enable(denali, int_mask); | |
543 | } | |
544 | ||
d3963721 SW |
545 | /* |
546 | * This helper function setups the registers for ECC and whether or not | |
547 | * the spare area will be transferred. | |
548 | */ | |
3eb3e72a CLS |
549 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
550 | bool transfer_spare) | |
551 | { | |
d3963721 | 552 | int ecc_en_flag, transfer_spare_flag; |
3eb3e72a CLS |
553 | |
554 | /* set ECC, transfer spare bits if needed */ | |
555 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | |
556 | transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0; | |
557 | ||
558 | /* Enable spare area/ECC per user's request. */ | |
559 | writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE); | |
560 | /* applicable for MAP01 only */ | |
561 | writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); | |
562 | } | |
563 | ||
d3963721 SW |
564 | /* |
565 | * sends a pipeline command operation to the controller. See the Denali NAND | |
3eb3e72a CLS |
566 | * controller's user guide for more information (section 4.2.3.6). |
567 | */ | |
568 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |
d3963721 SW |
569 | bool ecc_en, bool transfer_spare, |
570 | int access_type, int op) | |
3eb3e72a CLS |
571 | { |
572 | uint32_t addr, cmd, irq_status; | |
573 | static uint32_t page_count = 1; | |
574 | ||
575 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | |
576 | ||
3eb3e72a CLS |
577 | clear_interrupts(denali); |
578 | ||
579 | addr = BANK(denali->flash_bank) | denali->page; | |
580 | ||
581 | /* setup the acccess type */ | |
582 | cmd = MODE_10 | addr; | |
583 | index_addr(denali, cmd, access_type); | |
584 | ||
585 | /* setup the pipeline command */ | |
586 | index_addr(denali, cmd, 0x2000 | op | page_count); | |
587 | ||
588 | cmd = MODE_01 | addr; | |
589 | writel(cmd, denali->flash_mem + INDEX_CTRL_REG); | |
590 | ||
591 | if (op == DENALI_READ) { | |
592 | /* wait for command to be accepted */ | |
593 | irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP); | |
594 | ||
595 | if (irq_status == 0) | |
596 | return -EIO; | |
597 | } | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /* helper function that simply writes a buffer to the flash */ | |
603 | static int write_data_to_flash_mem(struct denali_nand_info *denali, | |
d3963721 | 604 | const uint8_t *buf, int len) |
3eb3e72a | 605 | { |
d3963721 SW |
606 | uint32_t *buf32; |
607 | int i; | |
3eb3e72a | 608 | |
d3963721 SW |
609 | /* |
610 | * verify that the len is a multiple of 4. | |
611 | * see comment in read_data_from_flash_mem() | |
612 | */ | |
3eb3e72a CLS |
613 | BUG_ON((len % 4) != 0); |
614 | ||
615 | /* write the data to the flash memory */ | |
616 | buf32 = (uint32_t *)buf; | |
617 | for (i = 0; i < len / 4; i++) | |
618 | writel(*buf32++, denali->flash_mem + INDEX_DATA_REG); | |
619 | return i * 4; /* intent is to return the number of bytes read */ | |
620 | } | |
621 | ||
622 | /* helper function that simply reads a buffer from the flash */ | |
623 | static int read_data_from_flash_mem(struct denali_nand_info *denali, | |
d3963721 | 624 | uint8_t *buf, int len) |
3eb3e72a | 625 | { |
d3963721 SW |
626 | uint32_t *buf32; |
627 | int i; | |
3eb3e72a CLS |
628 | |
629 | /* | |
d3963721 SW |
630 | * we assume that len will be a multiple of 4, if not it would be nice |
631 | * to know about it ASAP rather than have random failures... | |
632 | * This assumption is based on the fact that this function is designed | |
633 | * to be used to read flash pages, which are typically multiples of 4. | |
3eb3e72a | 634 | */ |
3eb3e72a CLS |
635 | BUG_ON((len % 4) != 0); |
636 | ||
637 | /* transfer the data from the flash */ | |
638 | buf32 = (uint32_t *)buf; | |
639 | for (i = 0; i < len / 4; i++) | |
640 | *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG); | |
641 | ||
642 | return i * 4; /* intent is to return the number of bytes read */ | |
643 | } | |
644 | ||
645 | static void denali_mode_main_access(struct denali_nand_info *denali) | |
646 | { | |
647 | uint32_t addr, cmd; | |
648 | ||
649 | addr = BANK(denali->flash_bank) | denali->page; | |
650 | cmd = MODE_10 | addr; | |
651 | index_addr(denali, cmd, MAIN_ACCESS); | |
652 | } | |
653 | ||
654 | static void denali_mode_main_spare_access(struct denali_nand_info *denali) | |
655 | { | |
656 | uint32_t addr, cmd; | |
657 | ||
658 | addr = BANK(denali->flash_bank) | denali->page; | |
659 | cmd = MODE_10 | addr; | |
660 | index_addr(denali, cmd, MAIN_SPARE_ACCESS); | |
661 | } | |
662 | ||
663 | /* writes OOB data to the device */ | |
664 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
665 | { | |
666 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
667 | uint32_t irq_status; | |
668 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | | |
669 | INTR_STATUS__PROGRAM_FAIL; | |
670 | int status = 0; | |
671 | ||
672 | denali->page = page; | |
673 | ||
674 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, | |
675 | DENALI_WRITE) == 0) { | |
676 | write_data_to_flash_mem(denali, buf, mtd->oobsize); | |
677 | ||
678 | /* wait for operation to complete */ | |
679 | irq_status = wait_for_irq(denali, irq_mask); | |
680 | ||
681 | if (irq_status == 0) { | |
682 | dev_err(denali->dev, "OOB write failed\n"); | |
683 | status = -EIO; | |
684 | } | |
685 | } else { | |
686 | printf("unable to send pipeline command\n"); | |
687 | status = -EIO; | |
688 | } | |
689 | return status; | |
690 | } | |
691 | ||
692 | /* reads OOB data from the device */ | |
693 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |
694 | { | |
695 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
d3963721 SW |
696 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
697 | uint32_t irq_status, addr, cmd; | |
3eb3e72a CLS |
698 | |
699 | denali->page = page; | |
700 | ||
701 | if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, | |
702 | DENALI_READ) == 0) { | |
703 | read_data_from_flash_mem(denali, buf, mtd->oobsize); | |
704 | ||
d3963721 SW |
705 | /* |
706 | * wait for command to be accepted | |
707 | * can always use status0 bit as the | |
708 | * mask is identical for each bank. | |
709 | */ | |
3eb3e72a CLS |
710 | irq_status = wait_for_irq(denali, irq_mask); |
711 | ||
712 | if (irq_status == 0) | |
713 | printf("page on OOB timeout %d\n", denali->page); | |
714 | ||
d3963721 SW |
715 | /* |
716 | * We set the device back to MAIN_ACCESS here as I observed | |
3eb3e72a CLS |
717 | * instability with the controller if you do a block erase |
718 | * and the last transaction was a SPARE_ACCESS. Block erase | |
719 | * is reliable (according to the MTD test infrastructure) | |
720 | * if you are in MAIN_ACCESS. | |
721 | */ | |
722 | addr = BANK(denali->flash_bank) | denali->page; | |
723 | cmd = MODE_10 | addr; | |
724 | index_addr(denali, cmd, MAIN_ACCESS); | |
725 | } | |
726 | } | |
727 | ||
d3963721 SW |
728 | /* |
729 | * this function examines buffers to see if they contain data that | |
3eb3e72a CLS |
730 | * indicate that the buffer is part of an erased region of flash. |
731 | */ | |
732 | static bool is_erased(uint8_t *buf, int len) | |
733 | { | |
d3963721 SW |
734 | int i; |
735 | ||
3eb3e72a CLS |
736 | for (i = 0; i < len; i++) |
737 | if (buf[i] != 0xFF) | |
738 | return false; | |
739 | return true; | |
740 | } | |
741 | ||
742 | /* programs the controller to either enable/disable DMA transfers */ | |
743 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) | |
744 | { | |
d3963721 | 745 | writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
3eb3e72a CLS |
746 | readl(denali->flash_reg + DMA_ENABLE); |
747 | } | |
748 | ||
749 | /* setups the HW to perform the data DMA */ | |
750 | static void denali_setup_dma(struct denali_nand_info *denali, int op) | |
751 | { | |
752 | uint32_t mode; | |
753 | const int page_count = 1; | |
73b5b27b | 754 | uint64_t addr = (unsigned long)denali->buf.dma_buf; |
3eb3e72a CLS |
755 | |
756 | flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf)); | |
757 | ||
758 | /* For Denali controller that is 64 bit bus IP core */ | |
759 | #ifdef CONFIG_SYS_NAND_DENALI_64BIT | |
760 | mode = MODE_10 | BANK(denali->flash_bank) | denali->page; | |
761 | ||
762 | /* DMA is a three step process */ | |
763 | ||
764 | /* 1. setup transfer type, interrupt when complete, | |
765 | burst len = 64 bytes, the number of pages */ | |
766 | index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); | |
767 | ||
768 | /* 2. set memory low address bits 31:0 */ | |
769 | index_addr(denali, mode, addr); | |
770 | ||
771 | /* 3. set memory high address bits 64:32 */ | |
73b5b27b | 772 | index_addr(denali, mode, addr >> 32); |
3eb3e72a CLS |
773 | #else |
774 | mode = MODE_10 | BANK(denali->flash_bank); | |
775 | ||
776 | /* DMA is a four step process */ | |
777 | ||
778 | /* 1. setup transfer type and # of pages */ | |
779 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | |
780 | ||
781 | /* 2. set memory high address bits 23:8 */ | |
73b5b27b | 782 | index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200); |
3eb3e72a CLS |
783 | |
784 | /* 3. set memory low address bits 23:8 */ | |
d3963721 | 785 | index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); |
3eb3e72a | 786 | |
d3963721 | 787 | /* 4. interrupt when complete, burst len = 64 bytes */ |
3eb3e72a CLS |
788 | index_addr(denali, mode | 0x14000, 0x2400); |
789 | #endif | |
790 | } | |
791 | ||
792 | /* Common DMA function */ | |
793 | static uint32_t denali_dma_configuration(struct denali_nand_info *denali, | |
794 | uint32_t ops, bool raw_xfer, | |
795 | uint32_t irq_mask, int oob_required) | |
796 | { | |
797 | uint32_t irq_status = 0; | |
798 | /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */ | |
799 | setup_ecc_for_xfer(denali, !raw_xfer, oob_required); | |
800 | ||
801 | /* clear any previous interrupt flags */ | |
802 | clear_interrupts(denali); | |
803 | ||
804 | /* enable the DMA */ | |
805 | denali_enable_dma(denali, true); | |
806 | ||
807 | /* setup the DMA */ | |
808 | denali_setup_dma(denali, ops); | |
809 | ||
810 | /* wait for operation to complete */ | |
811 | irq_status = wait_for_irq(denali, irq_mask); | |
812 | ||
813 | /* if ECC fault happen, seems we need delay before turning off DMA. | |
814 | * If not, the controller will go into non responsive condition */ | |
815 | if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) | |
816 | udelay(100); | |
817 | ||
818 | /* disable the DMA */ | |
819 | denali_enable_dma(denali, false); | |
820 | ||
821 | return irq_status; | |
822 | } | |
823 | ||
824 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
825 | const uint8_t *buf, bool raw_xfer, int oob_required) | |
826 | { | |
827 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
828 | ||
829 | uint32_t irq_status = 0; | |
830 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; | |
831 | ||
832 | denali->status = 0; | |
833 | ||
834 | /* copy buffer into DMA buffer */ | |
835 | memcpy(denali->buf.dma_buf, buf, mtd->writesize); | |
836 | ||
837 | /* need extra memcpy for raw transfer */ | |
838 | if (raw_xfer) | |
839 | memcpy(denali->buf.dma_buf + mtd->writesize, | |
840 | chip->oob_poi, mtd->oobsize); | |
841 | ||
842 | /* setting up DMA */ | |
843 | irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer, | |
844 | irq_mask, oob_required); | |
845 | ||
846 | /* if timeout happen, error out */ | |
847 | if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { | |
848 | debug("DMA timeout for denali write_page\n"); | |
849 | denali->status = NAND_STATUS_FAIL; | |
850 | return -EIO; | |
851 | } | |
852 | ||
853 | if (irq_status & INTR_STATUS__LOCKED_BLK) { | |
854 | debug("Failed as write to locked block\n"); | |
855 | denali->status = NAND_STATUS_FAIL; | |
856 | return -EIO; | |
857 | } | |
858 | return 0; | |
859 | } | |
860 | ||
861 | /* NAND core entry points */ | |
862 | ||
863 | /* | |
864 | * this is the callback that the NAND core calls to write a page. Since | |
865 | * writing a page with ECC or without is similar, all the work is done | |
866 | * by write_page above. | |
867 | */ | |
868 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
81c77252 SW |
869 | const uint8_t *buf, int oob_required, |
870 | int page) | |
3eb3e72a CLS |
871 | { |
872 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
873 | ||
874 | /* | |
875 | * for regular page writes, we let HW handle all the ECC | |
876 | * data written to the device. | |
877 | */ | |
878 | if (oob_required) | |
879 | /* switch to main + spare access */ | |
880 | denali_mode_main_spare_access(denali); | |
881 | else | |
882 | /* switch to main access only */ | |
883 | denali_mode_main_access(denali); | |
884 | ||
885 | return write_page(mtd, chip, buf, false, oob_required); | |
886 | } | |
887 | ||
888 | /* | |
889 | * This is the callback that the NAND core calls to write a page without ECC. | |
890 | * raw access is similar to ECC page writes, so all the work is done in the | |
891 | * write_page() function above. | |
892 | */ | |
893 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
81c77252 SW |
894 | const uint8_t *buf, int oob_required, |
895 | int page) | |
3eb3e72a CLS |
896 | { |
897 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
898 | ||
899 | /* | |
900 | * for raw page writes, we want to disable ECC and simply write | |
901 | * whatever data is in the buffer. | |
902 | */ | |
903 | ||
904 | if (oob_required) | |
905 | /* switch to main + spare access */ | |
906 | denali_mode_main_spare_access(denali); | |
907 | else | |
908 | /* switch to main access only */ | |
909 | denali_mode_main_access(denali); | |
910 | ||
911 | return write_page(mtd, chip, buf, true, oob_required); | |
912 | } | |
913 | ||
914 | static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
915 | int page) | |
916 | { | |
917 | return write_oob_data(mtd, chip->oob_poi, page); | |
918 | } | |
919 | ||
920 | /* raw include ECC value and all the spare area */ | |
921 | static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
922 | uint8_t *buf, int oob_required, int page) | |
923 | { | |
924 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
925 | ||
926 | uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; | |
927 | ||
928 | if (denali->page != page) { | |
929 | debug("Missing NAND_CMD_READ0 command\n"); | |
930 | return -EIO; | |
931 | } | |
932 | ||
933 | if (oob_required) | |
934 | /* switch to main + spare access */ | |
935 | denali_mode_main_spare_access(denali); | |
936 | else | |
937 | /* switch to main access only */ | |
938 | denali_mode_main_access(denali); | |
939 | ||
940 | /* setting up the DMA where ecc_enable is false */ | |
941 | irq_status = denali_dma_configuration(denali, DENALI_READ, true, | |
942 | irq_mask, oob_required); | |
943 | ||
944 | /* if timeout happen, error out */ | |
945 | if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) { | |
946 | debug("DMA timeout for denali_read_page_raw\n"); | |
947 | return -EIO; | |
948 | } | |
949 | ||
950 | /* splitting the content to destination buffer holder */ | |
951 | memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize), | |
952 | mtd->oobsize); | |
953 | memcpy(buf, denali->buf.dma_buf, mtd->writesize); | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
959 | uint8_t *buf, int oob_required, int page) | |
960 | { | |
961 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
962 | uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP; | |
963 | ||
964 | if (denali->page != page) { | |
965 | debug("Missing NAND_CMD_READ0 command\n"); | |
966 | return -EIO; | |
967 | } | |
968 | ||
969 | if (oob_required) | |
970 | /* switch to main + spare access */ | |
971 | denali_mode_main_spare_access(denali); | |
972 | else | |
973 | /* switch to main access only */ | |
974 | denali_mode_main_access(denali); | |
975 | ||
976 | /* setting up the DMA where ecc_enable is true */ | |
977 | irq_status = denali_dma_configuration(denali, DENALI_READ, false, | |
978 | irq_mask, oob_required); | |
979 | ||
980 | memcpy(buf, denali->buf.dma_buf, mtd->writesize); | |
981 | ||
982 | /* check whether any ECC error */ | |
983 | if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) { | |
984 | /* is the ECC cause by erase page, check using read_page_raw */ | |
985 | debug(" Uncorrected ECC detected\n"); | |
986 | denali_read_page_raw(mtd, chip, buf, oob_required, | |
987 | denali->page); | |
988 | ||
989 | if (is_erased(buf, mtd->writesize) == true && | |
990 | is_erased(chip->oob_poi, mtd->oobsize) == true) { | |
991 | debug(" ECC error cause by erased block\n"); | |
992 | /* false alarm, return the 0xFF */ | |
993 | } else { | |
994 | return -EIO; | |
995 | } | |
996 | } | |
997 | memcpy(buf, denali->buf.dma_buf, mtd->writesize); | |
998 | return 0; | |
999 | } | |
1000 | ||
1001 | static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
1002 | int page) | |
1003 | { | |
1004 | read_oob_data(mtd, chip->oob_poi, page); | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static uint8_t denali_read_byte(struct mtd_info *mtd) | |
1010 | { | |
1011 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1012 | uint32_t addr, result; | |
1013 | ||
1014 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1015 | index_addr_read_data(denali, addr | 2, &result); | |
1016 | return (uint8_t)result & 0xFF; | |
1017 | } | |
1018 | ||
1019 | static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
1020 | { | |
1021 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1022 | uint32_t i, addr, result; | |
1023 | ||
1024 | /* delay for tR (data transfer from Flash array to data register) */ | |
1025 | udelay(25); | |
1026 | ||
1027 | /* ensure device completed else additional delay and polling */ | |
1028 | wait_for_irq(denali, INTR_STATUS__INT_ACT); | |
1029 | ||
1030 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | |
1031 | for (i = 0; i < len; i++) { | |
1032 | index_addr_read_data(denali, (uint32_t)addr | 2, &result); | |
1033 | write_byte_to_buf(denali, result); | |
1034 | } | |
1035 | memcpy(buf, denali->buf.buf, len); | |
1036 | } | |
1037 | ||
1038 | static void denali_select_chip(struct mtd_info *mtd, int chip) | |
1039 | { | |
1040 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1041 | ||
1042 | denali->flash_bank = chip; | |
1043 | } | |
1044 | ||
1045 | static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |
1046 | { | |
1047 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1048 | int status = denali->status; | |
d3963721 | 1049 | |
3eb3e72a CLS |
1050 | denali->status = 0; |
1051 | ||
1052 | return status; | |
1053 | } | |
1054 | ||
d3963721 | 1055 | static int denali_erase(struct mtd_info *mtd, int page) |
3eb3e72a CLS |
1056 | { |
1057 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
d3963721 | 1058 | |
3eb3e72a CLS |
1059 | uint32_t cmd, irq_status; |
1060 | ||
3eb3e72a CLS |
1061 | clear_interrupts(denali); |
1062 | ||
1063 | /* setup page read request for access type */ | |
1064 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | |
1065 | index_addr(denali, cmd, 0x1); | |
1066 | ||
1067 | /* wait for erase to complete or failure to occur */ | |
1068 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | | |
1069 | INTR_STATUS__ERASE_FAIL); | |
1070 | ||
1071 | if (irq_status & INTR_STATUS__ERASE_FAIL || | |
1072 | irq_status & INTR_STATUS__LOCKED_BLK) | |
d3963721 SW |
1073 | return NAND_STATUS_FAIL; |
1074 | ||
1075 | return 0; | |
3eb3e72a CLS |
1076 | } |
1077 | ||
1078 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | |
1079 | int page) | |
1080 | { | |
1081 | struct denali_nand_info *denali = mtd_to_denali(mtd); | |
1082 | uint32_t addr; | |
1083 | ||
1084 | switch (cmd) { | |
1085 | case NAND_CMD_PAGEPROG: | |
1086 | break; | |
1087 | case NAND_CMD_STATUS: | |
1088 | addr = MODE_11 | BANK(denali->flash_bank); | |
1089 | index_addr(denali, addr | 0, cmd); | |
1090 | break; | |
3eb3e72a | 1091 | case NAND_CMD_READID: |
05968e7c | 1092 | case NAND_CMD_PARAM: |
3eb3e72a | 1093 | reset_buf(denali); |
d3963721 SW |
1094 | /* |
1095 | * sometimes ManufactureId read from register is not right | |
3eb3e72a CLS |
1096 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1097 | * So here we send READID cmd to NAND insteand | |
d3963721 | 1098 | */ |
3eb3e72a CLS |
1099 | addr = MODE_11 | BANK(denali->flash_bank); |
1100 | index_addr(denali, addr | 0, cmd); | |
1101 | index_addr(denali, addr | 1, col & 0xFF); | |
05968e7c MY |
1102 | if (cmd == NAND_CMD_PARAM) |
1103 | udelay(50); | |
3eb3e72a | 1104 | break; |
ed3c980b MY |
1105 | case NAND_CMD_RNDOUT: |
1106 | addr = MODE_11 | BANK(denali->flash_bank); | |
1107 | index_addr(denali, addr | 0, cmd); | |
1108 | index_addr(denali, addr | 1, col & 0xFF); | |
1109 | index_addr(denali, addr | 1, col >> 8); | |
1110 | index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART); | |
1111 | break; | |
3eb3e72a CLS |
1112 | case NAND_CMD_READ0: |
1113 | case NAND_CMD_SEQIN: | |
1114 | denali->page = page; | |
1115 | break; | |
1116 | case NAND_CMD_RESET: | |
1117 | reset_bank(denali); | |
1118 | break; | |
1119 | case NAND_CMD_READOOB: | |
1120 | /* TODO: Read OOB data */ | |
1121 | break; | |
1122 | case NAND_CMD_ERASE1: | |
1123 | /* | |
1124 | * supporting block erase only, not multiblock erase as | |
1125 | * it will cross plane and software need complex calculation | |
1126 | * to identify the block count for the cross plane | |
1127 | */ | |
1128 | denali_erase(mtd, page); | |
1129 | break; | |
1130 | case NAND_CMD_ERASE2: | |
1131 | /* nothing to do here as it was done during NAND_CMD_ERASE1 */ | |
1132 | break; | |
1133 | case NAND_CMD_UNLOCK1: | |
1134 | addr = MODE_10 | BANK(denali->flash_bank) | page; | |
1135 | index_addr(denali, addr | 0, DENALI_UNLOCK_START); | |
1136 | break; | |
1137 | case NAND_CMD_UNLOCK2: | |
1138 | addr = MODE_10 | BANK(denali->flash_bank) | page; | |
1139 | index_addr(denali, addr | 0, DENALI_UNLOCK_END); | |
1140 | break; | |
1141 | case NAND_CMD_LOCK: | |
1142 | addr = MODE_10 | BANK(denali->flash_bank); | |
1143 | index_addr(denali, addr | 0, DENALI_LOCK); | |
1144 | break; | |
1145 | default: | |
1146 | printf(": unsupported command received 0x%x\n", cmd); | |
1147 | break; | |
1148 | } | |
1149 | } | |
1150 | /* end NAND core entry points */ | |
1151 | ||
1152 | /* Initialization code to bring the device up to a known good state */ | |
1153 | static void denali_hw_init(struct denali_nand_info *denali) | |
1154 | { | |
1155 | /* | |
1156 | * tell driver how many bit controller will skip before writing | |
1157 | * ECC code in OOB. This is normally used for bad block marker | |
1158 | */ | |
1159 | writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES, | |
1160 | denali->flash_reg + SPARE_AREA_SKIP_BYTES); | |
1161 | detect_max_banks(denali); | |
1162 | denali_nand_reset(denali); | |
1163 | writel(0x0F, denali->flash_reg + RB_PIN_ENABLED); | |
1164 | writel(CHIP_EN_DONT_CARE__FLAG, | |
1165 | denali->flash_reg + CHIP_ENABLE_DONT_CARE); | |
1166 | writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER); | |
1167 | ||
1168 | /* Should set value for these registers when init */ | |
1169 | writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES); | |
1170 | writel(1, denali->flash_reg + ECC_ENABLE); | |
1171 | denali_nand_timing_set(denali); | |
1172 | denali_irq_init(denali); | |
1173 | } | |
1174 | ||
1175 | static struct nand_ecclayout nand_oob; | |
1176 | ||
65e4145a | 1177 | static int denali_init(struct denali_nand_info *denali) |
3eb3e72a | 1178 | { |
65e4145a | 1179 | int ret; |
3eb3e72a | 1180 | |
65e4145a | 1181 | denali_hw_init(denali); |
3eb3e72a | 1182 | |
65e4145a MY |
1183 | denali->mtd->name = "denali-nand"; |
1184 | denali->mtd->owner = THIS_MODULE; | |
3eb3e72a | 1185 | |
65e4145a MY |
1186 | /* register the driver with the NAND core subsystem */ |
1187 | denali->nand.select_chip = denali_select_chip; | |
1188 | denali->nand.cmdfunc = denali_cmdfunc; | |
1189 | denali->nand.read_byte = denali_read_byte; | |
1190 | denali->nand.read_buf = denali_read_buf; | |
1191 | denali->nand.waitfunc = denali_waitfunc; | |
1192 | ||
1193 | /* | |
1194 | * scan for NAND devices attached to the controller | |
1195 | * this is the first stage in a two step process to register | |
1196 | * with the nand subsystem | |
1197 | */ | |
1198 | if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) { | |
1199 | ret = -ENXIO; | |
1200 | goto fail; | |
1201 | } | |
3eb3e72a CLS |
1202 | |
1203 | #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT | |
1204 | /* check whether flash got BBT table (located at end of flash). As we | |
1205 | * use NAND_BBT_NO_OOB, the BBT page will start with | |
1206 | * bbt_pattern. We will have mirror pattern too */ | |
65e4145a | 1207 | denali->nand.bbt_options |= NAND_BBT_USE_FLASH; |
3eb3e72a CLS |
1208 | /* |
1209 | * We are using main + spare with ECC support. As BBT need ECC support, | |
1210 | * we need to ensure BBT code don't write to OOB for the BBT pattern. | |
1211 | * All BBT info will be stored into data area with ECC support. | |
1212 | */ | |
65e4145a | 1213 | denali->nand.bbt_options |= NAND_BBT_NO_OOB; |
3eb3e72a CLS |
1214 | #endif |
1215 | ||
65e4145a MY |
1216 | denali->nand.ecc.mode = NAND_ECC_HW; |
1217 | denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE; | |
1218 | ||
d3963721 SW |
1219 | /* no subpage writes on denali */ |
1220 | denali->nand.options |= NAND_NO_SUBPAGE_WRITE; | |
1221 | ||
3eb3e72a CLS |
1222 | /* |
1223 | * Tell driver the ecc strength. This register may be already set | |
1224 | * correctly. So we read this value out. | |
1225 | */ | |
65e4145a MY |
1226 | denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION); |
1227 | switch (denali->nand.ecc.size) { | |
3eb3e72a | 1228 | case 512: |
65e4145a MY |
1229 | denali->nand.ecc.bytes = |
1230 | (denali->nand.ecc.strength * 13 + 15) / 16 * 2; | |
3eb3e72a CLS |
1231 | break; |
1232 | case 1024: | |
65e4145a MY |
1233 | denali->nand.ecc.bytes = |
1234 | (denali->nand.ecc.strength * 14 + 15) / 16 * 2; | |
3eb3e72a CLS |
1235 | break; |
1236 | default: | |
1237 | pr_err("Unsupported ECC size\n"); | |
65e4145a MY |
1238 | ret = -EINVAL; |
1239 | goto fail; | |
3eb3e72a | 1240 | } |
65e4145a MY |
1241 | nand_oob.eccbytes = denali->nand.ecc.bytes; |
1242 | denali->nand.ecc.layout = &nand_oob; | |
1243 | ||
f09eb52b MY |
1244 | writel(denali->mtd->erasesize / denali->mtd->writesize, |
1245 | denali->flash_reg + PAGES_PER_BLOCK); | |
1246 | writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0, | |
1247 | denali->flash_reg + DEVICE_WIDTH); | |
1248 | writel(denali->mtd->writesize, | |
1249 | denali->flash_reg + DEVICE_MAIN_AREA_SIZE); | |
1250 | writel(denali->mtd->oobsize, | |
1251 | denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | |
1252 | if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0) | |
1253 | writel(1, denali->flash_reg + DEVICES_CONNECTED); | |
1254 | ||
65e4145a MY |
1255 | /* override the default operations */ |
1256 | denali->nand.ecc.read_page = denali_read_page; | |
1257 | denali->nand.ecc.read_page_raw = denali_read_page_raw; | |
1258 | denali->nand.ecc.write_page = denali_write_page; | |
1259 | denali->nand.ecc.write_page_raw = denali_write_page_raw; | |
1260 | denali->nand.ecc.read_oob = denali_read_oob; | |
1261 | denali->nand.ecc.write_oob = denali_write_oob; | |
1262 | ||
1263 | if (nand_scan_tail(denali->mtd)) { | |
1264 | ret = -ENXIO; | |
1265 | goto fail; | |
1266 | } | |
1267 | ||
b616d9b0 | 1268 | ret = nand_register(0, denali->mtd); |
65e4145a MY |
1269 | |
1270 | fail: | |
1271 | return ret; | |
1272 | } | |
1273 | ||
1274 | static int __board_nand_init(void) | |
1275 | { | |
1276 | struct denali_nand_info *denali; | |
1277 | ||
1278 | denali = kzalloc(sizeof(*denali), GFP_KERNEL); | |
1279 | if (!denali) | |
1280 | return -ENOMEM; | |
1281 | ||
1282 | /* | |
1283 | * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible | |
1284 | * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c | |
1285 | * still provides a "struct mtd_info nand_info" instance. | |
1286 | */ | |
b616d9b0 | 1287 | denali->mtd = &denali->nand.mtd; |
65e4145a MY |
1288 | |
1289 | /* | |
1290 | * In the future, these base addresses should be taken from | |
1291 | * Device Tree or platform data. | |
1292 | */ | |
1293 | denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; | |
1294 | denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; | |
1295 | ||
1296 | return denali_init(denali); | |
3eb3e72a CLS |
1297 | } |
1298 | ||
65e4145a | 1299 | void board_nand_init(void) |
3eb3e72a | 1300 | { |
65e4145a MY |
1301 | if (__board_nand_init() < 0) |
1302 | pr_warn("Failed to initialize Denali NAND controller.\n"); | |
3eb3e72a | 1303 | } |