]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mtd/nand/fsl_ifc_nand.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged
[people/ms/u-boot.git] / drivers / mtd / nand / fsl_ifc_nand.c
CommitLineData
52f90dad
DD		 1/* Integrated Flash Controller NAND Machine Driver
2 *
5f720b85 3 * Copyright (c) 2012 Freescale Semiconductor, Inc
52f90dad
DD		 4 *
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <common.h>
23#include <malloc.h>
24
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/nand_ecc.h>
28
29#include <asm/io.h>
30#include <asm/errno.h>
31#include <asm/fsl_ifc.h>
32
79da5e3d 33#define FSL_IFC_V1_1_0 0x01010000
52f90dad
DD		 34#define MAX_BANKS 4
35#define ERR_BYTE 0xFF /* Value returned for read bytes
36 when read failed */
37#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
38 NAND Machine */
39
40struct fsl_ifc_ctrl;
41
42/* mtd information per set */
43struct fsl_ifc_mtd {
44 struct mtd_info mtd;
45 struct nand_chip chip;
46 struct fsl_ifc_ctrl *ctrl;
47
48 struct device *dev;
49 int bank; /* Chip select bank number */
50 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
51 u8 __iomem *vbase; /* Chip select base virtual address */
52};
53
54/* overview of the fsl ifc controller */
55struct fsl_ifc_ctrl {
56 struct nand_hw_control controller;
57 struct fsl_ifc_mtd *chips[MAX_BANKS];
58
59 /* device info */
60 struct fsl_ifc *regs;
61 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
62 unsigned int cs_nand; /* On which chipsel NAND is connected */
63 unsigned int page; /* Last page written to / read from */
64 unsigned int read_bytes; /* Number of bytes read during command */
65 unsigned int column; /* Saved column from SEQIN */
66 unsigned int index; /* Pointer to next byte to 'read' */
67 unsigned int status; /* status read from NEESR after last op */
68 unsigned int oob; /* Non zero if operating on OOB data */
69 unsigned int eccread; /* Non zero for a full-page ECC read */
70};
71
72static struct fsl_ifc_ctrl *ifc_ctrl;
73
74/* 512-byte page with 4-bit ECC, 8-bit */
75static struct nand_ecclayout oob_512_8bit_ecc4 = {
76 .eccbytes = 8,
77 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
78 .oobfree = { {0, 5}, {6, 2} },
79};
80
81/* 512-byte page with 4-bit ECC, 16-bit */
82static struct nand_ecclayout oob_512_16bit_ecc4 = {
83 .eccbytes = 8,
84 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
85 .oobfree = { {2, 6}, },
86};
87
88/* 2048-byte page size with 4-bit ECC */
89static struct nand_ecclayout oob_2048_ecc4 = {
90 .eccbytes = 32,
91 .eccpos = {
92 8, 9, 10, 11, 12, 13, 14, 15,
93 16, 17, 18, 19, 20, 21, 22, 23,
94 24, 25, 26, 27, 28, 29, 30, 31,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 },
97 .oobfree = { {2, 6}, {40, 24} },
98};
99
100/* 4096-byte page size with 4-bit ECC */
101static struct nand_ecclayout oob_4096_ecc4 = {
102 .eccbytes = 64,
103 .eccpos = {
104 8, 9, 10, 11, 12, 13, 14, 15,
105 16, 17, 18, 19, 20, 21, 22, 23,
106 24, 25, 26, 27, 28, 29, 30, 31,
107 32, 33, 34, 35, 36, 37, 38, 39,
108 40, 41, 42, 43, 44, 45, 46, 47,
109 48, 49, 50, 51, 52, 53, 54, 55,
110 56, 57, 58, 59, 60, 61, 62, 63,
111 64, 65, 66, 67, 68, 69, 70, 71,
112 },
113 .oobfree = { {2, 6}, {72, 56} },
114};
115
116/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
117static struct nand_ecclayout oob_4096_ecc8 = {
118 .eccbytes = 128,
119 .eccpos = {
120 8, 9, 10, 11, 12, 13, 14, 15,
121 16, 17, 18, 19, 20, 21, 22, 23,
122 24, 25, 26, 27, 28, 29, 30, 31,
123 32, 33, 34, 35, 36, 37, 38, 39,
124 40, 41, 42, 43, 44, 45, 46, 47,
125 48, 49, 50, 51, 52, 53, 54, 55,
126 56, 57, 58, 59, 60, 61, 62, 63,
127 64, 65, 66, 67, 68, 69, 70, 71,
128 72, 73, 74, 75, 76, 77, 78, 79,
129 80, 81, 82, 83, 84, 85, 86, 87,
130 88, 89, 90, 91, 92, 93, 94, 95,
131 96, 97, 98, 99, 100, 101, 102, 103,
132 104, 105, 106, 107, 108, 109, 110, 111,
133 112, 113, 114, 115, 116, 117, 118, 119,
134 120, 121, 122, 123, 124, 125, 126, 127,
135 128, 129, 130, 131, 132, 133, 134, 135,
136 },
137 .oobfree = { {2, 6}, {136, 82} },
138};
139
140
141/*
142 * Generic flash bbt descriptors
143 */
144static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
145static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
146
147static struct nand_bbt_descr bbt_main_descr = {
148 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
149 NAND_BBT_2BIT | NAND_BBT_VERSION,
150 .offs = 2, /* 0 on 8-bit small page */
151 .len = 4,
152 .veroffs = 6,
153 .maxblocks = 4,
154 .pattern = bbt_pattern,
155};
156
157static struct nand_bbt_descr bbt_mirror_descr = {
158 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
159 NAND_BBT_2BIT | NAND_BBT_VERSION,
160 .offs = 2, /* 0 on 8-bit small page */
161 .len = 4,
162 .veroffs = 6,
163 .maxblocks = 4,
164 .pattern = mirror_pattern,
165};
166
167/*
168 * Set up the IFC hardware block and page address fields, and the ifc nand
169 * structure addr field to point to the correct IFC buffer in memory
170 */
171static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
172{
173 struct nand_chip *chip = mtd->priv;
174 struct fsl_ifc_mtd *priv = chip->priv;
175 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
176 struct fsl_ifc *ifc = ctrl->regs;
177 int buf_num;
178
179 ctrl->page = page_addr;
180
181 /* Program ROW0/COL0 */
182 out_be32(&ifc->ifc_nand.row0, page_addr);
183 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
184
185 buf_num = page_addr & priv->bufnum_mask;
186
187 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
188 ctrl->index = column;
189
190 /* for OOB data point to the second half of the buffer */
191 if (oob)
192 ctrl->index += mtd->writesize;
193}
194
195static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
196 unsigned int bufnum)
197{
198 struct nand_chip *chip = mtd->priv;
199 struct fsl_ifc_mtd *priv = chip->priv;
200 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
201 u32 __iomem *main = (u32 *)addr;
202 u8 __iomem *oob = addr + mtd->writesize;
203 int i;
204
205 for (i = 0; i < mtd->writesize / 4; i++) {
206 if (__raw_readl(&main[i]) != 0xffffffff)
207 return 0;
208 }
209
210 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
211 int pos = chip->ecc.layout->eccpos[i];
212
213 if (__raw_readb(&oob[pos]) != 0xff)
214 return 0;
215 }
216
217 return 1;
218}
219
220/* returns nonzero if entire page is blank */
221static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
222 u32 *eccstat, unsigned int bufnum)
223{
224 u32 reg = eccstat[bufnum / 4];
5f720b85
PK		 225 int errors;
226
227 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
52f90dad 228
5f720b85 229 return errors;
52f90dad
DD		 230}
231
232/*
233 * execute IFC NAND command and wait for it to complete
234 */
235static int fsl_ifc_run_command(struct mtd_info *mtd)
236{
237 struct nand_chip *chip = mtd->priv;
238 struct fsl_ifc_mtd *priv = chip->priv;
239 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
240 struct fsl_ifc *ifc = ctrl->regs;
241 long long end_tick;
242 u32 eccstat[4];
243 int i;
244
245 /* set the chip select for NAND Transaction */
246 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
247
248 /* start read/write seq */
249 out_be32(&ifc->ifc_nand.nandseq_strt,
250 IFC_NAND_SEQ_STRT_FIR_STRT);
251
252 /* wait for NAND Machine complete flag or timeout */
253 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
254
255 while (end_tick > get_ticks()) {
256 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
257
258 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
259 break;
260 }
261
262 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
263
264 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
265 printf("%s: Flash Time Out Error\n", __func__);
266 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
267 printf("%s: Write Protect Error\n", __func__);
268
269 if (ctrl->eccread) {
5f720b85
PK		 270 int errors;
271 int bufnum = ctrl->page & priv->bufnum_mask;
272 int sector = bufnum * chip->ecc.steps;
273 int sector_end = sector + chip->ecc.steps - 1;
52f90dad 274
5f720b85 275 for (i = sector / 4; i <= sector_end / 4; i++)
52f90dad
DD		 276 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
277
5f720b85
PK		 278 for (i = sector; i <= sector_end; i++) {
279 errors = check_read_ecc(mtd, ctrl, eccstat, i);
280
281 if (errors == 15) {
282 /*
283 * Uncorrectable error.
284 * OK only if the whole page is blank.
285 *
286 * We disable ECCER reporting due to erratum
287 * IFC-A002770 -- so report it now if we
288 * see an uncorrectable error in ECCSTAT.
289 */
290 if (!is_blank(mtd, ctrl, bufnum))
291 ctrl->status |=
292 IFC_NAND_EVTER_STAT_ECCER;
52f90dad 293 break;
5f720b85
PK		 294 }
295
296 mtd->ecc_stats.corrected += errors;
52f90dad
DD		 297 }
298
299 ctrl->eccread = 0;
300 }
301
302 /* returns 0 on success otherwise non-zero) */
303 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
304}
305
306static void fsl_ifc_do_read(struct nand_chip *chip,
307 int oob,
308 struct mtd_info *mtd)
309{
310 struct fsl_ifc_mtd *priv = chip->priv;
311 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
312 struct fsl_ifc *ifc = ctrl->regs;
313
314 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
315 if (mtd->writesize > 512) {
316 out_be32(&ifc->ifc_nand.nand_fir0,
317 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
318 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
319 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
320 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
321 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
322 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
323
324 out_be32(&ifc->ifc_nand.nand_fcr0,
325 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
326 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
327 } else {
328 out_be32(&ifc->ifc_nand.nand_fir0,
329 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
330 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
331 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
332 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
333
334 if (oob)
335 out_be32(&ifc->ifc_nand.nand_fcr0,
336 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
337 else
338 out_be32(&ifc->ifc_nand.nand_fcr0,
339 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
340 }
341}
342
343/* cmdfunc send commands to the IFC NAND Machine */
344static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
345 int column, int page_addr)
346{
347 struct nand_chip *chip = mtd->priv;
348 struct fsl_ifc_mtd *priv = chip->priv;
349 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
350 struct fsl_ifc *ifc = ctrl->regs;
351
352 /* clear the read buffer */
353 ctrl->read_bytes = 0;
354 if (command != NAND_CMD_PAGEPROG)
355 ctrl->index = 0;
356
357 switch (command) {
358 /* READ0 read the entire buffer to use hardware ECC. */
359 case NAND_CMD_READ0: {
360 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
361 set_addr(mtd, 0, page_addr, 0);
362
363 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
364 ctrl->index += column;
365
366 if (chip->ecc.mode == NAND_ECC_HW)
367 ctrl->eccread = 1;
368
369 fsl_ifc_do_read(chip, 0, mtd);
370 fsl_ifc_run_command(mtd);
371 return;
372 }
373
374 /* READOOB reads only the OOB because no ECC is performed. */
375 case NAND_CMD_READOOB:
376 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
377 set_addr(mtd, column, page_addr, 1);
378
379 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
380
381 fsl_ifc_do_read(chip, 1, mtd);
382 fsl_ifc_run_command(mtd);
383
384 return;
385
386 /* READID must read all possible bytes while CEB is active */
387 case NAND_CMD_READID:
807fc702
PK		 388 case NAND_CMD_PARAM: {
389 int timing = IFC_FIR_OP_RB;
390 if (command == NAND_CMD_PARAM)
391 timing = IFC_FIR_OP_RBCD;
392
52f90dad
DD		 393 out_be32(&ifc->ifc_nand.nand_fir0,
394 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
395 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
807fc702 396 (timing << IFC_NAND_FIR0_OP2_SHIFT));
52f90dad 397 out_be32(&ifc->ifc_nand.nand_fcr0,
807fc702
PK		 398 command << IFC_NAND_FCR0_CMD0_SHIFT);
399 out_be32(&ifc->ifc_nand.row3, column);
400
401 /*
402 * although currently it's 8 bytes for READID, we always read
403 * the maximum 256 bytes(for PARAM)
404 */
405 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
406 ctrl->read_bytes = 256;
52f90dad
DD		 407
408 set_addr(mtd, 0, 0, 0);
409 fsl_ifc_run_command(mtd);
410 return;
807fc702 411 }
52f90dad
DD		 412
413 /* ERASE1 stores the block and page address */
414 case NAND_CMD_ERASE1:
415 set_addr(mtd, 0, page_addr, 0);
416 return;
417
418 /* ERASE2 uses the block and page address from ERASE1 */
419 case NAND_CMD_ERASE2:
420 out_be32(&ifc->ifc_nand.nand_fir0,
421 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
422 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
423 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
424
425 out_be32(&ifc->ifc_nand.nand_fcr0,
426 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
427 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
428
429 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
430 ctrl->read_bytes = 0;
431 fsl_ifc_run_command(mtd);
432 return;
433
434 /* SEQIN sets up the addr buffer and all registers except the length */
435 case NAND_CMD_SEQIN: {
436 u32 nand_fcr0;
437 ctrl->column = column;
438 ctrl->oob = 0;
439
440 if (mtd->writesize > 512) {
441 nand_fcr0 =
442 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
443 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
444
445 out_be32(&ifc->ifc_nand.nand_fir0,
446 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
447 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
448 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
449 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
450 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
451 out_be32(&ifc->ifc_nand.nand_fir1, 0);
452 } else {
453 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
454 IFC_NAND_FCR0_CMD1_SHIFT) |
455 (NAND_CMD_SEQIN <<
456 IFC_NAND_FCR0_CMD2_SHIFT));
457
458 out_be32(&ifc->ifc_nand.nand_fir0,
459 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
460 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
461 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
462 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
463 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
464 out_be32(&ifc->ifc_nand.nand_fir1,
465 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
466
d9036128
PK		 467 if (column >= mtd->writesize)
468 nand_fcr0 |=
469 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
470 else
471 nand_fcr0 |=
472 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
52f90dad
DD		 473 }
474
d9036128
PK		 475 if (column >= mtd->writesize) {
476 /* OOB area --> READOOB */
477 column -= mtd->writesize;
478 ctrl->oob = 1;
479 }
52f90dad
DD		 480 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
481 set_addr(mtd, column, page_addr, ctrl->oob);
482 return;
483 }
484
485 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
486 case NAND_CMD_PAGEPROG:
487 if (ctrl->oob)
d9036128
PK		 488 out_be32(&ifc->ifc_nand.nand_fbcr,
489 ctrl->index - ctrl->column);
52f90dad
DD		 490 else
491 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
492
493 fsl_ifc_run_command(mtd);
494 return;
495
496 case NAND_CMD_STATUS:
497 out_be32(&ifc->ifc_nand.nand_fir0,
498 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
499 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
500 out_be32(&ifc->ifc_nand.nand_fcr0,
501 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
502 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
503 set_addr(mtd, 0, 0, 0);
504 ctrl->read_bytes = 1;
505
506 fsl_ifc_run_command(mtd);
507
508 /* Chip sometimes reporting write protect even when it's not */
509 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
510 return;
511
512 case NAND_CMD_RESET:
513 out_be32(&ifc->ifc_nand.nand_fir0,
514 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
515 out_be32(&ifc->ifc_nand.nand_fcr0,
516 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
517 fsl_ifc_run_command(mtd);
518 return;
519
520 default:
521 printf("%s: error, unsupported command 0x%x.\n",
522 __func__, command);
523 }
524}
525
526/*
527 * Write buf to the IFC NAND Controller Data Buffer
528 */
529static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
530{
531 struct nand_chip *chip = mtd->priv;
532 struct fsl_ifc_mtd *priv = chip->priv;
533 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
534 unsigned int bufsize = mtd->writesize + mtd->oobsize;
535
536 if (len <= 0) {
537 printf("%s of %d bytes", __func__, len);
538 ctrl->status = 0;
539 return;
540 }
541
542 if ((unsigned int)len > bufsize - ctrl->index) {
543 printf("%s beyond end of buffer "
544 "(%d requested, %u available)\n",
545 __func__, len, bufsize - ctrl->index);
546 len = bufsize - ctrl->index;
547 }
548
549 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
550 ctrl->index += len;
551}
552
553/*
554 * read a byte from either the IFC hardware buffer if it has any data left
555 * otherwise issue a command to read a single byte.
556 */
557static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
558{
559 struct nand_chip *chip = mtd->priv;
560 struct fsl_ifc_mtd *priv = chip->priv;
561 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
562
563 /* If there are still bytes in the IFC buffer, then use the
564 * next byte. */
565 if (ctrl->index < ctrl->read_bytes)
566 return in_8(&ctrl->addr[ctrl->index++]);
567
568 printf("%s beyond end of buffer\n", __func__);
569 return ERR_BYTE;
570}
571
572/*
573 * Read two bytes from the IFC hardware buffer
574 * read function for 16-bit buswith
575 */
576static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
577{
578 struct nand_chip *chip = mtd->priv;
579 struct fsl_ifc_mtd *priv = chip->priv;
580 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
581 uint16_t data;
582
583 /*
584 * If there are still bytes in the IFC buffer, then use the
585 * next byte.
586 */
587 if (ctrl->index < ctrl->read_bytes) {
588 data = in_be16((uint16_t *)&ctrl->
589 addr[ctrl->index]);
590 ctrl->index += 2;
591 return (uint8_t)data;
592 }
593
594 printf("%s beyond end of buffer\n", __func__);
595 return ERR_BYTE;
596}
597
598/*
599 * Read from the IFC Controller Data Buffer
600 */
601static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
602{
603 struct nand_chip *chip = mtd->priv;
604 struct fsl_ifc_mtd *priv = chip->priv;
605 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
606 int avail;
607
608 if (len < 0)
609 return;
610
611 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
612 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
613 ctrl->index += avail;
614
615 if (len > avail)
616 printf("%s beyond end of buffer "
617 "(%d requested, %d available)\n",
618 __func__, len, avail);
619}
620
621/*
622 * Verify buffer against the IFC Controller Data Buffer
623 */
624static int fsl_ifc_verify_buf(struct mtd_info *mtd,
625 const u_char *buf, int len)
626{
627 struct nand_chip *chip = mtd->priv;
628 struct fsl_ifc_mtd *priv = chip->priv;
629 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
630 int i;
631
632 if (len < 0) {
633 printf("%s of %d bytes", __func__, len);
634 return -EINVAL;
635 }
636
637 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
638 printf("%s beyond end of buffer "
639 "(%d requested, %u available)\n",
640 __func__, len, ctrl->read_bytes - ctrl->index);
641
642 ctrl->index = ctrl->read_bytes;
643 return -EINVAL;
644 }
645
646 for (i = 0; i < len; i++)
647 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
648 break;
649
650 ctrl->index += len;
651 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
652}
653
654/* This function is called after Program and Erase Operations to
655 * check for success or failure.
656 */
657static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
658{
659 struct fsl_ifc_mtd *priv = chip->priv;
660 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
661 struct fsl_ifc *ifc = ctrl->regs;
662 u32 nand_fsr;
663
664 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
665 return NAND_STATUS_FAIL;
666
667 /* Use READ_STATUS command, but wait for the device to be ready */
668 out_be32(&ifc->ifc_nand.nand_fir0,
669 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
670 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
671 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
672 IFC_NAND_FCR0_CMD0_SHIFT);
673 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
674 set_addr(mtd, 0, 0, 0);
675 ctrl->read_bytes = 1;
676
677 fsl_ifc_run_command(mtd);
678
679 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
680 return NAND_STATUS_FAIL;
681
682 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
683
684 /* Chip sometimes reporting write protect even when it's not */
685 nand_fsr = nand_fsr | NAND_STATUS_WP;
686 return nand_fsr;
687}
688
689static int fsl_ifc_read_page(struct mtd_info *mtd,
690 struct nand_chip *chip,
691 uint8_t *buf, int page)
692{
693 struct fsl_ifc_mtd *priv = chip->priv;
694 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
695
696 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
697 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
698
699 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
700 mtd->ecc_stats.failed++;
701
702 return 0;
703}
704
705/* ECC will be calculated automatically, and errors will be detected in
706 * waitfunc.
707 */
708static void fsl_ifc_write_page(struct mtd_info *mtd,
709 struct nand_chip *chip,
710 const uint8_t *buf)
711{
712 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
713 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
714}
715
716static void fsl_ifc_ctrl_init(void)
717{
718 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
719 if (!ifc_ctrl)
720 return;
721
722 ifc_ctrl->regs = IFC_BASE_ADDR;
723
724 /* clear event registers */
725 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
726 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
727
728 /* Enable error and event for any detected errors */
729 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
730 IFC_NAND_EVTER_EN_OPC_EN |
731 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
732 IFC_NAND_EVTER_EN_FTOER_EN |
733 IFC_NAND_EVTER_EN_WPER_EN);
734
735 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
736}
737
738static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
739{
740}
741
79da5e3d
PK		 742static void fsl_ifc_sram_init(void)
743{
744 struct fsl_ifc *ifc = ifc_ctrl->regs;
745 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
746 long long end_tick;
747
748 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
749
750 /* Save CSOR and CSOR_ext */
751 csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
752 csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
753
754 /* chage PageSize 8K and SpareSize 1K*/
755 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
756 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
757 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
758
759 /* READID */
760 out_be32(&ifc->ifc_nand.nand_fir0,
761 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
762 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
763 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
764 out_be32(&ifc->ifc_nand.nand_fcr0,
765 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
766 out_be32(&ifc->ifc_nand.row3, 0x0);
767
768 out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
769
770 /* Program ROW0/COL0 */
771 out_be32(&ifc->ifc_nand.row0, 0x0);
772 out_be32(&ifc->ifc_nand.col0, 0x0);
773
774 /* set the chip select for NAND Transaction */
775 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
776
777 /* start read seq */
778 out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
779
780 /* wait for NAND Machine complete flag or timeout */
781 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
782
783 while (end_tick > get_ticks()) {
784 ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
785
786 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
787 break;
788 }
789
790 out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
791
792 /* Restore CSOR and CSOR_ext */
793 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
794 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
795}
796
52f90dad
DD		 797int board_nand_init(struct nand_chip *nand)
798{
799 struct fsl_ifc_mtd *priv;
800 struct nand_ecclayout *layout;
79da5e3d 801 uint32_t cspr = 0, csor = 0, ver = 0;
52f90dad
DD		 802
803 if (!ifc_ctrl) {
804 fsl_ifc_ctrl_init();
805 if (!ifc_ctrl)
806 return -1;
807 }
808
809 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
810 if (!priv)
811 return -ENOMEM;
812
813 priv->ctrl = ifc_ctrl;
814 priv->vbase = nand->IO_ADDR_R;
815
816 /* Find which chip select it is connected to.
817 */
818 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
819 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
820
821 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
822 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
823
824 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
825 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
826 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
827 break;
828 }
829 }
830
831 if (priv->bank >= MAX_BANKS) {
832 printf("%s: address did not match any "
833 "chip selects\n", __func__);
76d067ac 834 kfree(priv);
52f90dad
DD		 835 return -ENODEV;
836 }
837
838 ifc_ctrl->chips[priv->bank] = priv;
839
840 /* fill in nand_chip structure */
841 /* set up function call table */
842
843 nand->write_buf = fsl_ifc_write_buf;
844 nand->read_buf = fsl_ifc_read_buf;
845 nand->verify_buf = fsl_ifc_verify_buf;
846 nand->select_chip = fsl_ifc_select_chip;
847 nand->cmdfunc = fsl_ifc_cmdfunc;
848 nand->waitfunc = fsl_ifc_wait;
849
850 /* set up nand options */
851 nand->bbt_td = &bbt_main_descr;
852 nand->bbt_md = &bbt_mirror_descr;
853
854 /* set up nand options */
855 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
cb04c772 856 NAND_USE_FLASH_BBT | NAND_NO_SUBPAGE_WRITE;
52f90dad
DD		 857
858 if (cspr & CSPR_PORT_SIZE_16) {
859 nand->read_byte = fsl_ifc_read_byte16;
860 nand->options |= NAND_BUSWIDTH_16;
861 } else {
862 nand->read_byte = fsl_ifc_read_byte;
863 }
864
865 nand->controller = &ifc_ctrl->controller;
866 nand->priv = priv;
867
868 nand->ecc.read_page = fsl_ifc_read_page;
869 nand->ecc.write_page = fsl_ifc_write_page;
870
871 /* Hardware generates ECC per 512 Bytes */
872 nand->ecc.size = 512;
873 nand->ecc.bytes = 8;
874
875 switch (csor & CSOR_NAND_PGS_MASK) {
876 case CSOR_NAND_PGS_512:
877 if (nand->options & NAND_BUSWIDTH_16) {
878 layout = &oob_512_16bit_ecc4;
879 } else {
880 layout = &oob_512_8bit_ecc4;
881
882 /* Avoid conflict with bad block marker */
883 bbt_main_descr.offs = 0;
884 bbt_mirror_descr.offs = 0;
885 }
886
887 priv->bufnum_mask = 15;
888 break;
889
890 case CSOR_NAND_PGS_2K:
891 layout = &oob_2048_ecc4;
892 priv->bufnum_mask = 3;
893 break;
894
895 case CSOR_NAND_PGS_4K:
896 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
897 CSOR_NAND_ECC_MODE_4) {
898 layout = &oob_4096_ecc4;
899 } else {
900 layout = &oob_4096_ecc8;
901 nand->ecc.bytes = 16;
902 }
903
904 priv->bufnum_mask = 1;
905 break;
906
907 default:
908 printf("ifc nand: bad csor %#x: bad page size\n", csor);
909 return -ENODEV;
910 }
911
912 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
913 if (csor & CSOR_NAND_ECC_DEC_EN) {
914 nand->ecc.mode = NAND_ECC_HW;
915 nand->ecc.layout = layout;
916 } else {
917 nand->ecc.mode = NAND_ECC_SOFT;
918 }
919
79da5e3d
PK		 920 ver = in_be32(&ifc_ctrl->regs->ifc_rev);
921 if (ver == FSL_IFC_V1_1_0)
922 fsl_ifc_sram_init();
923
52f90dad
DD		 924 return 0;
925}
"Das U-Boot" Source Tree