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cd9d2305 AV |
1 | /* |
2 | * FSL UPM NAND driver | |
3 | * | |
4 | * Copyright (C) 2007 MontaVista Software, Inc. | |
5 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <config.h> | |
14 | ||
15 | #if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_FSL_UPM) | |
16 | #include <common.h> | |
17 | #include <asm/io.h> | |
18 | #include <asm/errno.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/fsl_upm.h> | |
21 | #include <nand.h> | |
22 | ||
a75a57ef | 23 | static int fsl_upm_in_pattern; |
cd9d2305 AV |
24 | |
25 | static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) | |
26 | { | |
a75a57ef | 27 | clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); |
cd9d2305 AV |
28 | } |
29 | ||
30 | static void fsl_upm_end_pattern(struct fsl_upm *upm) | |
31 | { | |
a75a57ef WG |
32 | clrbits_be32(upm->mxmr, MxMR_OP_RUNP); |
33 | ||
34 | while (in_be32(upm->mxmr) & MxMR_OP_RUNP) | |
cd9d2305 AV |
35 | eieio(); |
36 | } | |
37 | ||
38 | static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd) | |
39 | { | |
a75a57ef WG |
40 | out_be32(upm->mar, cmd << (32 - width)); |
41 | switch (width) { | |
42 | case 8: | |
cd9d2305 | 43 | out_8(upm->io_addr, 0x0); |
a75a57ef WG |
44 | break; |
45 | case 16: | |
46 | out_be16(upm->io_addr, 0x0); | |
47 | break; | |
48 | case 32: | |
49 | out_be32(upm->io_addr, 0x0); | |
50 | break; | |
cd9d2305 | 51 | } |
cd9d2305 AV |
52 | } |
53 | ||
a75a57ef | 54 | static void nand_hwcontrol (struct mtd_info *mtd, int cmd) |
cd9d2305 AV |
55 | { |
56 | struct nand_chip *chip = mtd->priv; | |
57 | struct fsl_upm_nand *fun = chip->priv; | |
58 | ||
a75a57ef WG |
59 | switch (cmd) { |
60 | case NAND_CTL_SETCLE: | |
61 | fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); | |
62 | fsl_upm_in_pattern++; | |
63 | break; | |
64 | case NAND_CTL_SETALE: | |
65 | fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); | |
66 | fsl_upm_in_pattern++; | |
67 | break; | |
68 | case NAND_CTL_CLRCLE: | |
69 | case NAND_CTL_CLRALE: | |
70 | fsl_upm_end_pattern(&fun->upm); | |
71 | fsl_upm_in_pattern--; | |
72 | break; | |
cd9d2305 | 73 | } |
a75a57ef | 74 | } |
cd9d2305 | 75 | |
a75a57ef WG |
76 | static void nand_write_byte(struct mtd_info *mtd, u_char byte) |
77 | { | |
78 | struct nand_chip *chip = mtd->priv; | |
cd9d2305 | 79 | |
a75a57ef WG |
80 | if (fsl_upm_in_pattern) { |
81 | struct fsl_upm_nand *fun = chip->priv; | |
cd9d2305 | 82 | |
a75a57ef | 83 | fsl_upm_run_pattern(&fun->upm, fun->width, byte); |
cd9d2305 | 84 | |
cd9d2305 AV |
85 | /* |
86 | * Some boards/chips needs this. At least on MPC8360E-RDK we | |
87 | * need it. Probably weird chip, because I don't see any need | |
88 | * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are | |
89 | * 0-2 unexpected busy states per block read. | |
90 | */ | |
a75a57ef WG |
91 | if (fun->wait_pattern) { |
92 | while (!fun->dev_ready()) | |
93 | debug("unexpected busy state\n"); | |
94 | } | |
95 | } else { | |
96 | out_8(chip->IO_ADDR_W, byte); | |
cd9d2305 AV |
97 | } |
98 | } | |
99 | ||
cd9d2305 AV |
100 | static u8 nand_read_byte(struct mtd_info *mtd) |
101 | { | |
102 | struct nand_chip *chip = mtd->priv; | |
103 | ||
104 | return in_8(chip->IO_ADDR_R); | |
105 | } | |
106 | ||
107 | static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
108 | { | |
109 | int i; | |
110 | struct nand_chip *chip = mtd->priv; | |
111 | ||
112 | for (i = 0; i < len; i++) | |
113 | out_8(chip->IO_ADDR_W, buf[i]); | |
114 | } | |
115 | ||
116 | static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
117 | { | |
118 | int i; | |
119 | struct nand_chip *chip = mtd->priv; | |
120 | ||
121 | for (i = 0; i < len; i++) | |
122 | buf[i] = in_8(chip->IO_ADDR_R); | |
123 | } | |
124 | ||
125 | static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
126 | { | |
127 | int i; | |
128 | struct nand_chip *chip = mtd->priv; | |
129 | ||
130 | for (i = 0; i < len; i++) { | |
131 | if (buf[i] != in_8(chip->IO_ADDR_R)) | |
132 | return -EFAULT; | |
133 | } | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
cd9d2305 AV |
138 | static int nand_dev_ready(struct mtd_info *mtd) |
139 | { | |
140 | struct nand_chip *chip = mtd->priv; | |
141 | struct fsl_upm_nand *fun = chip->priv; | |
142 | ||
143 | return fun->dev_ready(); | |
144 | } | |
145 | ||
146 | int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) | |
147 | { | |
a75a57ef | 148 | if (fun->width != 8 && fun->width != 16 && fun->width != 32) |
cd9d2305 AV |
149 | return -ENOSYS; |
150 | ||
cd9d2305 AV |
151 | chip->priv = fun; |
152 | chip->chip_delay = fun->chip_delay; | |
153 | chip->eccmode = NAND_ECC_SOFT; | |
cd9d2305 AV |
154 | chip->hwcontrol = nand_hwcontrol; |
155 | chip->read_byte = nand_read_byte; | |
156 | chip->read_buf = nand_read_buf; | |
157 | chip->write_byte = nand_write_byte; | |
158 | chip->write_buf = nand_write_buf; | |
159 | chip->verify_buf = nand_verify_buf; | |
a75a57ef WG |
160 | if (fun->dev_ready) |
161 | chip->dev_ready = nand_dev_ready; | |
cd9d2305 AV |
162 | |
163 | return 0; | |
164 | } | |
165 | #endif /* CONFIG_CMD_NAND */ |