projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 205a0988 PW |
1 | /* |
| 2 | * (C) Copyright 2009 | |
| 3 | * Marvell Semiconductor <www.marvell.com> | |
| 4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | #include <common.h> | |
| 26 | #include <asm/io.h> | |
| 27 | #include <asm/arch/kirkwood.h> | |
| 28 | #include <nand.h> | |
| 29 | ||
| 30 | /* NAND Flash Soc registers */ | |
| 31 | struct kwnandf_registers { | |
| 32 | u32 rd_params; /* 0x10418 */ | |
| 33 | u32 wr_param; /* 0x1041c */ | |
| 34 | u8 pad[0x10470 - 0x1041c - 4]; | |
| 35 | u32 ctrl; /* 0x10470 */ | |
| 36 | }; | |
| 37 | ||
| 38 | static struct kwnandf_registers *nf_reg = | |
| 39 | (struct kwnandf_registers *)KW_NANDF_BASE; | |
| 40 | ||
| 41 | /* | |
| 42 | * hardware specific access to control-lines/bits | |
| 43 | */ | |
| 44 | #define NAND_ACTCEBOOT_BIT 0x02 | |
| 45 | ||
| 46 | static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, | |
| 47 | unsigned int ctrl) | |
| 48 | { | |
| 49 | struct nand_chip *nc = mtd->priv; | |
| 50 | u32 offs; | |
| 51 | ||
| 52 | if (cmd == NAND_CMD_NONE) | |
| 53 | return; | |
| 54 | ||
| 55 | if (ctrl & NAND_CLE) | |
| 56 | offs = (1 << 0); /* Commands with A[1:0] == 01 */ | |
| 57 | else if (ctrl & NAND_ALE) | |
| 58 | offs = (1 << 1); /* Addresses with A[1:0] == 10 */ | |
| 59 | else | |
| 60 | return; | |
| 61 | ||
| 62 | writeb(cmd, nc->IO_ADDR_W + offs); | |
| 63 | } | |
| 64 | ||
| 65 | void kw_nand_select_chip(struct mtd_info *mtd, int chip) | |
| 66 | { | |
| 67 | u32 data; | |
| 68 | ||
| 69 | data = readl(&nf_reg->ctrl); | |
| 70 | data |= NAND_ACTCEBOOT_BIT; | |
| 71 | writel(data, &nf_reg->ctrl); | |
| 72 | } | |
| 73 | ||
| 74 | int board_nand_init(struct nand_chip *nand) | |
| 75 | { | |
| 76 | nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; | |
| 77 | nand->ecc.mode = NAND_ECC_SOFT; | |
| 78 | nand->cmd_ctrl = kw_nand_hwcontrol; | |
| 79 | nand->chip_delay = 30; | |
| 80 | nand->select_chip = kw_nand_select_chip; | |
| 81 | return 0; | |
| 82 | } |