]>
Commit | Line | Data |
---|---|---|
0d4e8509 MV |
1 | /* |
2 | * Freescale i.MX28 NAND flash driver | |
3 | * | |
4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
5 | * on behalf of DENX Software Engineering GmbH | |
6 | * | |
7 | * Based on code from LTIB: | |
8 | * Freescale GPMI NFC NAND Flash Driver | |
9 | * | |
10 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
11 | * Copyright (C) 2008 Embedded Alley Solutions, Inc. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License along | |
24 | * with this program; if not, write to the Free Software Foundation, Inc., | |
25 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
26 | */ | |
27 | ||
28 | #include <linux/mtd/mtd.h> | |
29 | #include <linux/mtd/nand.h> | |
30 | #include <linux/types.h> | |
31 | #include <common.h> | |
32 | #include <malloc.h> | |
33 | #include <asm/errno.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/arch/clock.h> | |
36 | #include <asm/arch/imx-regs.h> | |
37 | #include <asm/arch/sys_proto.h> | |
38 | #include <asm/arch/dma.h> | |
39 | ||
40 | #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 | |
41 | ||
42 | #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512 | |
43 | #define MXS_NAND_METADATA_SIZE 10 | |
44 | ||
45 | #define MXS_NAND_COMMAND_BUFFER_SIZE 32 | |
46 | ||
47 | #define MXS_NAND_BCH_TIMEOUT 10000 | |
48 | ||
49 | struct mxs_nand_info { | |
50 | int cur_chip; | |
51 | ||
52 | uint32_t cmd_queue_len; | |
6b9408ed | 53 | uint32_t data_buf_size; |
0d4e8509 MV |
54 | |
55 | uint8_t *cmd_buf; | |
56 | uint8_t *data_buf; | |
57 | uint8_t *oob_buf; | |
58 | ||
59 | uint8_t marking_block_bad; | |
60 | uint8_t raw_oob_mode; | |
61 | ||
62 | /* Functions with altered behaviour */ | |
63 | int (*hooked_read_oob)(struct mtd_info *mtd, | |
64 | loff_t from, struct mtd_oob_ops *ops); | |
65 | int (*hooked_write_oob)(struct mtd_info *mtd, | |
66 | loff_t to, struct mtd_oob_ops *ops); | |
67 | int (*hooked_block_markbad)(struct mtd_info *mtd, | |
68 | loff_t ofs); | |
69 | ||
70 | /* DMA descriptors */ | |
71 | struct mxs_dma_desc **desc; | |
72 | uint32_t desc_index; | |
73 | }; | |
74 | ||
75 | struct nand_ecclayout fake_ecc_layout; | |
76 | ||
6b9408ed MV |
77 | /* |
78 | * Cache management functions | |
79 | */ | |
80 | #ifndef CONFIG_SYS_DCACHE_OFF | |
81 | static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) | |
82 | { | |
83 | uint32_t addr = (uint32_t)info->data_buf; | |
84 | ||
85 | flush_dcache_range(addr, addr + info->data_buf_size); | |
86 | } | |
87 | ||
88 | static void mxs_nand_inval_data_buf(struct mxs_nand_info *info) | |
89 | { | |
90 | uint32_t addr = (uint32_t)info->data_buf; | |
91 | ||
92 | invalidate_dcache_range(addr, addr + info->data_buf_size); | |
93 | } | |
94 | ||
95 | static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) | |
96 | { | |
97 | uint32_t addr = (uint32_t)info->cmd_buf; | |
98 | ||
99 | flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE); | |
100 | } | |
101 | #else | |
102 | static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {} | |
103 | static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {} | |
104 | static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {} | |
105 | #endif | |
106 | ||
0d4e8509 MV |
107 | static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info) |
108 | { | |
109 | struct mxs_dma_desc *desc; | |
110 | ||
111 | if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) { | |
112 | printf("MXS NAND: Too many DMA descriptors requested\n"); | |
113 | return NULL; | |
114 | } | |
115 | ||
116 | desc = info->desc[info->desc_index]; | |
117 | info->desc_index++; | |
118 | ||
119 | return desc; | |
120 | } | |
121 | ||
122 | static void mxs_nand_return_dma_descs(struct mxs_nand_info *info) | |
123 | { | |
124 | int i; | |
125 | struct mxs_dma_desc *desc; | |
126 | ||
127 | for (i = 0; i < info->desc_index; i++) { | |
128 | desc = info->desc[i]; | |
129 | memset(desc, 0, sizeof(struct mxs_dma_desc)); | |
130 | desc->address = (dma_addr_t)desc; | |
131 | } | |
132 | ||
133 | info->desc_index = 0; | |
134 | } | |
135 | ||
136 | static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size) | |
137 | { | |
138 | return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE; | |
139 | } | |
140 | ||
141 | static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength) | |
142 | { | |
143 | return ecc_strength * 13; | |
144 | } | |
145 | ||
146 | static uint32_t mxs_nand_aux_status_offset(void) | |
147 | { | |
148 | return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3; | |
149 | } | |
150 | ||
151 | static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, | |
152 | uint32_t page_oob_size) | |
153 | { | |
154 | if (page_data_size == 2048) | |
155 | return 8; | |
156 | ||
157 | if (page_data_size == 4096) { | |
158 | if (page_oob_size == 128) | |
159 | return 8; | |
160 | ||
161 | if (page_oob_size == 218) | |
162 | return 16; | |
163 | } | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size, | |
169 | uint32_t ecc_strength) | |
170 | { | |
171 | uint32_t chunk_data_size_in_bits; | |
172 | uint32_t chunk_ecc_size_in_bits; | |
173 | uint32_t chunk_total_size_in_bits; | |
174 | uint32_t block_mark_chunk_number; | |
175 | uint32_t block_mark_chunk_bit_offset; | |
176 | uint32_t block_mark_bit_offset; | |
177 | ||
178 | chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8; | |
179 | chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength); | |
180 | ||
181 | chunk_total_size_in_bits = | |
182 | chunk_data_size_in_bits + chunk_ecc_size_in_bits; | |
183 | ||
184 | /* Compute the bit offset of the block mark within the physical page. */ | |
185 | block_mark_bit_offset = page_data_size * 8; | |
186 | ||
187 | /* Subtract the metadata bits. */ | |
188 | block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8; | |
189 | ||
190 | /* | |
191 | * Compute the chunk number (starting at zero) in which the block mark | |
192 | * appears. | |
193 | */ | |
194 | block_mark_chunk_number = | |
195 | block_mark_bit_offset / chunk_total_size_in_bits; | |
196 | ||
197 | /* | |
198 | * Compute the bit offset of the block mark within its chunk, and | |
199 | * validate it. | |
200 | */ | |
201 | block_mark_chunk_bit_offset = block_mark_bit_offset - | |
202 | (block_mark_chunk_number * chunk_total_size_in_bits); | |
203 | ||
204 | if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) | |
205 | return 1; | |
206 | ||
207 | /* | |
208 | * Now that we know the chunk number in which the block mark appears, | |
209 | * we can subtract all the ECC bits that appear before it. | |
210 | */ | |
211 | block_mark_bit_offset -= | |
212 | block_mark_chunk_number * chunk_ecc_size_in_bits; | |
213 | ||
214 | return block_mark_bit_offset; | |
215 | } | |
216 | ||
217 | static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd) | |
218 | { | |
219 | uint32_t ecc_strength; | |
220 | ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); | |
221 | return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3; | |
222 | } | |
223 | ||
224 | static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd) | |
225 | { | |
226 | uint32_t ecc_strength; | |
227 | ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize); | |
228 | return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7; | |
229 | } | |
230 | ||
231 | /* | |
232 | * Wait for BCH complete IRQ and clear the IRQ | |
233 | */ | |
234 | static int mxs_nand_wait_for_bch_complete(void) | |
235 | { | |
9c471142 | 236 | struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; |
0d4e8509 MV |
237 | int timeout = MXS_NAND_BCH_TIMEOUT; |
238 | int ret; | |
239 | ||
fa7a51cb | 240 | ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg, |
0d4e8509 MV |
241 | BCH_CTRL_COMPLETE_IRQ, timeout); |
242 | ||
243 | writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr); | |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
248 | /* | |
249 | * This is the function that we install in the cmd_ctrl function pointer of the | |
250 | * owning struct nand_chip. The only functions in the reference implementation | |
251 | * that use these functions pointers are cmdfunc and select_chip. | |
252 | * | |
253 | * In this driver, we implement our own select_chip, so this function will only | |
254 | * be called by the reference implementation's cmdfunc. For this reason, we can | |
255 | * ignore the chip enable bit and concentrate only on sending bytes to the NAND | |
256 | * Flash. | |
257 | */ | |
258 | static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) | |
259 | { | |
260 | struct nand_chip *nand = mtd->priv; | |
261 | struct mxs_nand_info *nand_info = nand->priv; | |
262 | struct mxs_dma_desc *d; | |
263 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; | |
264 | int ret; | |
265 | ||
266 | /* | |
267 | * If this condition is true, something is _VERY_ wrong in MTD | |
268 | * subsystem! | |
269 | */ | |
270 | if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) { | |
271 | printf("MXS NAND: Command queue too long\n"); | |
272 | return; | |
273 | } | |
274 | ||
275 | /* | |
276 | * Every operation begins with a command byte and a series of zero or | |
277 | * more address bytes. These are distinguished by either the Address | |
278 | * Latch Enable (ALE) or Command Latch Enable (CLE) signals being | |
279 | * asserted. When MTD is ready to execute the command, it will | |
280 | * deasert both latch enables. | |
281 | * | |
282 | * Rather than run a separate DMA operation for every single byte, we | |
283 | * queue them up and run a single DMA operation for the entire series | |
284 | * of command and data bytes. | |
285 | */ | |
286 | if (ctrl & (NAND_ALE | NAND_CLE)) { | |
287 | if (data != NAND_CMD_NONE) | |
288 | nand_info->cmd_buf[nand_info->cmd_queue_len++] = data; | |
289 | return; | |
290 | } | |
291 | ||
292 | /* | |
293 | * If control arrives here, MTD has deasserted both the ALE and CLE, | |
294 | * which means it's ready to run an operation. Check if we have any | |
295 | * bytes to send. | |
296 | */ | |
297 | if (nand_info->cmd_queue_len == 0) | |
298 | return; | |
299 | ||
300 | /* Compile the DMA descriptor -- a descriptor that sends command. */ | |
301 | d = mxs_nand_get_dma_desc(nand_info); | |
302 | d->cmd.data = | |
303 | MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | | |
304 | MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM | | |
305 | MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | | |
306 | (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET); | |
307 | ||
308 | d->cmd.address = (dma_addr_t)nand_info->cmd_buf; | |
309 | ||
310 | d->cmd.pio_words[0] = | |
311 | GPMI_CTRL0_COMMAND_MODE_WRITE | | |
312 | GPMI_CTRL0_WORD_LENGTH | | |
313 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
314 | GPMI_CTRL0_ADDRESS_NAND_CLE | | |
315 | GPMI_CTRL0_ADDRESS_INCREMENT | | |
316 | nand_info->cmd_queue_len; | |
317 | ||
318 | mxs_dma_desc_append(channel, d); | |
319 | ||
6b9408ed MV |
320 | /* Flush caches */ |
321 | mxs_nand_flush_cmd_buf(nand_info); | |
322 | ||
0d4e8509 MV |
323 | /* Execute the DMA chain. */ |
324 | ret = mxs_dma_go(channel); | |
325 | if (ret) | |
326 | printf("MXS NAND: Error sending command\n"); | |
327 | ||
328 | mxs_nand_return_dma_descs(nand_info); | |
329 | ||
330 | /* Reset the command queue. */ | |
331 | nand_info->cmd_queue_len = 0; | |
332 | } | |
333 | ||
334 | /* | |
335 | * Test if the NAND flash is ready. | |
336 | */ | |
337 | static int mxs_nand_device_ready(struct mtd_info *mtd) | |
338 | { | |
339 | struct nand_chip *chip = mtd->priv; | |
340 | struct mxs_nand_info *nand_info = chip->priv; | |
9c471142 OS |
341 | struct mxs_gpmi_regs *gpmi_regs = |
342 | (struct mxs_gpmi_regs *)MXS_GPMI_BASE; | |
0d4e8509 MV |
343 | uint32_t tmp; |
344 | ||
345 | tmp = readl(&gpmi_regs->hw_gpmi_stat); | |
346 | tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip); | |
347 | ||
348 | return tmp & 1; | |
349 | } | |
350 | ||
351 | /* | |
352 | * Select the NAND chip. | |
353 | */ | |
354 | static void mxs_nand_select_chip(struct mtd_info *mtd, int chip) | |
355 | { | |
356 | struct nand_chip *nand = mtd->priv; | |
357 | struct mxs_nand_info *nand_info = nand->priv; | |
358 | ||
359 | nand_info->cur_chip = chip; | |
360 | } | |
361 | ||
362 | /* | |
363 | * Handle block mark swapping. | |
364 | * | |
365 | * Note that, when this function is called, it doesn't know whether it's | |
366 | * swapping the block mark, or swapping it *back* -- but it doesn't matter | |
367 | * because the the operation is the same. | |
368 | */ | |
369 | static void mxs_nand_swap_block_mark(struct mtd_info *mtd, | |
370 | uint8_t *data_buf, uint8_t *oob_buf) | |
371 | { | |
372 | uint32_t bit_offset; | |
373 | uint32_t buf_offset; | |
374 | ||
375 | uint32_t src; | |
376 | uint32_t dst; | |
377 | ||
378 | bit_offset = mxs_nand_mark_bit_offset(mtd); | |
379 | buf_offset = mxs_nand_mark_byte_offset(mtd); | |
380 | ||
381 | /* | |
382 | * Get the byte from the data area that overlays the block mark. Since | |
383 | * the ECC engine applies its own view to the bits in the page, the | |
384 | * physical block mark won't (in general) appear on a byte boundary in | |
385 | * the data. | |
386 | */ | |
387 | src = data_buf[buf_offset] >> bit_offset; | |
388 | src |= data_buf[buf_offset + 1] << (8 - bit_offset); | |
389 | ||
390 | dst = oob_buf[0]; | |
391 | ||
392 | oob_buf[0] = src; | |
393 | ||
394 | data_buf[buf_offset] &= ~(0xff << bit_offset); | |
395 | data_buf[buf_offset + 1] &= 0xff << bit_offset; | |
396 | ||
397 | data_buf[buf_offset] |= dst << bit_offset; | |
398 | data_buf[buf_offset + 1] |= dst >> (8 - bit_offset); | |
399 | } | |
400 | ||
401 | /* | |
402 | * Read data from NAND. | |
403 | */ | |
404 | static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) | |
405 | { | |
406 | struct nand_chip *nand = mtd->priv; | |
407 | struct mxs_nand_info *nand_info = nand->priv; | |
408 | struct mxs_dma_desc *d; | |
409 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; | |
410 | int ret; | |
411 | ||
412 | if (length > NAND_MAX_PAGESIZE) { | |
413 | printf("MXS NAND: DMA buffer too big\n"); | |
414 | return; | |
415 | } | |
416 | ||
417 | if (!buf) { | |
418 | printf("MXS NAND: DMA buffer is NULL\n"); | |
419 | return; | |
420 | } | |
421 | ||
422 | /* Compile the DMA descriptor - a descriptor that reads data. */ | |
423 | d = mxs_nand_get_dma_desc(nand_info); | |
424 | d->cmd.data = | |
425 | MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ | | |
426 | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | | |
427 | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | | |
428 | (length << MXS_DMA_DESC_BYTES_OFFSET); | |
429 | ||
430 | d->cmd.address = (dma_addr_t)nand_info->data_buf; | |
431 | ||
432 | d->cmd.pio_words[0] = | |
433 | GPMI_CTRL0_COMMAND_MODE_READ | | |
434 | GPMI_CTRL0_WORD_LENGTH | | |
435 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
436 | GPMI_CTRL0_ADDRESS_NAND_DATA | | |
437 | length; | |
438 | ||
439 | mxs_dma_desc_append(channel, d); | |
440 | ||
441 | /* | |
442 | * A DMA descriptor that waits for the command to end and the chip to | |
443 | * become ready. | |
444 | * | |
445 | * I think we actually should *not* be waiting for the chip to become | |
446 | * ready because, after all, we don't care. I think the original code | |
447 | * did that and no one has re-thought it yet. | |
448 | */ | |
449 | d = mxs_nand_get_dma_desc(nand_info); | |
450 | d->cmd.data = | |
451 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | | |
452 | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM | | |
453 | MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET); | |
454 | ||
455 | d->cmd.address = 0; | |
456 | ||
457 | d->cmd.pio_words[0] = | |
458 | GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | | |
459 | GPMI_CTRL0_WORD_LENGTH | | |
460 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
461 | GPMI_CTRL0_ADDRESS_NAND_DATA; | |
462 | ||
463 | mxs_dma_desc_append(channel, d); | |
464 | ||
465 | /* Execute the DMA chain. */ | |
466 | ret = mxs_dma_go(channel); | |
467 | if (ret) { | |
468 | printf("MXS NAND: DMA read error\n"); | |
469 | goto rtn; | |
470 | } | |
471 | ||
6b9408ed MV |
472 | /* Invalidate caches */ |
473 | mxs_nand_inval_data_buf(nand_info); | |
474 | ||
0d4e8509 MV |
475 | memcpy(buf, nand_info->data_buf, length); |
476 | ||
477 | rtn: | |
478 | mxs_nand_return_dma_descs(nand_info); | |
479 | } | |
480 | ||
481 | /* | |
482 | * Write data to NAND. | |
483 | */ | |
484 | static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, | |
485 | int length) | |
486 | { | |
487 | struct nand_chip *nand = mtd->priv; | |
488 | struct mxs_nand_info *nand_info = nand->priv; | |
489 | struct mxs_dma_desc *d; | |
490 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; | |
491 | int ret; | |
492 | ||
493 | if (length > NAND_MAX_PAGESIZE) { | |
494 | printf("MXS NAND: DMA buffer too big\n"); | |
495 | return; | |
496 | } | |
497 | ||
498 | if (!buf) { | |
499 | printf("MXS NAND: DMA buffer is NULL\n"); | |
500 | return; | |
501 | } | |
502 | ||
503 | memcpy(nand_info->data_buf, buf, length); | |
504 | ||
505 | /* Compile the DMA descriptor - a descriptor that writes data. */ | |
506 | d = mxs_nand_get_dma_desc(nand_info); | |
507 | d->cmd.data = | |
508 | MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | | |
509 | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | | |
510 | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | | |
511 | (length << MXS_DMA_DESC_BYTES_OFFSET); | |
512 | ||
513 | d->cmd.address = (dma_addr_t)nand_info->data_buf; | |
514 | ||
515 | d->cmd.pio_words[0] = | |
516 | GPMI_CTRL0_COMMAND_MODE_WRITE | | |
517 | GPMI_CTRL0_WORD_LENGTH | | |
518 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
519 | GPMI_CTRL0_ADDRESS_NAND_DATA | | |
520 | length; | |
521 | ||
522 | mxs_dma_desc_append(channel, d); | |
523 | ||
6b9408ed MV |
524 | /* Flush caches */ |
525 | mxs_nand_flush_data_buf(nand_info); | |
526 | ||
0d4e8509 MV |
527 | /* Execute the DMA chain. */ |
528 | ret = mxs_dma_go(channel); | |
529 | if (ret) | |
530 | printf("MXS NAND: DMA write error\n"); | |
531 | ||
532 | mxs_nand_return_dma_descs(nand_info); | |
533 | } | |
534 | ||
535 | /* | |
536 | * Read a single byte from NAND. | |
537 | */ | |
538 | static uint8_t mxs_nand_read_byte(struct mtd_info *mtd) | |
539 | { | |
540 | uint8_t buf; | |
541 | mxs_nand_read_buf(mtd, &buf, 1); | |
542 | return buf; | |
543 | } | |
544 | ||
545 | /* | |
546 | * Read a page from NAND. | |
547 | */ | |
548 | static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, | |
549 | uint8_t *buf, int page) | |
550 | { | |
551 | struct mxs_nand_info *nand_info = nand->priv; | |
552 | struct mxs_dma_desc *d; | |
553 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; | |
554 | uint32_t corrected = 0, failed = 0; | |
555 | uint8_t *status; | |
556 | int i, ret; | |
557 | ||
558 | /* Compile the DMA descriptor - wait for ready. */ | |
559 | d = mxs_nand_get_dma_desc(nand_info); | |
560 | d->cmd.data = | |
561 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | | |
562 | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | | |
563 | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); | |
564 | ||
565 | d->cmd.address = 0; | |
566 | ||
567 | d->cmd.pio_words[0] = | |
568 | GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | | |
569 | GPMI_CTRL0_WORD_LENGTH | | |
570 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
571 | GPMI_CTRL0_ADDRESS_NAND_DATA; | |
572 | ||
573 | mxs_dma_desc_append(channel, d); | |
574 | ||
575 | /* Compile the DMA descriptor - enable the BCH block and read. */ | |
576 | d = mxs_nand_get_dma_desc(nand_info); | |
577 | d->cmd.data = | |
578 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | | |
579 | MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); | |
580 | ||
581 | d->cmd.address = 0; | |
582 | ||
583 | d->cmd.pio_words[0] = | |
584 | GPMI_CTRL0_COMMAND_MODE_READ | | |
585 | GPMI_CTRL0_WORD_LENGTH | | |
586 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
587 | GPMI_CTRL0_ADDRESS_NAND_DATA | | |
588 | (mtd->writesize + mtd->oobsize); | |
589 | d->cmd.pio_words[1] = 0; | |
590 | d->cmd.pio_words[2] = | |
591 | GPMI_ECCCTRL_ENABLE_ECC | | |
592 | GPMI_ECCCTRL_ECC_CMD_DECODE | | |
593 | GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; | |
594 | d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize; | |
595 | d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; | |
596 | d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; | |
597 | ||
598 | mxs_dma_desc_append(channel, d); | |
599 | ||
600 | /* Compile the DMA descriptor - disable the BCH block. */ | |
601 | d = mxs_nand_get_dma_desc(nand_info); | |
602 | d->cmd.data = | |
603 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | | |
604 | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END | | |
605 | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET); | |
606 | ||
607 | d->cmd.address = 0; | |
608 | ||
609 | d->cmd.pio_words[0] = | |
610 | GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY | | |
611 | GPMI_CTRL0_WORD_LENGTH | | |
612 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
613 | GPMI_CTRL0_ADDRESS_NAND_DATA | | |
614 | (mtd->writesize + mtd->oobsize); | |
615 | d->cmd.pio_words[1] = 0; | |
616 | d->cmd.pio_words[2] = 0; | |
617 | ||
618 | mxs_dma_desc_append(channel, d); | |
619 | ||
620 | /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */ | |
621 | d = mxs_nand_get_dma_desc(nand_info); | |
622 | d->cmd.data = | |
623 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | | |
624 | MXS_DMA_DESC_DEC_SEM; | |
625 | ||
626 | d->cmd.address = 0; | |
627 | ||
628 | mxs_dma_desc_append(channel, d); | |
629 | ||
630 | /* Execute the DMA chain. */ | |
631 | ret = mxs_dma_go(channel); | |
632 | if (ret) { | |
633 | printf("MXS NAND: DMA read error\n"); | |
634 | goto rtn; | |
635 | } | |
636 | ||
637 | ret = mxs_nand_wait_for_bch_complete(); | |
638 | if (ret) { | |
639 | printf("MXS NAND: BCH read timeout\n"); | |
640 | goto rtn; | |
641 | } | |
642 | ||
6b9408ed MV |
643 | /* Invalidate caches */ |
644 | mxs_nand_inval_data_buf(nand_info); | |
645 | ||
0d4e8509 MV |
646 | /* Read DMA completed, now do the mark swapping. */ |
647 | mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); | |
648 | ||
649 | /* Loop over status bytes, accumulating ECC status. */ | |
650 | status = nand_info->oob_buf + mxs_nand_aux_status_offset(); | |
651 | for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) { | |
652 | if (status[i] == 0x00) | |
653 | continue; | |
654 | ||
655 | if (status[i] == 0xff) | |
656 | continue; | |
657 | ||
658 | if (status[i] == 0xfe) { | |
659 | failed++; | |
660 | continue; | |
661 | } | |
662 | ||
663 | corrected += status[i]; | |
664 | } | |
665 | ||
666 | /* Propagate ECC status to the owning MTD. */ | |
667 | mtd->ecc_stats.failed += failed; | |
668 | mtd->ecc_stats.corrected += corrected; | |
669 | ||
670 | /* | |
671 | * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for | |
672 | * details about our policy for delivering the OOB. | |
673 | * | |
674 | * We fill the caller's buffer with set bits, and then copy the block | |
675 | * mark to the caller's buffer. Note that, if block mark swapping was | |
676 | * necessary, it has already been done, so we can rely on the first | |
677 | * byte of the auxiliary buffer to contain the block mark. | |
678 | */ | |
679 | memset(nand->oob_poi, 0xff, mtd->oobsize); | |
680 | ||
681 | nand->oob_poi[0] = nand_info->oob_buf[0]; | |
682 | ||
683 | memcpy(buf, nand_info->data_buf, mtd->writesize); | |
684 | ||
685 | rtn: | |
686 | mxs_nand_return_dma_descs(nand_info); | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
691 | /* | |
692 | * Write a page to NAND. | |
693 | */ | |
694 | static void mxs_nand_ecc_write_page(struct mtd_info *mtd, | |
695 | struct nand_chip *nand, const uint8_t *buf) | |
696 | { | |
697 | struct mxs_nand_info *nand_info = nand->priv; | |
698 | struct mxs_dma_desc *d; | |
699 | uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip; | |
700 | int ret; | |
701 | ||
702 | memcpy(nand_info->data_buf, buf, mtd->writesize); | |
703 | memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize); | |
704 | ||
705 | /* Handle block mark swapping. */ | |
706 | mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf); | |
707 | ||
708 | /* Compile the DMA descriptor - write data. */ | |
709 | d = mxs_nand_get_dma_desc(nand_info); | |
710 | d->cmd.data = | |
711 | MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | | |
712 | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | | |
713 | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET); | |
714 | ||
715 | d->cmd.address = 0; | |
716 | ||
717 | d->cmd.pio_words[0] = | |
718 | GPMI_CTRL0_COMMAND_MODE_WRITE | | |
719 | GPMI_CTRL0_WORD_LENGTH | | |
720 | (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) | | |
721 | GPMI_CTRL0_ADDRESS_NAND_DATA; | |
722 | d->cmd.pio_words[1] = 0; | |
723 | d->cmd.pio_words[2] = | |
724 | GPMI_ECCCTRL_ENABLE_ECC | | |
725 | GPMI_ECCCTRL_ECC_CMD_ENCODE | | |
726 | GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE; | |
727 | d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize); | |
728 | d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; | |
729 | d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; | |
730 | ||
731 | mxs_dma_desc_append(channel, d); | |
732 | ||
6b9408ed MV |
733 | /* Flush caches */ |
734 | mxs_nand_flush_data_buf(nand_info); | |
735 | ||
0d4e8509 MV |
736 | /* Execute the DMA chain. */ |
737 | ret = mxs_dma_go(channel); | |
738 | if (ret) { | |
739 | printf("MXS NAND: DMA write error\n"); | |
740 | goto rtn; | |
741 | } | |
742 | ||
743 | ret = mxs_nand_wait_for_bch_complete(); | |
744 | if (ret) { | |
745 | printf("MXS NAND: BCH write timeout\n"); | |
746 | goto rtn; | |
747 | } | |
748 | ||
749 | rtn: | |
750 | mxs_nand_return_dma_descs(nand_info); | |
751 | } | |
752 | ||
753 | /* | |
754 | * Read OOB from NAND. | |
755 | * | |
756 | * This function is a veneer that replaces the function originally installed by | |
757 | * the NAND Flash MTD code. | |
758 | */ | |
759 | static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from, | |
760 | struct mtd_oob_ops *ops) | |
761 | { | |
762 | struct nand_chip *chip = mtd->priv; | |
763 | struct mxs_nand_info *nand_info = chip->priv; | |
764 | int ret; | |
765 | ||
766 | if (ops->mode == MTD_OOB_RAW) | |
767 | nand_info->raw_oob_mode = 1; | |
768 | else | |
769 | nand_info->raw_oob_mode = 0; | |
770 | ||
771 | ret = nand_info->hooked_read_oob(mtd, from, ops); | |
772 | ||
773 | nand_info->raw_oob_mode = 0; | |
774 | ||
775 | return ret; | |
776 | } | |
777 | ||
778 | /* | |
779 | * Write OOB to NAND. | |
780 | * | |
781 | * This function is a veneer that replaces the function originally installed by | |
782 | * the NAND Flash MTD code. | |
783 | */ | |
784 | static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to, | |
785 | struct mtd_oob_ops *ops) | |
786 | { | |
787 | struct nand_chip *chip = mtd->priv; | |
788 | struct mxs_nand_info *nand_info = chip->priv; | |
789 | int ret; | |
790 | ||
791 | if (ops->mode == MTD_OOB_RAW) | |
792 | nand_info->raw_oob_mode = 1; | |
793 | else | |
794 | nand_info->raw_oob_mode = 0; | |
795 | ||
796 | ret = nand_info->hooked_write_oob(mtd, to, ops); | |
797 | ||
798 | nand_info->raw_oob_mode = 0; | |
799 | ||
800 | return ret; | |
801 | } | |
802 | ||
803 | /* | |
804 | * Mark a block bad in NAND. | |
805 | * | |
806 | * This function is a veneer that replaces the function originally installed by | |
807 | * the NAND Flash MTD code. | |
808 | */ | |
809 | static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
810 | { | |
811 | struct nand_chip *chip = mtd->priv; | |
812 | struct mxs_nand_info *nand_info = chip->priv; | |
813 | int ret; | |
814 | ||
815 | nand_info->marking_block_bad = 1; | |
816 | ||
817 | ret = nand_info->hooked_block_markbad(mtd, ofs); | |
818 | ||
819 | nand_info->marking_block_bad = 0; | |
820 | ||
821 | return ret; | |
822 | } | |
823 | ||
824 | /* | |
825 | * There are several places in this driver where we have to handle the OOB and | |
826 | * block marks. This is the function where things are the most complicated, so | |
827 | * this is where we try to explain it all. All the other places refer back to | |
828 | * here. | |
829 | * | |
830 | * These are the rules, in order of decreasing importance: | |
831 | * | |
832 | * 1) Nothing the caller does can be allowed to imperil the block mark, so all | |
833 | * write operations take measures to protect it. | |
834 | * | |
835 | * 2) In read operations, the first byte of the OOB we return must reflect the | |
836 | * true state of the block mark, no matter where that block mark appears in | |
837 | * the physical page. | |
838 | * | |
839 | * 3) ECC-based read operations return an OOB full of set bits (since we never | |
840 | * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads | |
841 | * return). | |
842 | * | |
843 | * 4) "Raw" read operations return a direct view of the physical bytes in the | |
844 | * page, using the conventional definition of which bytes are data and which | |
845 | * are OOB. This gives the caller a way to see the actual, physical bytes | |
846 | * in the page, without the distortions applied by our ECC engine. | |
847 | * | |
848 | * What we do for this specific read operation depends on whether we're doing | |
849 | * "raw" read, or an ECC-based read. | |
850 | * | |
851 | * It turns out that knowing whether we want an "ECC-based" or "raw" read is not | |
852 | * easy. When reading a page, for example, the NAND Flash MTD code calls our | |
853 | * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an | |
854 | * ECC-based or raw view of the page is implicit in which function it calls | |
855 | * (there is a similar pair of ECC-based/raw functions for writing). | |
856 | * | |
857 | * Since MTD assumes the OOB is not covered by ECC, there is no pair of | |
858 | * ECC-based/raw functions for reading or or writing the OOB. The fact that the | |
859 | * caller wants an ECC-based or raw view of the page is not propagated down to | |
860 | * this driver. | |
861 | * | |
862 | * Since our OOB *is* covered by ECC, we need this information. So, we hook the | |
863 | * ecc.read_oob and ecc.write_oob function pointers in the owning | |
864 | * struct mtd_info with our own functions. These hook functions set the | |
865 | * raw_oob_mode field so that, when control finally arrives here, we'll know | |
866 | * what to do. | |
867 | */ | |
868 | static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand, | |
869 | int page, int cmd) | |
870 | { | |
871 | struct mxs_nand_info *nand_info = nand->priv; | |
872 | ||
873 | /* | |
874 | * First, fill in the OOB buffer. If we're doing a raw read, we need to | |
875 | * get the bytes from the physical page. If we're not doing a raw read, | |
876 | * we need to fill the buffer with set bits. | |
877 | */ | |
878 | if (nand_info->raw_oob_mode) { | |
879 | /* | |
880 | * If control arrives here, we're doing a "raw" read. Send the | |
881 | * command to read the conventional OOB and read it. | |
882 | */ | |
883 | nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); | |
884 | nand->read_buf(mtd, nand->oob_poi, mtd->oobsize); | |
885 | } else { | |
886 | /* | |
887 | * If control arrives here, we're not doing a "raw" read. Fill | |
888 | * the OOB buffer with set bits and correct the block mark. | |
889 | */ | |
890 | memset(nand->oob_poi, 0xff, mtd->oobsize); | |
891 | ||
892 | nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page); | |
893 | mxs_nand_read_buf(mtd, nand->oob_poi, 1); | |
894 | } | |
895 | ||
896 | return 0; | |
897 | ||
898 | } | |
899 | ||
900 | /* | |
901 | * Write OOB data to NAND. | |
902 | */ | |
903 | static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand, | |
904 | int page) | |
905 | { | |
906 | struct mxs_nand_info *nand_info = nand->priv; | |
907 | uint8_t block_mark = 0; | |
908 | ||
909 | /* | |
910 | * There are fundamental incompatibilities between the i.MX GPMI NFC and | |
911 | * the NAND Flash MTD model that make it essentially impossible to write | |
912 | * the out-of-band bytes. | |
913 | * | |
914 | * We permit *ONE* exception. If the *intent* of writing the OOB is to | |
915 | * mark a block bad, we can do that. | |
916 | */ | |
917 | ||
918 | if (!nand_info->marking_block_bad) { | |
919 | printf("NXS NAND: Writing OOB isn't supported\n"); | |
920 | return -EIO; | |
921 | } | |
922 | ||
923 | /* Write the block mark. */ | |
924 | nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
925 | nand->write_buf(mtd, &block_mark, 1); | |
926 | nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
927 | ||
928 | /* Check if it worked. */ | |
929 | if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL) | |
930 | return -EIO; | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
935 | /* | |
936 | * Claims all blocks are good. | |
937 | * | |
938 | * In principle, this function is *only* called when the NAND Flash MTD system | |
939 | * isn't allowed to keep an in-memory bad block table, so it is forced to ask | |
940 | * the driver for bad block information. | |
941 | * | |
942 | * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so | |
943 | * this function is *only* called when we take it away. | |
944 | * | |
945 | * Thus, this function is only called when we want *all* blocks to look good, | |
946 | * so it *always* return success. | |
947 | */ | |
948 | static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
949 | { | |
950 | return 0; | |
951 | } | |
952 | ||
953 | /* | |
954 | * Nominally, the purpose of this function is to look for or create the bad | |
955 | * block table. In fact, since the we call this function at the very end of | |
956 | * the initialization process started by nand_scan(), and we doesn't have a | |
957 | * more formal mechanism, we "hook" this function to continue init process. | |
958 | * | |
959 | * At this point, the physical NAND Flash chips have been identified and | |
960 | * counted, so we know the physical geometry. This enables us to make some | |
961 | * important configuration decisions. | |
962 | * | |
963 | * The return value of this function propogates directly back to this driver's | |
964 | * call to nand_scan(). Anything other than zero will cause this driver to | |
965 | * tear everything down and declare failure. | |
966 | */ | |
967 | static int mxs_nand_scan_bbt(struct mtd_info *mtd) | |
968 | { | |
969 | struct nand_chip *nand = mtd->priv; | |
970 | struct mxs_nand_info *nand_info = nand->priv; | |
9c471142 | 971 | struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; |
0d4e8509 MV |
972 | uint32_t tmp; |
973 | ||
974 | /* Configure BCH and set NFC geometry */ | |
fa7a51cb | 975 | mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); |
0d4e8509 MV |
976 | |
977 | /* Configure layout 0 */ | |
978 | tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1) | |
979 | << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; | |
980 | tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; | |
981 | tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) | |
982 | << BCH_FLASHLAYOUT0_ECC0_OFFSET; | |
983 | tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE; | |
984 | writel(tmp, &bch_regs->hw_bch_flash0layout0); | |
985 | ||
986 | tmp = (mtd->writesize + mtd->oobsize) | |
987 | << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; | |
988 | tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1) | |
989 | << BCH_FLASHLAYOUT1_ECCN_OFFSET; | |
990 | tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE; | |
991 | writel(tmp, &bch_regs->hw_bch_flash0layout1); | |
992 | ||
993 | /* Set *all* chip selects to use layout 0 */ | |
994 | writel(0, &bch_regs->hw_bch_layoutselect); | |
995 | ||
996 | /* Enable BCH complete interrupt */ | |
997 | writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set); | |
998 | ||
999 | /* Hook some operations at the MTD level. */ | |
1000 | if (mtd->read_oob != mxs_nand_hook_read_oob) { | |
1001 | nand_info->hooked_read_oob = mtd->read_oob; | |
1002 | mtd->read_oob = mxs_nand_hook_read_oob; | |
1003 | } | |
1004 | ||
1005 | if (mtd->write_oob != mxs_nand_hook_write_oob) { | |
1006 | nand_info->hooked_write_oob = mtd->write_oob; | |
1007 | mtd->write_oob = mxs_nand_hook_write_oob; | |
1008 | } | |
1009 | ||
1010 | if (mtd->block_markbad != mxs_nand_hook_block_markbad) { | |
1011 | nand_info->hooked_block_markbad = mtd->block_markbad; | |
1012 | mtd->block_markbad = mxs_nand_hook_block_markbad; | |
1013 | } | |
1014 | ||
1015 | /* We use the reference implementation for bad block management. */ | |
1016 | return nand_default_bbt(mtd); | |
1017 | } | |
1018 | ||
1019 | /* | |
1020 | * Allocate DMA buffers | |
1021 | */ | |
1022 | int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info) | |
1023 | { | |
1024 | uint8_t *buf; | |
1025 | const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE; | |
1026 | ||
6b9408ed MV |
1027 | nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT); |
1028 | ||
0d4e8509 | 1029 | /* DMA buffers */ |
6b9408ed | 1030 | buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size); |
0d4e8509 MV |
1031 | if (!buf) { |
1032 | printf("MXS NAND: Error allocating DMA buffers\n"); | |
1033 | return -ENOMEM; | |
1034 | } | |
1035 | ||
6b9408ed | 1036 | memset(buf, 0, nand_info->data_buf_size); |
0d4e8509 MV |
1037 | |
1038 | nand_info->data_buf = buf; | |
1039 | nand_info->oob_buf = buf + NAND_MAX_PAGESIZE; | |
0d4e8509 MV |
1040 | /* Command buffers */ |
1041 | nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT, | |
1042 | MXS_NAND_COMMAND_BUFFER_SIZE); | |
1043 | if (!nand_info->cmd_buf) { | |
1044 | free(buf); | |
1045 | printf("MXS NAND: Error allocating command buffers\n"); | |
1046 | return -ENOMEM; | |
1047 | } | |
1048 | memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE); | |
1049 | nand_info->cmd_queue_len = 0; | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Initializes the NFC hardware. | |
1056 | */ | |
1057 | int mxs_nand_init(struct mxs_nand_info *info) | |
1058 | { | |
9c471142 OS |
1059 | struct mxs_gpmi_regs *gpmi_regs = |
1060 | (struct mxs_gpmi_regs *)MXS_GPMI_BASE; | |
96666a39 | 1061 | int i = 0, j; |
0d4e8509 MV |
1062 | |
1063 | info->desc = malloc(sizeof(struct mxs_dma_desc *) * | |
1064 | MXS_NAND_DMA_DESCRIPTOR_COUNT); | |
1065 | if (!info->desc) | |
1066 | goto err1; | |
1067 | ||
1068 | /* Allocate the DMA descriptors. */ | |
1069 | for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) { | |
1070 | info->desc[i] = mxs_dma_desc_alloc(); | |
1071 | if (!info->desc[i]) | |
1072 | goto err2; | |
1073 | } | |
1074 | ||
1075 | /* Init the DMA controller. */ | |
96666a39 MV |
1076 | for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0; |
1077 | j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) { | |
1078 | if (mxs_dma_init_channel(j)) | |
1079 | goto err3; | |
1080 | } | |
0d4e8509 MV |
1081 | |
1082 | /* Reset the GPMI block. */ | |
fa7a51cb | 1083 | mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg); |
0d4e8509 MV |
1084 | |
1085 | /* | |
1086 | * Choose NAND mode, set IRQ polarity, disable write protection and | |
1087 | * select BCH ECC. | |
1088 | */ | |
1089 | clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1, | |
1090 | GPMI_CTRL1_GPMI_MODE, | |
1091 | GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET | | |
1092 | GPMI_CTRL1_BCH_MODE); | |
1093 | ||
1094 | return 0; | |
1095 | ||
96666a39 MV |
1096 | err3: |
1097 | for (--j; j >= 0; j--) | |
1098 | mxs_dma_release(j); | |
0d4e8509 MV |
1099 | err2: |
1100 | free(info->desc); | |
1101 | err1: | |
1102 | for (--i; i >= 0; i--) | |
1103 | mxs_dma_desc_free(info->desc[i]); | |
1104 | printf("MXS NAND: Unable to allocate DMA descriptors\n"); | |
1105 | return -ENOMEM; | |
1106 | } | |
1107 | ||
1108 | /*! | |
1109 | * This function is called during the driver binding process. | |
1110 | * | |
1111 | * @param pdev the device structure used to store device specific | |
1112 | * information that is used by the suspend, resume and | |
1113 | * remove functions | |
1114 | * | |
1115 | * @return The function always returns 0. | |
1116 | */ | |
1117 | int board_nand_init(struct nand_chip *nand) | |
1118 | { | |
1119 | struct mxs_nand_info *nand_info; | |
1120 | int err; | |
1121 | ||
1122 | nand_info = malloc(sizeof(struct mxs_nand_info)); | |
1123 | if (!nand_info) { | |
1124 | printf("MXS NAND: Failed to allocate private data\n"); | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | memset(nand_info, 0, sizeof(struct mxs_nand_info)); | |
1128 | ||
1129 | err = mxs_nand_alloc_buffers(nand_info); | |
1130 | if (err) | |
1131 | goto err1; | |
1132 | ||
1133 | err = mxs_nand_init(nand_info); | |
1134 | if (err) | |
1135 | goto err2; | |
1136 | ||
1137 | memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); | |
1138 | ||
1139 | nand->priv = nand_info; | |
1140 | nand->options |= NAND_NO_SUBPAGE_WRITE; | |
1141 | ||
1142 | nand->cmd_ctrl = mxs_nand_cmd_ctrl; | |
1143 | ||
1144 | nand->dev_ready = mxs_nand_device_ready; | |
1145 | nand->select_chip = mxs_nand_select_chip; | |
1146 | nand->block_bad = mxs_nand_block_bad; | |
1147 | nand->scan_bbt = mxs_nand_scan_bbt; | |
1148 | ||
1149 | nand->read_byte = mxs_nand_read_byte; | |
1150 | ||
1151 | nand->read_buf = mxs_nand_read_buf; | |
1152 | nand->write_buf = mxs_nand_write_buf; | |
1153 | ||
1154 | nand->ecc.read_page = mxs_nand_ecc_read_page; | |
1155 | nand->ecc.write_page = mxs_nand_ecc_write_page; | |
1156 | nand->ecc.read_oob = mxs_nand_ecc_read_oob; | |
1157 | nand->ecc.write_oob = mxs_nand_ecc_write_oob; | |
1158 | ||
1159 | nand->ecc.layout = &fake_ecc_layout; | |
1160 | nand->ecc.mode = NAND_ECC_HW; | |
1161 | nand->ecc.bytes = 9; | |
1162 | nand->ecc.size = 512; | |
1163 | ||
1164 | return 0; | |
1165 | ||
1166 | err2: | |
1167 | free(nand_info->data_buf); | |
1168 | free(nand_info->cmd_buf); | |
1169 | err1: | |
1170 | free(nand_info); | |
1171 | return err; | |
1172 | } |