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mtd, spi: Add MTD layer driver
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1/*
2 * SPI flash internal definitions
3 *
4 * Copyright (C) 2008 Atmel Corporation
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5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6 *
0c88a84a 7 * SPDX-License-Identifier: GPL-2.0+
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8 */
9
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10#ifndef _SF_INTERNAL_H_
11#define _SF_INTERNAL_H_
d25ce7d2 12
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13#include <linux/types.h>
14#include <linux/compiler.h>
15
16/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
17enum spi_dual_flash {
18 SF_SINGLE_FLASH = 0,
19 SF_DUAL_STACKED_FLASH = 1 << 0,
20 SF_DUAL_PARALLEL_FLASH = 1 << 1,
21};
22
23/* Enum list - Full read commands */
24enum spi_read_cmds {
25 ARRAY_SLOW = 1 << 0,
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26 ARRAY_FAST = 1 << 1,
27 DUAL_OUTPUT_FAST = 1 << 2,
28 DUAL_IO_FAST = 1 << 3,
29 QUAD_OUTPUT_FAST = 1 << 4,
30 QUAD_IO_FAST = 1 << 5,
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31};
32
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33/* Normal - Extended - Full command set */
34#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
35#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
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36#define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
37
38/* sf param flags */
39enum {
40 SECT_4K = 1 << 0,
41 SECT_32K = 1 << 1,
42 E_FSR = 1 << 2,
54ba653a 43 SST_BP = 1 << 3,
b648742a 44 SST_WP = 1 << 4,
54ba653a 45 WR_QPP = 1 << 5,
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46};
47
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48#define SST_WR (SST_BP | SST_WP)
49
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50#define SPI_FLASH_3B_ADDR_LEN 3
51#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
a5e8199a 52#define SPI_FLASH_16MB_BOUN 0x1000000
d25ce7d2 53
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54/* CFI Manufacture ID's */
55#define SPI_FLASH_CFI_MFR_SPANSION 0x01
56#define SPI_FLASH_CFI_MFR_STMICRO 0x20
06795122 57#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
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58#define SPI_FLASH_CFI_MFR_WINBOND 0xef
59
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60/* Erase commands */
61#define CMD_ERASE_4K 0x20
62#define CMD_ERASE_32K 0x52
63#define CMD_ERASE_CHIP 0xc7
64#define CMD_ERASE_64K 0xd8
d25ce7d2 65
a5e8199a 66/* Write commands */
b4c87d65 67#define CMD_WRITE_STATUS 0x01
d4aa5009 68#define CMD_PAGE_PROGRAM 0x02
66ecb7cd 69#define CMD_WRITE_DISABLE 0x04
ff0960f9 70#define CMD_READ_STATUS 0x05
3163aaa6 71#define CMD_QUAD_PAGE_PROGRAM 0x32
ffdb20be 72#define CMD_READ_STATUS1 0x35
e7b44edd 73#define CMD_WRITE_ENABLE 0x06
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74#define CMD_READ_CONFIG 0x35
75#define CMD_FLAG_STATUS 0x70
6163045b 76
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77/* Read commands */
78#define CMD_READ_ARRAY_SLOW 0x03
79#define CMD_READ_ARRAY_FAST 0x0b
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80#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
81#define CMD_READ_DUAL_IO_FAST 0xbb
3163aaa6 82#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
c4ba0d82 83#define CMD_READ_QUAD_IO_FAST 0xeb
a5e8199a 84#define CMD_READ_ID 0x9f
e612ddf5 85
cf6b11dc 86/* Bank addr access commands */
a5e8199a 87#ifdef CONFIG_SPI_FLASH_BAR
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88# define CMD_BANKADDR_BRWR 0x17
89# define CMD_BANKADDR_BRRD 0x16
90# define CMD_EXTNADDR_WREAR 0xC5
91# define CMD_EXTNADDR_RDEAR 0xC8
92#endif
cf6b11dc 93
6163045b 94/* Common status */
2ba863fa 95#define STATUS_WIP (1 << 0)
d08a1baf 96#define STATUS_QEB_WINSPAN (1 << 1)
ff0960f9 97#define STATUS_QEB_MXIC (1 << 6)
2ba863fa 98#define STATUS_PEC (1 << 7)
6163045b 99
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100/* Flash timeout values */
101#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
ff0960f9 102#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
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103#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
104
105/* SST specific */
106#ifdef CONFIG_SPI_FLASH_SST
ce22b922 107# define CMD_SST_BP 0x02 /* Byte Program */
ff0960f9 108# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
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109
110int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
111 const void *buf);
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112int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
113 const void *buf);
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114#endif
115
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116/**
117 * struct spi_flash_params - SPI/QSPI flash device params structure
118 *
119 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
120 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
121 * @ext_jedec: Device ext_jedec ID
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122 * @sector_size: Isn't necessarily a sector size from vendor,
123 * the size listed here is what works with CMD_ERASE_64K
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124 * @nr_sectors: No.of sectors on this device
125 * @e_rd_cmd: Enum list for read commands
126 * @flags: Important param, for flash specific behaviour
127 */
128struct spi_flash_params {
129 const char *name;
130 u32 jedec;
131 u16 ext_jedec;
132 u32 sector_size;
133 u32 nr_sectors;
134 u8 e_rd_cmd;
135 u16 flags;
136};
137
138extern const struct spi_flash_params spi_flash_params_table[];
139
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140/* Send a single-byte command to the device and read the response */
141int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
142
143/*
144 * Send a multi-byte command to the device and read the response. Used
145 * for flash array reads, etc.
146 */
147int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
148 size_t cmd_len, void *data, size_t data_len);
149
150/*
151 * Send a multi-byte command to the device followed by (optional)
152 * data. Used for programming the flash array, etc.
153 */
154int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
155 const void *data, size_t data_len);
156
d4aa5009 157
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158/* Flash erase(sectors) operation, support all possible erase commands */
159int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
10ca45d0 160
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161/* Read the status register */
162int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
163
a5e8199a 164/* Program the status register */
2ba863fa 165int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
a5e8199a 166
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167/* Read the config register */
168int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
06795122 169
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170/* Program the config register */
171int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
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172
173/* Enable writing on the SPI flash */
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174static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
175{
176 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
177}
178
a5e8199a 179/* Disable writing on the SPI flash */
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180static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
181{
182 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
183}
184
d25ce7d2 185/*
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186 * Send the read status command to the device and wait for the wip
187 * (write-in-progress) bit to clear itself.
d25ce7d2 188 */
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189int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
190
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191/*
192 * Used for spi_flash write operation
193 * - SPI claim
194 * - spi_flash_cmd_write_enable
195 * - spi_flash_cmd_write
196 * - spi_flash_cmd_wait_ready
197 * - SPI release
198 */
199int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
200 size_t cmd_len, const void *buf, size_t buf_len);
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201
202/*
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203 * Flash write operation, support all possible write commands.
204 * Write the requested data out breaking it up into multiple write
205 * commands as needed per the write size.
6163045b 206 */
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207int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
208 size_t len, const void *buf);
209
210/*
211 * Same as spi_flash_cmd_read() except it also claims/releases the SPI
212 * bus. Used as common part of the ->read() operation.
213 */
214int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
215 size_t cmd_len, void *data, size_t data_len);
216
217/* Flash read operation, support all possible read commands */
218int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
219 size_t len, void *data);
6163045b 220
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221#ifdef CONFIG_SPI_FLASH_MTD
222int spi_flash_mtd_register(struct spi_flash *flash);
223void spi_flash_mtd_unregister(void);
224#endif
225
469146c0 226#endif /* _SF_INTERNAL_H_ */