[people/ms/u-boot.git] / drivers / net / at91_emac.c

/*
 * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
 * Jens Scharsig (esw@bus-elektronik.de)
 *
 * (C) Copyright 2003
 * Author : Hamid Ikdoumi (Atmel)

 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#ifndef CONFIG_AT91_LEGACY
#include <asm/arch/hardware.h>
#include <asm/arch/at91_emac.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#else
/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
#include <asm/arch-at91/at91rm9200.h>
#include <asm/arch-at91/hardware.h>
#include <asm/arch-at91/at91_emac.h>
#include <asm/arch-at91/at91_pmc.h>
#include <asm/arch-at91/at91_pio.h>
#endif
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>

#undef MII_DEBUG
#undef ET_DEBUG

#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
#error AT91 EMAC supports max 1024 RX buffers. \
	Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
#endif

#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
#define CONFIG_DRIVER_AT91EMAC_PHYADDR	0
#endif

/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
#if (AT91C_MASTER_CLOCK > 80000000)
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_64
#elif (AT91C_MASTER_CLOCK > 40000000)
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_32
#elif (AT91C_MASTER_CLOCK > 20000000)
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_16
#else
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_8
#endif

#ifdef ET_DEBUG
#define DEBUG_AT91EMAC(...)	printf(__VA_ARGS__);
#else
#define DEBUG_AT91EMAC(...)
#endif

#ifdef MII_DEBUG
#define DEBUG_AT91PHY(...)	printf(__VA_ARGS__);
#else
#define DEBUG_AT91PHY(...)
#endif

#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
#define VERBOSEP(...)	printf(__VA_ARGS__);
#else
#define VERBOSEP(...)
#endif

#define RBF_ADDR      0xfffffffc
#define RBF_OWNER     (1<<0)
#define RBF_WRAP      (1<<1)
#define RBF_BROADCAST (1<<31)
#define RBF_MULTICAST (1<<30)
#define RBF_UNICAST   (1<<29)
#define RBF_EXTERNAL  (1<<28)
#define RBF_UNKNOWN   (1<<27)
#define RBF_SIZE      0x07ff
#define RBF_LOCAL4    (1<<26)
#define RBF_LOCAL3    (1<<25)
#define RBF_LOCAL2    (1<<24)
#define RBF_LOCAL1    (1<<23)

#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
#define RBF_FRAMELEN 0x600

typedef struct {
	unsigned long addr, size;
} rbf_t;

typedef struct {
	rbf_t 		rbfdt[RBF_FRAMEMAX];
	unsigned long	rbindex;
} emac_device;

void at91emac_EnableMDIO(at91_emac_t *at91mac)
{
	/* Mac CTRL reg set for MDIO enable */
	writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
}

void at91emac_DisableMDIO(at91_emac_t *at91mac)
{
	/* Mac CTRL reg set for MDIO disable */
	writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
}

int  at91emac_read(at91_emac_t *at91mac, unsigned char addr,
		unsigned char reg, unsigned short *value)
{
	unsigned long netstat;
	at91emac_EnableMDIO(at91mac);

	writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
		AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
		AT91_EMAC_MAN_PHYA(addr),
		&at91mac->man);

	do {
		netstat = readl(&at91mac->sr);
		DEBUG_AT91PHY("poll SR %08lx\n", netstat);
	} while (!(netstat & AT91_EMAC_SR_IDLE));

	*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;

	at91emac_DisableMDIO(at91mac);

	DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value)

	return 0;
}

int  at91emac_write(at91_emac_t *at91mac, unsigned char addr,
		unsigned char reg, unsigned short value)
{
	unsigned long netstat;
	DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value)

	at91emac_EnableMDIO(at91mac);

	writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
		AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
		AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
		&at91mac->man);

	do {
		netstat = readl(&at91mac->sr);
		DEBUG_AT91PHY("poll SR %08lx\n", netstat);
	} while (!(netstat & AT91_EMAC_SR_IDLE));

	at91emac_DisableMDIO(at91mac);

	return 0;
}

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)

at91_emac_t *get_emacbase_by_name(const char *devname)
{
	struct eth_device *netdev;

	netdev = eth_get_dev_by_name(devname);
	return (at91_emac_t *) netdev->iobase;
}

int  at91emac_mii_read(const char *devname, unsigned char addr,
		unsigned char reg, unsigned short *value)
{
	at91_emac_t *emac;

	emac = get_emacbase_by_name(devname);
	at91emac_read(emac , addr, reg, value);
	return 0;
}


int  at91emac_mii_write(const char *devname, unsigned char addr,
		unsigned char reg, unsigned short value)
{
	at91_emac_t *emac;

	emac = get_emacbase_by_name(devname);
	at91emac_write(emac, addr, reg, value);
	return 0;
}

#endif

static int at91emac_phy_reset(struct eth_device *netdev)
{
	int i;
	u16 status, adv;
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;

	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
		MII_ADVERTISE, adv);
	VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
		(BMCR_ANENABLE | BMCR_ANRESTART));

	for (i = 0; i < 30000; i++) {
		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
			MII_BMSR, &status);
		if (status & BMSR_ANEGCOMPLETE)
			break;
		udelay(100);
	}

	if (status & BMSR_ANEGCOMPLETE) {
		VERBOSEP("%s: Autonegotiation complete\n", netdev->name);
	} else {
		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
		       netdev->name, status);
		return -1;
	}
	return 0;
}

static int at91emac_phy_init(struct eth_device *netdev)
{
	u16 phy_id, status, adv, lpa;
	int media, speed, duplex;
	int i;
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;

	/* Check if the PHY is up to snuff... */
	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
		MII_PHYSID1, &phy_id);
	if (phy_id == 0xffff) {
		printf("%s: No PHY present\n", netdev->name);
		return -1;
	}

	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
		MII_BMSR, &status);

	if (!(status & BMSR_LSTATUS)) {
		/* Try to re-negotiate if we don't have link already. */
		if (at91emac_phy_reset(netdev))
			return -2;

		for (i = 0; i < 100000 / 100; i++) {
			at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
				MII_BMSR, &status);
			if (status & BMSR_LSTATUS)
				break;
			udelay(100);
		}
	}
	if (!(status & BMSR_LSTATUS)) {
		VERBOSEP("%s: link down\n", netdev->name);
		return -3;
	} else {
		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
			MII_ADVERTISE, &adv);
		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
			MII_LPA, &lpa);
		media = mii_nway_result(lpa & adv);
		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
			 ? 1 : 0);
		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
		VERBOSEP("%s: link up, %sMbps %s-duplex\n",
		       netdev->name,
		       speed ? "100" : "10",
		       duplex ? "full" : "half");
	}
	return 0;
}

int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
{
	unsigned short stat1;

	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);

	if (!(stat1 & BMSR_LSTATUS))	/* link status up? */
		return -1;

	if (stat1 & BMSR_100FULL) {
		/*set Emac for 100BaseTX and Full Duplex  */
		writel(readl(&emac->cfg) |
			AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
			&emac->cfg);
		return 0;
	}

	if (stat1 & BMSR_10FULL) {
		/*set MII for 10BaseT and Full Duplex  */
		writel((readl(&emac->cfg) &
			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
			) | AT91_EMAC_CFG_FD,
			&emac->cfg);
		return 0;
	}

	if (stat1 & BMSR_100HALF) {
		/*set MII for 100BaseTX and Half Duplex  */
		writel((readl(&emac->cfg) &
			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
			) | AT91_EMAC_CFG_SPD,
			&emac->cfg);
		return 0;
	}

	if (stat1 & BMSR_10HALF) {
		/*set MII for 10BaseT and Half Duplex  */
		writel((readl(&emac->cfg) &
			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
			&emac->cfg);
		return 0;
	}
	return 0;
}

static int at91emac_init(struct eth_device *netdev, bd_t *bd)
{
	int i;
	u32 value;
	emac_device *dev;
	at91_emac_t *emac;
	at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;

	emac = (at91_emac_t *) netdev->iobase;
	dev = (emac_device *) netdev->priv;

	/* PIO Disable Register */
	value =	AT91_PMX_AA_EMDIO |	AT91_PMX_AA_EMDC |
		AT91_PMX_AA_ERXER |	AT91_PMX_AA_ERX1 |
		AT91_PMX_AA_ERX0 |	AT91_PMX_AA_ECRS |
		AT91_PMX_AA_ETX1 |	AT91_PMX_AA_ETX0 |
		AT91_PMX_AA_ETXEN |	AT91_PMX_AA_EREFCK;

	writel(value, &pio->pioa.pdr);
	writel(value, &pio->pioa.asr);

#ifdef CONFIG_RMII
	value = AT91_PMX_BA_ERXCK;
#else
	value = AT91_PMX_BA_ERXCK |	AT91_PMX_BA_ECOL |
		AT91_PMX_BA_ERXDV |	AT91_PMX_BA_ERX3 |
		AT91_PMX_BA_ERX2 |	AT91_PMX_BA_ETXER |
		AT91_PMX_BA_ETX3 |	AT91_PMX_BA_ETX2;
#endif
	writel(value, &pio->piob.pdr);
	writel(value, &pio->piob.bsr);

	writel(1 << AT91_ID_EMAC, &pmc->pcer);
	writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);

	/* Init Ethernet buffers */
	for (i = 0; i < RBF_FRAMEMAX; i++) {
		dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
		dev->rbfdt[i].size = 0;
	}
	dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
	dev->rbindex = 0;
	writel((u32) &(dev->rbfdt[0]), &emac->rbqp);

	writel(readl(&emac->rsr) &
		~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
		&emac->rsr);

	value = AT91_EMAC_CFG_CAF |	AT91_EMAC_CFG_NBC |
		HCLK_DIV;
#ifdef CONFIG_RMII
	value |= AT91_EMAC_CFG_RMII;
#endif
	writel(value, &emac->cfg);

	writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
		&emac->ctl);

	if (!at91emac_phy_init(netdev)) {
		at91emac_UpdateLinkSpeed(emac);
		return 0;
	}
	return -1;
}

static void at91emac_halt(struct eth_device *netdev)
{
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;
	writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
		&emac->ctl);
	DEBUG_AT91EMAC("halt MAC\n");
}

static int at91emac_send(struct eth_device *netdev, volatile void *packet,
		     int length)
{
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;

	while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
		;
	writel((u32) packet, &emac->tar);
	writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
	while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
		;
	DEBUG_AT91EMAC("Send %d \n", length);
	writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
	return 0;
}

static int at91emac_recv(struct eth_device *netdev)
{
	emac_device *dev;
	at91_emac_t *emac;
	rbf_t *rbfp;
	int size;

	emac = (at91_emac_t *) netdev->iobase;
	dev = (emac_device *) netdev->priv;

	rbfp = &dev->rbfdt[dev->rbindex];
	while (rbfp->addr & RBF_OWNER)	{
		size = rbfp->size & RBF_SIZE;
		NetReceive(NetRxPackets[dev->rbindex], size);

		DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n",
			dev->rbindex, size, rbfp->addr);

		rbfp->addr &= ~RBF_OWNER;
		rbfp->size = 0;
		if (dev->rbindex < (RBF_FRAMEMAX-1))
			dev->rbindex++;
		else
			dev->rbindex = 0;

		rbfp = &(dev->rbfdt[dev->rbindex]);
		if (!(rbfp->addr & RBF_OWNER))
			writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
				&emac->rsr);
	}

	if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
		/* EMAC silicon bug 41.3.1 workaround 1 */
		writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
		writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
		dev->rbindex = 0;
		printf("%s: reset receiver (EMAC dead lock bug)\n",
			netdev->name);
	}
	return 0;
}

static int at91emac_write_hwaddr(struct eth_device *netdev)
{
	emac_device *dev;
	at91_emac_t *emac;
	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
	emac = (at91_emac_t *) netdev->iobase;
	dev = (emac_device *) netdev->priv;

	writel(1 << AT91_ID_EMAC, &pmc->pcer);
	DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
		cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
		cpu_to_le32(*((u32 *)netdev->enetaddr)));
	writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
	writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
	DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
		readl(&emac->sa2h), readl(&emac->sa2l));
	return 0;
}

int at91emac_register(bd_t *bis, unsigned long iobase)
{
	emac_device *emac;
	emac_device *emacfix;
	struct eth_device *dev;

	if (iobase == 0)
		iobase = AT91_EMAC_BASE;
	emac = malloc(sizeof(*emac)+512);
	if (emac == NULL)
		return -1;
	dev = malloc(sizeof(*dev));
	if (dev == NULL) {
		free(emac);
		return -1;
	}
	/* alignment as per Errata (64 bytes) is insufficient! */
	emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
	memset(emacfix, 0, sizeof(emac_device));

	memset(dev, 0, sizeof(*dev));
	sprintf(dev->name, "emac");
	dev->iobase = iobase;
	dev->priv = emacfix;
	dev->init = at91emac_init;
	dev->halt = at91emac_halt;
	dev->send = at91emac_send;
	dev->recv = at91emac_recv;
	dev->write_hwaddr = at91emac_write_hwaddr;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
#endif
	return 1;
}
Commit	Line	Data
c041e9d2 JS	1	/*
	2	* Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
	3	* Jens Scharsig (esw@bus-elektronik.de)
	4	*
	5	* (C) Copyright 2003
	6	* Author : Hamid Ikdoumi (Atmel)
	7
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <asm/io.h>
	29	#ifndef CONFIG_AT91_LEGACY
	30	#include <asm/arch/hardware.h>
	31	#include <asm/arch/at91_emac.h>
	32	#include <asm/arch/at91_pmc.h>
	33	#include <asm/arch/at91_pio.h>
	34	#else
	35	/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
	36	#include <asm/arch-at91/at91rm9200.h>
	37	#include <asm/arch-at91/hardware.h>
	38	#include <asm/arch-at91/at91_emac.h>
	39	#include <asm/arch-at91/at91_pmc.h>
	40	#include <asm/arch-at91/at91_pio.h>
	41	#endif
	42	#include <net.h>
	43	#include <netdev.h>
	44	#include <malloc.h>
	45	#include <miiphy.h>
	46	#include <linux/mii.h>
	47
	48	#undef MII_DEBUG
	49	#undef ET_DEBUG
	50
	51	#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
	52	#error AT91 EMAC supports max 1024 RX buffers. \
	53	Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
	54	#endif
	55
836cd453 EB	56	#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
	57	#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
	58	#endif
	59
c041e9d2 JS	60	/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
	61	#if (AT91C_MASTER_CLOCK > 80000000)
	62	#define HCLK_DIV AT91_EMAC_CFG_MCLK_64
	63	#elif (AT91C_MASTER_CLOCK > 40000000)
	64	#define HCLK_DIV AT91_EMAC_CFG_MCLK_32
	65	#elif (AT91C_MASTER_CLOCK > 20000000)
	66	#define HCLK_DIV AT91_EMAC_CFG_MCLK_16
	67	#else
	68	#define HCLK_DIV AT91_EMAC_CFG_MCLK_8
	69	#endif
	70
	71	#ifdef ET_DEBUG
	72	#define DEBUG_AT91EMAC(...) printf(__VA_ARGS__);
	73	#else
	74	#define DEBUG_AT91EMAC(...)
	75	#endif
	76
	77	#ifdef MII_DEBUG
	78	#define DEBUG_AT91PHY(...) printf(__VA_ARGS__);
	79	#else
	80	#define DEBUG_AT91PHY(...)
	81	#endif
	82
	83	#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
	84	#define VERBOSEP(...) printf(__VA_ARGS__);
	85	#else
	86	#define VERBOSEP(...)
	87	#endif
	88
	89	#define RBF_ADDR 0xfffffffc
	90	#define RBF_OWNER (1<<0)
	91	#define RBF_WRAP (1<<1)
	92	#define RBF_BROADCAST (1<<31)
	93	#define RBF_MULTICAST (1<<30)
	94	#define RBF_UNICAST (1<<29)
	95	#define RBF_EXTERNAL (1<<28)
6052cbab	96	#define RBF_UNKNOWN (1<<27)
c041e9d2 JS	97	#define RBF_SIZE 0x07ff
	98	#define RBF_LOCAL4 (1<<26)
	99	#define RBF_LOCAL3 (1<<25)
	100	#define RBF_LOCAL2 (1<<24)
	101	#define RBF_LOCAL1 (1<<23)
	102
	103	#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
	104	#define RBF_FRAMELEN 0x600
	105
	106	typedef struct {
	107	unsigned long addr, size;
	108	} rbf_t;
	109
	110	typedef struct {
	111	rbf_t rbfdt[RBF_FRAMEMAX];
	112	unsigned long rbindex;
	113	} emac_device;
	114
	115	void at91emac_EnableMDIO(at91_emac_t *at91mac)
	116	{
	117	/* Mac CTRL reg set for MDIO enable */
	118	writel(readl(&at91mac->ctl) \| AT91_EMAC_CTL_MPE, &at91mac->ctl);
	119	}
	120
	121	void at91emac_DisableMDIO(at91_emac_t *at91mac)
	122	{
	123	/* Mac CTRL reg set for MDIO disable */
	124	writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
	125	}
	126
	127	int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
	128	unsigned char reg, unsigned short *value)
	129	{
38bda019	130	unsigned long netstat;
c041e9d2 JS	131	at91emac_EnableMDIO(at91mac);
	132
	133	writel(AT91_EMAC_MAN_HIGH \| AT91_EMAC_MAN_RW_R \|
	134	AT91_EMAC_MAN_REGA(reg) \| AT91_EMAC_MAN_CODE_802_3 \|
	135	AT91_EMAC_MAN_PHYA(addr),
	136	&at91mac->man);
38bda019 AB	137
	138	do {
	139	netstat = readl(&at91mac->sr);
	140	DEBUG_AT91PHY("poll SR %08lx\n", netstat);
	141	} while (!(netstat & AT91_EMAC_SR_IDLE));
	142
c041e9d2 JS	143	*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
	144
	145	at91emac_DisableMDIO(at91mac);
	146
	147	DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value)
	148
	149	return 0;
	150	}
	151
	152	int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
	153	unsigned char reg, unsigned short value)
	154	{
38bda019	155	unsigned long netstat;
c041e9d2 JS	156	DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value)
	157
	158	at91emac_EnableMDIO(at91mac);
	159
	160	writel(AT91_EMAC_MAN_HIGH \| AT91_EMAC_MAN_RW_W \|
	161	AT91_EMAC_MAN_REGA(reg) \| AT91_EMAC_MAN_CODE_802_3 \|
	162	AT91_EMAC_MAN_PHYA(addr) \| (value & AT91_EMAC_MAN_DATA_MASK),
	163	&at91mac->man);
38bda019 AB	164
	165	do {
	166	netstat = readl(&at91mac->sr);
	167	DEBUG_AT91PHY("poll SR %08lx\n", netstat);
	168	} while (!(netstat & AT91_EMAC_SR_IDLE));
c041e9d2 JS	169
c041e9d2 JS	170	at91emac_DisableMDIO(at91mac);
38bda019	171
c041e9d2 JS	172	return 0;
	173	}
	174
	175	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	176
d7fb9bcf	177	at91_emac_t get_emacbase_by_name(const char devname)
c041e9d2 JS	178	{
	179	struct eth_device *netdev;
	180
	181	netdev = eth_get_dev_by_name(devname);
	182	return (at91_emac_t *) netdev->iobase;
	183	}
	184
5700bb63	185	int at91emac_mii_read(const char *devname, unsigned char addr,
c041e9d2 JS	186	unsigned char reg, unsigned short *value)
	187	{
	188	at91_emac_t *emac;
	189
	190	emac = get_emacbase_by_name(devname);
	191	at91emac_read(emac , addr, reg, value);
	192	return 0;
	193	}
	194
	195
5700bb63	196	int at91emac_mii_write(const char *devname, unsigned char addr,
c041e9d2 JS	197	unsigned char reg, unsigned short value)
	198	{
	199	at91_emac_t *emac;
	200
	201	emac = get_emacbase_by_name(devname);
	202	at91emac_write(emac, addr, reg, value);
	203	return 0;
	204	}
	205
	206	#endif
	207
	208	static int at91emac_phy_reset(struct eth_device *netdev)
	209	{
	210	int i;
	211	u16 status, adv;
	212	at91_emac_t *emac;
	213
	214	emac = (at91_emac_t *) netdev->iobase;
	215
	216	adv = ADVERTISE_CSMA \| ADVERTISE_ALL;
836cd453 EB	217	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	218	MII_ADVERTISE, adv);
c041e9d2	219	VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
836cd453 EB	220	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
836cd453 EB	221	(BMCR_ANENABLE \| BMCR_ANRESTART));
c041e9d2	222
e63ac4cf	223	for (i = 0; i < 30000; i++) {
836cd453 EB	224	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	225	MII_BMSR, &status);
c041e9d2 JS	226	if (status & BMSR_ANEGCOMPLETE)
	227	break;
	228	udelay(100);
	229	}
	230
	231	if (status & BMSR_ANEGCOMPLETE) {
	232	VERBOSEP("%s: Autonegotiation complete\n", netdev->name);
	233	} else {
	234	printf("%s: Autonegotiation timed out (status=0x%04x)\n",
	235	netdev->name, status);
77179067	236	return -1;
c041e9d2 JS	237	}
	238	return 0;
	239	}
	240
	241	static int at91emac_phy_init(struct eth_device *netdev)
	242	{
	243	u16 phy_id, status, adv, lpa;
	244	int media, speed, duplex;
	245	int i;
	246	at91_emac_t *emac;
	247
	248	emac = (at91_emac_t *) netdev->iobase;
	249
	250	/* Check if the PHY is up to snuff... */
836cd453 EB	251	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	252	MII_PHYSID1, &phy_id);
c041e9d2 JS	253	if (phy_id == 0xffff) {
c041e9d2 JS	254	printf("%s: No PHY present\n", netdev->name);
77179067	255	return -1;
c041e9d2 JS	256	}
c041e9d2 JS	257
836cd453 EB	258	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	259	MII_BMSR, &status);
c041e9d2 JS	260
	261	if (!(status & BMSR_LSTATUS)) {
	262	/* Try to re-negotiate if we don't have link already. */
	263	if (at91emac_phy_reset(netdev))
77179067	264	return -2;
c041e9d2 JS	265
c041e9d2 JS	266	for (i = 0; i < 100000 / 100; i++) {
836cd453 EB	267	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	268	MII_BMSR, &status);
c041e9d2 JS	269	if (status & BMSR_LSTATUS)
	270	break;
	271	udelay(100);
	272	}
	273	}
	274	if (!(status & BMSR_LSTATUS)) {
	275	VERBOSEP("%s: link down\n", netdev->name);
77179067	276	return -3;
c041e9d2	277	} else {
836cd453 EB	278	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
	279	MII_ADVERTISE, &adv);
	280	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
	281	MII_LPA, &lpa);
c041e9d2 JS	282	media = mii_nway_result(lpa & adv);
	283	speed = (media & (ADVERTISE_100FULL \| ADVERTISE_100HALF)
	284	? 1 : 0);
	285	duplex = (media & ADVERTISE_FULL) ? 1 : 0;
	286	VERBOSEP("%s: link up, %sMbps %s-duplex\n",
	287	netdev->name,
	288	speed ? "100" : "10",
	289	duplex ? "full" : "half");
	290	}
	291	return 0;
	292	}
	293
	294	int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
	295	{
	296	unsigned short stat1;
	297
836cd453	298	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
c041e9d2 JS	299
c041e9d2 JS	300	if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
77179067	301	return -1;
c041e9d2 JS	302
	303	if (stat1 & BMSR_100FULL) {
	304	/set Emac for 100BaseTX and Full Duplex /
	305	writel(readl(&emac->cfg) \|
	306	AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD,
	307	&emac->cfg);
	308	return 0;
	309	}
	310
	311	if (stat1 & BMSR_10FULL) {
	312	/set MII for 10BaseT and Full Duplex /
	313	writel((readl(&emac->cfg) &
	314	~(AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD)
	315	) \| AT91_EMAC_CFG_FD,
	316	&emac->cfg);
	317	return 0;
	318	}
	319
	320	if (stat1 & BMSR_100HALF) {
	321	/set MII for 100BaseTX and Half Duplex /
	322	writel((readl(&emac->cfg) &
	323	~(AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD)
	324	) \| AT91_EMAC_CFG_SPD,
	325	&emac->cfg);
	326	return 0;
	327	}
	328
	329	if (stat1 & BMSR_10HALF) {
	330	/set MII for 10BaseT and Half Duplex /
	331	writel((readl(&emac->cfg) &
	332	~(AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD)),
	333	&emac->cfg);
	334	return 0;
	335	}
77179067	336	return 0;
c041e9d2 JS	337	}
	338
	339	static int at91emac_init(struct eth_device netdev, bd_t bd)
	340	{
	341	int i;
	342	u32 value;
	343	emac_device *dev;
	344	at91_emac_t *emac;
	345	at91_pio_t pio = (at91_pio_t ) AT91_PIO_BASE;
	346	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
	347
	348	emac = (at91_emac_t *) netdev->iobase;
	349	dev = (emac_device *) netdev->priv;
	350
	351	/* PIO Disable Register */
	352	value = AT91_PMX_AA_EMDIO \| AT91_PMX_AA_EMDC \|
	353	AT91_PMX_AA_ERXER \| AT91_PMX_AA_ERX1 \|
	354	AT91_PMX_AA_ERX0 \| AT91_PMX_AA_ECRS \|
	355	AT91_PMX_AA_ETX1 \| AT91_PMX_AA_ETX0 \|
	356	AT91_PMX_AA_ETXEN \| AT91_PMX_AA_EREFCK;
	357
	358	writel(value, &pio->pioa.pdr);
	359	writel(value, &pio->pioa.asr);
	360
	361	#ifdef CONFIG_RMII
	362	value = AT91_PMX_BA_ERXCK;
	363	#else
	364	value = AT91_PMX_BA_ERXCK \| AT91_PMX_BA_ECOL \|
	365	AT91_PMX_BA_ERXDV \| AT91_PMX_BA_ERX3 \|
	366	AT91_PMX_BA_ERX2 \| AT91_PMX_BA_ETXER \|
	367	AT91_PMX_BA_ETX3 \| AT91_PMX_BA_ETX2;
	368	#endif
	369	writel(value, &pio->piob.pdr);
	370	writel(value, &pio->piob.bsr);
	371
	372	writel(1 << AT91_ID_EMAC, &pmc->pcer);
	373	writel(readl(&emac->ctl) \| AT91_EMAC_CTL_CSR, &emac->ctl);
	374
c041e9d2 JS	375	/* Init Ethernet buffers */
	376	for (i = 0; i < RBF_FRAMEMAX; i++) {
	377	dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
	378	dev->rbfdt[i].size = 0;
	379	}
	380	dev->rbfdt[RBF_FRAMEMAX - 1].addr \|= RBF_WRAP;
	381	dev->rbindex = 0;
	382	writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
	383
	384	writel(readl(&emac->rsr) &
	385	~(AT91_EMAC_RSR_OVR \| AT91_EMAC_RSR_REC \| AT91_EMAC_RSR_BNA),
	386	&emac->rsr);
	387
	388	value = AT91_EMAC_CFG_CAF \| AT91_EMAC_CFG_NBC \|
	389	HCLK_DIV;
	390	#ifdef CONFIG_RMII
836cd453	391	value \|= AT91_EMAC_CFG_RMII;
c041e9d2 JS	392	#endif
	393	writel(value, &emac->cfg);
	394
	395	writel(readl(&emac->ctl) \| AT91_EMAC_CTL_TE \| AT91_EMAC_CTL_RE,
	396	&emac->ctl);
	397
	398	if (!at91emac_phy_init(netdev)) {
	399	at91emac_UpdateLinkSpeed(emac);
	400	return 0;
	401	}
77179067	402	return -1;
c041e9d2 JS	403	}
	404
	405	static void at91emac_halt(struct eth_device *netdev)
	406	{
	407	at91_emac_t *emac;
	408
	409	emac = (at91_emac_t *) netdev->iobase;
	410	writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE \| AT91_EMAC_CTL_RE),
	411	&emac->ctl);
	412	DEBUG_AT91EMAC("halt MAC\n");
	413	}
	414
	415	static int at91emac_send(struct eth_device netdev, volatile void packet,
	416	int length)
	417	{
	418	at91_emac_t *emac;
	419
	420	emac = (at91_emac_t *) netdev->iobase;
	421
	422	while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
	423	;
	424	writel((u32) packet, &emac->tar);
	425	writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
	426	while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
	427	;
	428	DEBUG_AT91EMAC("Send %d \n", length);
	429	writel(readl(&emac->tsr) \| AT91_EMAC_TSR_COMP, &emac->tsr);
	430	return 0;
	431	}
	432
	433	static int at91emac_recv(struct eth_device *netdev)
	434	{
	435	emac_device *dev;
	436	at91_emac_t *emac;
	437	rbf_t *rbfp;
	438	int size;
	439
	440	emac = (at91_emac_t *) netdev->iobase;
	441	dev = (emac_device *) netdev->priv;
	442
	443	rbfp = &dev->rbfdt[dev->rbindex];
	444	while (rbfp->addr & RBF_OWNER) {
	445	size = rbfp->size & RBF_SIZE;
	446	NetReceive(NetRxPackets[dev->rbindex], size);
	447
	448	DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n",
	449	dev->rbindex, size, rbfp->addr);
	450
	451	rbfp->addr &= ~RBF_OWNER;
	452	rbfp->size = 0;
	453	if (dev->rbindex < (RBF_FRAMEMAX-1))
	454	dev->rbindex++;
	455	else
	456	dev->rbindex = 0;
	457
	458	rbfp = &(dev->rbfdt[dev->rbindex]);
	459	if (!(rbfp->addr & RBF_OWNER))
	460	writel(readl(&emac->rsr) \| AT91_EMAC_RSR_REC,
	461	&emac->rsr);
	462	}
	463
	464	if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
	465	/* EMAC silicon bug 41.3.1 workaround 1 */
	466	writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
467	writel(readl(&emac->ctl) \| AT91_EMAC_CTL_RE, &emac->ctl);
468	dev->rbindex = 0;
469	printf("%s: reset receiver (EMAC dead lock bug)\n",
470	netdev->name);
471	}
472	return 0;
473	}
474
409943a9 EB	475	static int at91emac_write_hwaddr(struct eth_device *netdev)
	476	{
	477	emac_device *dev;
	478	at91_emac_t *emac;
	479	at91_pmc_t pmc = (at91_pmc_t ) AT91_PMC_BASE;
	480	emac = (at91_emac_t *) netdev->iobase;
	481	dev = (emac_device *) netdev->priv;
	482
	483	writel(1 << AT91_ID_EMAC, &pmc->pcer);
	484	DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
	485	cpu_to_le16(((u16 )(netdev->enetaddr + 4))),
	486	cpu_to_le32(((u32 )netdev->enetaddr)));
	487	writel(cpu_to_le32(((u32 )netdev->enetaddr)), &emac->sa2l);
	488	writel(cpu_to_le16(((u16 )(netdev->enetaddr + 4))), &emac->sa2h);
	489	DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
	490	readl(&emac->sa2h), readl(&emac->sa2l));
	491	return 0;
	492	}
	493
c041e9d2 JS	494	int at91emac_register(bd_t *bis, unsigned long iobase)
	495	{
	496	emac_device *emac;
	497	emac_device *emacfix;
	498	struct eth_device *dev;
	499
	500	if (iobase == 0)
	501	iobase = AT91_EMAC_BASE;
	502	emac = malloc(sizeof(*emac)+512);
	503	if (emac == NULL)
77179067	504	return -1;
c041e9d2 JS	505	dev = malloc(sizeof(*dev));
	506	if (dev == NULL) {
	507	free(emac);
77179067	508	return -1;
c041e9d2 JS	509	}
	510	/* alignment as per Errata (64 bytes) is insufficient! */
	511	emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
	512	memset(emacfix, 0, sizeof(emac_device));
	513
	514	memset(dev, 0, sizeof(*dev));
4b8d77bb	515	sprintf(dev->name, "emac");
c041e9d2 JS	516	dev->iobase = iobase;
	517	dev->priv = emacfix;
	518	dev->init = at91emac_init;
	519	dev->halt = at91emac_halt;
	520	dev->send = at91emac_send;
	521	dev->recv = at91emac_recv;
409943a9	522	dev->write_hwaddr = at91emac_write_hwaddr;
c041e9d2 JS	523
	524	eth_register(dev);
	525
	526	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	527	miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
	528	#endif
	529	return 1;
	530	}