[people/ms/u-boot.git] / drivers / net / cs8900.c

/*
 * Cirrus Logic CS8900A Ethernet
 *
 * (C) 2009 Ben Warren , biggerbadderben@gmail.com
 *     Converted to use CONFIG_NET_MULTI API
 *
 * (C) 2003 Wolfgang Denk, wd@denx.de
 *     Extension to synchronize ethaddr environment variable
 *     against value in EEPROM
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
 *
 * This program is loaded into SRAM in bootstrap mode, where it waits
 * for commands on UART1 to read and write memory, jump to code etc.
 * A design goal for this program is to be entirely independent of the
 * target board.  Anything with a CL-PS7111 or EP7211 should be able to run
 * this code in bootstrap mode.  All the board specifics can be handled on
 * the host.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <net.h>
#include <malloc.h>
#include "cs8900.h"

#undef DEBUG

/* packet page register access functions */

#ifdef CONFIG_CS8900_BUS32

#define REG_WRITE(v, a) writel((v),(a))
#define REG_READ(a) readl((a))

/* we don't need 16 bit initialisation on 32 bit bus */
#define get_reg_init_bus(r,d) get_reg((r),(d))

#else

#define REG_WRITE(v, a) writew((v),(a))
#define REG_READ(a) readw((a))

static u16 get_reg_init_bus(struct eth_device *dev, int regno)
{
	/* force 16 bit busmode */
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
	uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;

	readb(iob);
	readb(iob + 1);
	readb(iob);
	readb(iob + 1);
	readb(iob);

	REG_WRITE(regno, &priv->regs->pptr);
	return REG_READ(&priv->regs->pdata);
}
#endif

static u16 get_reg(struct eth_device *dev, int regno)
{
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
	REG_WRITE(regno, &priv->regs->pptr);
	return REG_READ(&priv->regs->pdata);
}


static void put_reg(struct eth_device *dev, int regno, u16 val)
{
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
	REG_WRITE(regno, &priv->regs->pptr);
	REG_WRITE(val, &priv->regs->pdata);
}

static void cs8900_reset(struct eth_device *dev)
{
	int tmo;
	u16 us;

	/* reset NIC */
	put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);

	/* wait for 200ms */
	udelay(200000);
	/* Wait until the chip is reset */

	tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
	while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
		PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
		/*NOP*/;
}

static void cs8900_reginit(struct eth_device *dev)
{
	/* receive only error free packets addressed to this card */
	put_reg(dev, PP_RxCTL,
		PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
	/* do not generate any interrupts on receive operations */
	put_reg(dev, PP_RxCFG, 0);
	/* do not generate any interrupts on transmit operations */
	put_reg(dev, PP_TxCFG, 0);
	/* do not generate any interrupts on buffer operations */
	put_reg(dev, PP_BufCFG, 0);
	/* enable transmitter/receiver mode */
	put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
}

void cs8900_get_enetaddr(struct eth_device *dev)
{
	int i;

	/* verify chip id */
	if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
		return;
	cs8900_reset(dev);
	if ((get_reg(dev, PP_SelfSTAT) &
		(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
		(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {

		/* Load the MAC from EEPROM */
		for (i = 0; i < 3; i++) {
			u32 Addr;

			Addr = get_reg(dev, PP_IA + i * 2);
			dev->enetaddr[i * 2] = Addr & 0xFF;
			dev->enetaddr[i * 2 + 1] = Addr >> 8;
		}
	}
}

void cs8900_halt(struct eth_device *dev)
{
	/* disable transmitter/receiver mode */
	put_reg(dev, PP_LineCTL, 0);

	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
	get_reg_init_bus(dev, PP_ChipID);
}

static int cs8900_init(struct eth_device *dev, bd_t * bd)
{
	uchar *enetaddr = dev->enetaddr;
	u16 id;

	/* verify chip id */
	id = get_reg_init_bus(dev, PP_ChipID);
	if (id != 0x630e) {
		printf ("CS8900 Ethernet chip not found: "
			"ID=0x%04x instead 0x%04x\n", id, 0x630e);
		return 1;
	}

	cs8900_reset (dev);
	/* set the ethernet address */
	put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
	put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
	put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));

	cs8900_reginit(dev);
	return 0;
}

/* Get a data block via Ethernet */
static int cs8900_recv(struct eth_device *dev)
{
	int i;
	u16 rxlen;
	u16 *addr;
	u16 status;

	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);

	status = get_reg(dev, PP_RER);

	if ((status & PP_RER_RxOK) == 0)
		return 0;

	status = REG_READ(&priv->regs->rtdata);
	rxlen = REG_READ(&priv->regs->rtdata);

	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
		debug("packet too big!\n");
	for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
		*addr++ = REG_READ(&priv->regs->rtdata);
	if (rxlen & 1)
		*addr++ = REG_READ(&priv->regs->rtdata);

	/* Pass the packet up to the protocol layers. */
	net_process_received_packet(net_rx_packets[0], rxlen);
	return rxlen;
}

/* Send a data block via Ethernet. */
static int cs8900_send(struct eth_device *dev, void *packet, int length)
{
	volatile u16 *addr;
	int tmo;
	u16 s;
	struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);

retry:
	/* initiate a transmit sequence */
	REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
	REG_WRITE(length, &priv->regs->txlen);

	/* Test to see if the chip has allocated memory for the packet */
	if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
		/* Oops... this should not happen! */
		debug("cs: unable to send packet; retrying...\n");
		for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
			get_timer(0) < tmo;)
			/*NOP*/;
		cs8900_reset(dev);
		cs8900_reginit(dev);
		goto retry;
	}

	/* Write the contents of the packet */
	/* assume even number of bytes */
	for (addr = packet; length > 0; length -= 2)
		REG_WRITE(*addr++, &priv->regs->rtdata);

	/* wait for transfer to succeed */
	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
		if (get_timer(0) >= tmo)
			break;
	}

	/* nothing */ ;
	if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
		debug("\ntransmission error %#x\n", s);
	}

	return 0;
}

static void cs8900_e2prom_ready(struct eth_device *dev)
{
	while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
		;
}

/***********************************************************/
/* read a 16-bit word out of the EEPROM                    */
/***********************************************************/

int cs8900_e2prom_read(struct eth_device *dev,
			u8 addr, u16 *value)
{
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
	cs8900_e2prom_ready(dev);
	*value = get_reg(dev, PP_EEData);

	return 0;
}


/***********************************************************/
/* write a 16-bit word into the EEPROM                     */
/***********************************************************/

int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
{
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EEData, value);
	put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
	cs8900_e2prom_ready(dev);
	put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
	cs8900_e2prom_ready(dev);

	return 0;
}

int cs8900_initialize(u8 dev_num, int base_addr)
{
	struct eth_device *dev;
	struct cs8900_priv *priv;

	dev = malloc(sizeof(*dev));
	if (!dev) {
		return 0;
	}
	memset(dev, 0, sizeof(*dev));

	priv = malloc(sizeof(*priv));
	if (!priv) {
		free(dev);
		return 0;
	}
	memset(priv, 0, sizeof(*priv));
	priv->regs = (struct cs8900_regs *)base_addr;

	dev->iobase = base_addr;
	dev->priv = priv;
	dev->init = cs8900_init;
	dev->halt = cs8900_halt;
	dev->send = cs8900_send;
	dev->recv = cs8900_recv;

	/* Load MAC address from EEPROM */
	cs8900_get_enetaddr(dev);

	sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);

	eth_register(dev);
	return 0;
}
Commit	Line	Data
c609719b WD	1	/*
	2	* Cirrus Logic CS8900A Ethernet
	3	*
b1c0eaac BW	4	* (C) 2009 Ben Warren , biggerbadderben@gmail.com
	5	* Converted to use CONFIG_NET_MULTI API
	6	*
6069ff26 WD	7	* (C) 2003 Wolfgang Denk, wd@denx.de
	8	* Extension to synchronize ethaddr environment variable
	9	* against value in EEPROM
	10	*
c609719b WD	11	* (C) Copyright 2002
	12	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	13	* Marius Groeger <mgroeger@sysgo.de>
	14	*
	15	* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
	16	*
c609719b WD	17	* This program is loaded into SRAM in bootstrap mode, where it waits
	18	* for commands on UART1 to read and write memory, jump to code etc.
	19	* A design goal for this program is to be entirely independent of the
	20	* target board. Anything with a CL-PS7111 or EP7211 should be able to run
	21	* this code in bootstrap mode. All the board specifics can be handled on
	22	* the host.
	23	*
1a459660	24	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	25	*/
	26
	27	#include <common.h>
	28	#include <command.h>
b1c0eaac	29	#include <asm/io.h>
c609719b	30	#include <net.h>
b1c0eaac BW	31	#include <malloc.h>
b1c0eaac BW	32	#include "cs8900.h"
c609719b	33
a2663ea4	34	#undef DEBUG
c609719b WD	35
	36	/* packet page register access functions */
	37
b1c0eaac BW	38	#ifdef CONFIG_CS8900_BUS32
	39
	40	#define REG_WRITE(v, a) writel((v),(a))
	41	#define REG_READ(a) readl((a))
	42
c609719b	43	/* we don't need 16 bit initialisation on 32 bit bus */
830c7b67	44	#define get_reg_init_bus(r,d) get_reg((r),(d))
b1c0eaac	45
c609719b	46	#else
6069ff26	47
b1c0eaac BW	48	#define REG_WRITE(v, a) writew((v),(a))
b1c0eaac BW	49	#define REG_READ(a) readw((a))
6069ff26	50
b1c0eaac BW	51	static u16 get_reg_init_bus(struct eth_device *dev, int regno)
	52	{
	53	/* force 16 bit busmode */
b1c0eaac BW	54	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	55	uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
	56
da227355 AG	57	readb(iob);
	58	readb(iob + 1);
	59	readb(iob);
	60	readb(iob + 1);
	61	readb(iob);
b1c0eaac BW	62
	63	REG_WRITE(regno, &priv->regs->pptr);
	64	return REG_READ(&priv->regs->pdata);
c609719b WD	65	}
	66	#endif
	67
b1c0eaac	68	static u16 get_reg(struct eth_device *dev, int regno)
c609719b	69	{
b1c0eaac BW	70	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	71	REG_WRITE(regno, &priv->regs->pptr);
	72	return REG_READ(&priv->regs->pdata);
c609719b WD	73	}
	74
	75
b1c0eaac	76	static void put_reg(struct eth_device *dev, int regno, u16 val)
c609719b	77	{
b1c0eaac BW	78	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	79	REG_WRITE(regno, &priv->regs->pptr);
	80	REG_WRITE(val, &priv->regs->pdata);
c609719b WD	81	}
c609719b WD	82
b1c0eaac	83	static void cs8900_reset(struct eth_device *dev)
c609719b	84	{
6069ff26	85	int tmo;
b1c0eaac	86	u16 us;
c609719b	87
6069ff26	88	/* reset NIC */
b1c0eaac	89	put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) \| PP_SelfCTL_Reset);
c609719b	90
6069ff26	91	/* wait for 200ms */
b1c0eaac	92	udelay(200000);
6069ff26	93	/* Wait until the chip is reset */
c609719b	94
b1c0eaac BW	95	tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
	96	while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
	97	PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
6069ff26	98	/NOP/;
c609719b WD	99	}
c609719b WD	100
b1c0eaac	101	static void cs8900_reginit(struct eth_device *dev)
a2663ea4 WD	102	{
a2663ea4 WD	103	/* receive only error free packets addressed to this card */
b1c0eaac BW	104	put_reg(dev, PP_RxCTL,
b1c0eaac BW	105	PP_RxCTL_IA \| PP_RxCTL_Broadcast \| PP_RxCTL_RxOK);
a2663ea4	106	/* do not generate any interrupts on receive operations */
b1c0eaac	107	put_reg(dev, PP_RxCFG, 0);
a2663ea4	108	/* do not generate any interrupts on transmit operations */
b1c0eaac	109	put_reg(dev, PP_TxCFG, 0);
a2663ea4	110	/* do not generate any interrupts on buffer operations */
b1c0eaac	111	put_reg(dev, PP_BufCFG, 0);
a2663ea4	112	/* enable transmitter/receiver mode */
b1c0eaac	113	put_reg(dev, PP_LineCTL, PP_LineCTL_Rx \| PP_LineCTL_Tx);
a2663ea4 WD	114	}
a2663ea4 WD	115
b1c0eaac	116	void cs8900_get_enetaddr(struct eth_device *dev)
c609719b	117	{
6069ff26	118	int i;
6069ff26 WD	119
6069ff26 WD	120	/* verify chip id */
b1c0eaac	121	if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
6069ff26	122	return;
b1c0eaac BW	123	cs8900_reset(dev);
	124	if ((get_reg(dev, PP_SelfSTAT) &
	125	(PP_SelfSTAT_EEPROM \| PP_SelfSTAT_EEPROM_OK)) ==
	126	(PP_SelfSTAT_EEPROM \| PP_SelfSTAT_EEPROM_OK)) {
6069ff26 WD	127
6069ff26 WD	128	/* Load the MAC from EEPROM */
b1c0eaac BW	129	for (i = 0; i < 3; i++) {
b1c0eaac BW	130	u32 Addr;
6069ff26	131
b1c0eaac BW	132	Addr = get_reg(dev, PP_IA + i * 2);
	133	dev->enetaddr[i * 2] = Addr & 0xFF;
	134	dev->enetaddr[i * 2 + 1] = Addr >> 8;
6069ff26	135	}
c609719b	136	}
c609719b WD	137	}
c609719b WD	138
b1c0eaac	139	void cs8900_halt(struct eth_device *dev)
c609719b	140	{
6069ff26	141	/* disable transmitter/receiver mode */
b1c0eaac	142	put_reg(dev, PP_LineCTL, 0);
c609719b	143
6069ff26	144	/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
b1c0eaac	145	get_reg_init_bus(dev, PP_ChipID);
c609719b WD	146	}
c609719b WD	147
b1c0eaac	148	static int cs8900_init(struct eth_device dev, bd_t bd)
c609719b	149	{
b1c0eaac BW	150	uchar *enetaddr = dev->enetaddr;
b1c0eaac BW	151	u16 id;
0a5238ce	152
6069ff26	153	/* verify chip id */
b1c0eaac BW	154	id = get_reg_init_bus(dev, PP_ChipID);
	155	if (id != 0x630e) {
	156	printf ("CS8900 Ethernet chip not found: "
	157	"ID=0x%04x instead 0x%04x\n", id, 0x630e);
	158	return 1;
6069ff26	159	}
c609719b	160
b1c0eaac	161	cs8900_reset (dev);
6069ff26	162	/* set the ethernet address */
b1c0eaac BW	163	put_reg(dev, PP_IA + 0, enetaddr[0] \| (enetaddr[1] << 8));
	164	put_reg(dev, PP_IA + 2, enetaddr[2] \| (enetaddr[3] << 8));
	165	put_reg(dev, PP_IA + 4, enetaddr[4] \| (enetaddr[5] << 8));
c609719b	166
b1c0eaac	167	cs8900_reginit(dev);
6069ff26	168	return 0;
c609719b WD	169	}
	170
	171	/* Get a data block via Ethernet */
b1c0eaac	172	static int cs8900_recv(struct eth_device *dev)
c609719b	173	{
6069ff26	174	int i;
b1c0eaac BW	175	u16 rxlen;
	176	u16 *addr;
	177	u16 status;
c609719b	178
b1c0eaac BW	179	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
	180
	181	status = get_reg(dev, PP_RER);
c609719b	182
6069ff26 WD	183	if ((status & PP_RER_RxOK) == 0)
6069ff26 WD	184	return 0;
c609719b	185
b1c0eaac BW	186	status = REG_READ(&priv->regs->rtdata);
b1c0eaac BW	187	rxlen = REG_READ(&priv->regs->rtdata);
c609719b	188
6069ff26	189	if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
b1c0eaac	190	debug("packet too big!\n");
1fd92db8	191	for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
b1c0eaac	192	*addr++ = REG_READ(&priv->regs->rtdata);
6069ff26	193	if (rxlen & 1)
b1c0eaac	194	*addr++ = REG_READ(&priv->regs->rtdata);
c609719b	195
6069ff26	196	/* Pass the packet up to the protocol layers. */
1fd92db8	197	net_process_received_packet(net_rx_packets[0], rxlen);
6069ff26	198	return rxlen;
c609719b WD	199	}
	200
	201	/* Send a data block via Ethernet. */
9d295177	202	static int cs8900_send(struct eth_device dev, void packet, int length)
c609719b	203	{
b1c0eaac	204	volatile u16 *addr;
6069ff26	205	int tmo;
b1c0eaac BW	206	u16 s;
b1c0eaac BW	207	struct cs8900_priv priv = (struct cs8900_priv )(dev->priv);
c609719b WD	208
c609719b WD	209	retry:
6069ff26	210	/* initiate a transmit sequence */
b1c0eaac BW	211	REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
b1c0eaac BW	212	REG_WRITE(length, &priv->regs->txlen);
6069ff26 WD	213
6069ff26 WD	214	/* Test to see if the chip has allocated memory for the packet */
b1c0eaac	215	if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
6069ff26	216	/* Oops... this should not happen! */
b1c0eaac BW	217	debug("cs: unable to send packet; retrying...\n");
	218	for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	219	get_timer(0) < tmo;)
6069ff26	220	/NOP/;
b1c0eaac BW	221	cs8900_reset(dev);
b1c0eaac BW	222	cs8900_reginit(dev);
6069ff26 WD	223	goto retry;
	224	}
	225
	226	/* Write the contents of the packet */
	227	/* assume even number of bytes */
	228	for (addr = packet; length > 0; length -= 2)
b1c0eaac	229	REG_WRITE(*addr++, &priv->regs->rtdata);
6069ff26 WD	230
6069ff26 WD	231	/* wait for transfer to succeed */
b1c0eaac BW	232	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	233	while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
	234	if (get_timer(0) >= tmo)
6069ff26 WD	235	break;
	236	}
	237
	238	/* nothing */ ;
b1c0eaac BW	239	if((s & (PP_TER_CRS \| PP_TER_TxOK)) != PP_TER_TxOK) {
b1c0eaac BW	240	debug("\ntransmission error %#x\n", s);
6069ff26 WD	241	}
	242
	243	return 0;
c609719b WD	244	}
c609719b WD	245
b1c0eaac	246	static void cs8900_e2prom_ready(struct eth_device *dev)
1cb8e980	247	{
b1c0eaac	248	while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
13e0b8f7	249	;
1cb8e980 WD	250	}
	251
	252	/***********************************************************/
	253	/* read a 16-bit word out of the EEPROM */
	254	/***********************************************************/
	255
b1c0eaac BW	256	int cs8900_e2prom_read(struct eth_device *dev,
b1c0eaac BW	257	u8 addr, u16 *value)
1cb8e980	258	{
b1c0eaac BW	259	cs8900_e2prom_ready(dev);
	260	put_reg(dev, PP_EECMD, EEPROM_READ_CMD \| addr);
	261	cs8900_e2prom_ready(dev);
	262	*value = get_reg(dev, PP_EEData);
1cb8e980 WD	263
	264	return 0;
	265	}
	266
	267
	268	/***********************************************************/
	269	/* write a 16-bit word into the EEPROM */
	270	/***********************************************************/
	271
b1c0eaac BW	272	int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
	273	{
	274	cs8900_e2prom_ready(dev);
	275	put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
	276	cs8900_e2prom_ready(dev);
	277	put_reg(dev, PP_EEData, value);
	278	put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD \| addr);
	279	cs8900_e2prom_ready(dev);
	280	put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
	281	cs8900_e2prom_ready(dev);
	282
	283	return 0;
	284	}
	285
	286	int cs8900_initialize(u8 dev_num, int base_addr)
1cb8e980	287	{
b1c0eaac BW	288	struct eth_device *dev;
	289	struct cs8900_priv *priv;
	290
	291	dev = malloc(sizeof(*dev));
	292	if (!dev) {
b1c0eaac BW	293	return 0;
	294	}
	295	memset(dev, 0, sizeof(*dev));
	296
	297	priv = malloc(sizeof(*priv));
	298	if (!priv) {
07c96606	299	free(dev);
b1c0eaac BW	300	return 0;
	301	}
	302	memset(priv, 0, sizeof(*priv));
	303	priv->regs = (struct cs8900_regs *)base_addr;
	304
b1c0eaac BW	305	dev->iobase = base_addr;
	306	dev->priv = priv;
	307	dev->init = cs8900_init;
	308	dev->halt = cs8900_halt;
	309	dev->send = cs8900_send;
	310	dev->recv = cs8900_recv;
497ab0ee HT	311
	312	/* Load MAC address from EEPROM */
	313	cs8900_get_enetaddr(dev);
	314
b1c0eaac	315	sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
1cb8e980	316
b1c0eaac	317	eth_register(dev);
06d01dbe	318	return 0;
1cb8e980	319	}