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[people/ms/u-boot.git] / drivers / net / e1000.c
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682011ff 1/**************************************************************************
ac3315c2 2Intel Pro 1000 for ppcboot/das-u-boot
682011ff
WD		 3Drivers are port from Intel's Linux driver e1000-4.3.15
4and from Etherboot pro 1000 driver by mrakes at vivato dot net
5tested on both gig copper and gig fiber boards
6***************************************************************************/
7/*******************************************************************************
8
8bde7f77 9
682011ff 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
8bde7f77 11
1a459660 12 * SPDX-License-Identifier: GPL-2.0+
8bde7f77 13
682011ff
WD		 14 Contact Information:
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17
18*******************************************************************************/
19/*
20 * Copyright (C) Archway Digital Solutions.
21 *
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
23 * 2/9/2002
24 *
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
2c2668f9
RZ		 28 *
29 * Copyright 2011 Freescale Semiconductor, Inc.
682011ff
WD		 30 */
31
32#include "e1000.h"
33
682011ff
WD		 34#define TOUT_LOOP 100000
35
f81ecb5d 36#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
682011ff 37#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
682011ff 38
9ea005fb
RZ		 39#define E1000_DEFAULT_PCI_PBA 0x00000030
40#define E1000_DEFAULT_PCIE_PBA 0x000a0026
682011ff
WD		 41
42/* NIC specific static variables go here */
43
873e8e01
MV		 44/* Intel i210 needs the DMA descriptor rings aligned to 128b */
45#define E1000_BUFFER_ALIGN 128
682011ff 46
873e8e01
MV		 47DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
48DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
49DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
682011ff
WD		 50
51static int tx_tail;
52static int rx_tail, rx_last;
53
d60626f8 54static struct pci_device_id e1000_supported[] = {
682011ff
WD		 55 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
56 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
57 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
58 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
59 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
60 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
61 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
62 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
63 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
8915f118 64 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
682011ff
WD		 65 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
66 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
67 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
2ab4a4d0 68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
682011ff 69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
ac3315c2 70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
aa3b8bf9 71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
aa070789
RZ		 72 /* E1000 PCIe card */
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
2c2668f9 89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
aa070789
RZ		 90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
6c499abe
MZ		 95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
95186063 97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
6c499abe 98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
95186063
MV		 99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
103
1bc43437 104 {}
682011ff
WD		 105};
106
107/* Function forward declarations */
108static int e1000_setup_link(struct eth_device *nic);
109static int e1000_setup_fiber_link(struct eth_device *nic);
110static int e1000_setup_copper_link(struct eth_device *nic);
111static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
112static void e1000_config_collision_dist(struct e1000_hw *hw);
113static int e1000_config_mac_to_phy(struct e1000_hw *hw);
114static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
115static int e1000_check_for_link(struct eth_device *nic);
116static int e1000_wait_autoneg(struct e1000_hw *hw);
aa070789 117static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
682011ff
WD		 118 uint16_t * duplex);
119static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
120 uint16_t * phy_data);
121static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
122 uint16_t phy_data);
aa070789 123static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
682011ff
WD		 124static int e1000_phy_reset(struct e1000_hw *hw);
125static int e1000_detect_gig_phy(struct e1000_hw *hw);
aa070789
RZ		 126static void e1000_set_media_type(struct e1000_hw *hw);
127
128static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
129static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
682011ff 130
8712adfd
RI		 131#ifndef CONFIG_E1000_NO_NVM
132static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
ecbd2078
RZ		 133static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
134 uint16_t words,
135 uint16_t *data);
682011ff
WD		 136/******************************************************************************
137 * Raises the EEPROM's clock input.
138 *
139 * hw - Struct containing variables accessed by shared code
140 * eecd - EECD's current value
141 *****************************************************************************/
2326a94d 142void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
682011ff
WD		 143{
144 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
145 * wait 50 microseconds.
146 */
147 *eecd = *eecd | E1000_EECD_SK;
148 E1000_WRITE_REG(hw, EECD, *eecd);
149 E1000_WRITE_FLUSH(hw);
150 udelay(50);
151}
152
153/******************************************************************************
154 * Lowers the EEPROM's clock input.
155 *
8bde7f77 156 * hw - Struct containing variables accessed by shared code
682011ff
WD		 157 * eecd - EECD's current value
158 *****************************************************************************/
2326a94d 159void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
682011ff 160{
8bde7f77
WD		 161 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
162 * wait 50 microseconds.
682011ff
WD		 163 */
164 *eecd = *eecd & ~E1000_EECD_SK;
165 E1000_WRITE_REG(hw, EECD, *eecd);
166 E1000_WRITE_FLUSH(hw);
167 udelay(50);
168}
169
170/******************************************************************************
171 * Shift data bits out to the EEPROM.
172 *
173 * hw - Struct containing variables accessed by shared code
174 * data - data to send to the EEPROM
175 * count - number of bits to shift out
176 *****************************************************************************/
177static void
178e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
179{
180 uint32_t eecd;
181 uint32_t mask;
182
183 /* We need to shift "count" bits out to the EEPROM. So, value in the
184 * "data" parameter will be shifted out to the EEPROM one bit at a time.
8bde7f77 185 * In order to do this, "data" must be broken down into bits.
682011ff
WD		 186 */
187 mask = 0x01 << (count - 1);
188 eecd = E1000_READ_REG(hw, EECD);
189 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
190 do {
191 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
192 * and then raising and then lowering the clock (the SK bit controls
193 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
194 * by setting "DI" to "0" and then raising and then lowering the clock.
195 */
196 eecd &= ~E1000_EECD_DI;
197
198 if (data & mask)
199 eecd |= E1000_EECD_DI;
200
201 E1000_WRITE_REG(hw, EECD, eecd);
202 E1000_WRITE_FLUSH(hw);
203
204 udelay(50);
205
206 e1000_raise_ee_clk(hw, &eecd);
207 e1000_lower_ee_clk(hw, &eecd);
208
209 mask = mask >> 1;
210
211 } while (mask);
212
213 /* We leave the "DI" bit set to "0" when we leave this routine. */
214 eecd &= ~E1000_EECD_DI;
215 E1000_WRITE_REG(hw, EECD, eecd);
216}
217
218/******************************************************************************
219 * Shift data bits in from the EEPROM
220 *
221 * hw - Struct containing variables accessed by shared code
222 *****************************************************************************/
223static uint16_t
aa070789 224e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
682011ff
WD		 225{
226 uint32_t eecd;
227 uint32_t i;
228 uint16_t data;
229
aa070789
RZ		 230 /* In order to read a register from the EEPROM, we need to shift 'count'
231 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
232 * input to the EEPROM (setting the SK bit), and then reading the
233 * value of the "DO" bit. During this "shifting in" process the
234 * "DI" bit should always be clear.
682011ff
WD		 235 */
236
237 eecd = E1000_READ_REG(hw, EECD);
238
239 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
240 data = 0;
241
aa070789 242 for (i = 0; i < count; i++) {
682011ff
WD		 243 data = data << 1;
244 e1000_raise_ee_clk(hw, &eecd);
245
246 eecd = E1000_READ_REG(hw, EECD);
247
248 eecd &= ~(E1000_EECD_DI);
249 if (eecd & E1000_EECD_DO)
250 data |= 1;
251
252 e1000_lower_ee_clk(hw, &eecd);
253 }
254
255 return data;
256}
257
258/******************************************************************************
aa070789 259 * Returns EEPROM to a "standby" state
682011ff
WD		 260 *
261 * hw - Struct containing variables accessed by shared code
682011ff 262 *****************************************************************************/
2326a94d 263void e1000_standby_eeprom(struct e1000_hw *hw)
682011ff 264{
aa070789 265 struct e1000_eeprom_info *eeprom = &hw->eeprom;
682011ff
WD		 266 uint32_t eecd;
267
268 eecd = E1000_READ_REG(hw, EECD);
269
aa070789
RZ		 270 if (eeprom->type == e1000_eeprom_microwire) {
271 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
272 E1000_WRITE_REG(hw, EECD, eecd);
273 E1000_WRITE_FLUSH(hw);
274 udelay(eeprom->delay_usec);
682011ff 275
aa070789
RZ		 276 /* Clock high */
277 eecd |= E1000_EECD_SK;
278 E1000_WRITE_REG(hw, EECD, eecd);
279 E1000_WRITE_FLUSH(hw);
280 udelay(eeprom->delay_usec);
281
282 /* Select EEPROM */
283 eecd |= E1000_EECD_CS;
284 E1000_WRITE_REG(hw, EECD, eecd);
285 E1000_WRITE_FLUSH(hw);
286 udelay(eeprom->delay_usec);
287
288 /* Clock low */
289 eecd &= ~E1000_EECD_SK;
290 E1000_WRITE_REG(hw, EECD, eecd);
291 E1000_WRITE_FLUSH(hw);
292 udelay(eeprom->delay_usec);
293 } else if (eeprom->type == e1000_eeprom_spi) {
294 /* Toggle CS to flush commands */
295 eecd |= E1000_EECD_CS;
296 E1000_WRITE_REG(hw, EECD, eecd);
297 E1000_WRITE_FLUSH(hw);
298 udelay(eeprom->delay_usec);
299 eecd &= ~E1000_EECD_CS;
300 E1000_WRITE_REG(hw, EECD, eecd);
301 E1000_WRITE_FLUSH(hw);
302 udelay(eeprom->delay_usec);
303 }
304}
305
306/***************************************************************************
307* Description: Determines if the onboard NVM is FLASH or EEPROM.
308*
309* hw - Struct containing variables accessed by shared code
310****************************************************************************/
472d5460 311static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
aa070789
RZ		 312{
313 uint32_t eecd = 0;
314
315 DEBUGFUNC();
316
317 if (hw->mac_type == e1000_ich8lan)
472d5460 318 return false;
aa070789 319
2c2668f9 320 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
aa070789
RZ		 321 eecd = E1000_READ_REG(hw, EECD);
322
323 /* Isolate bits 15 & 16 */
324 eecd = ((eecd >> 15) & 0x03);
325
326 /* If both bits are set, device is Flash type */
327 if (eecd == 0x03)
472d5460 328 return false;
aa070789 329 }
472d5460 330 return true;
682011ff
WD		 331}
332
333/******************************************************************************
aa070789 334 * Prepares EEPROM for access
8bde7f77 335 *
682011ff 336 * hw - Struct containing variables accessed by shared code
aa070789
RZ		 337 *
338 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
339 * function should be called before issuing a command to the EEPROM.
682011ff 340 *****************************************************************************/
2326a94d 341int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
682011ff 342{
aa070789
RZ		 343 struct e1000_eeprom_info *eeprom = &hw->eeprom;
344 uint32_t eecd, i = 0;
682011ff 345
f81ecb5d 346 DEBUGFUNC();
aa070789
RZ		 347
348 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
349 return -E1000_ERR_SWFW_SYNC;
682011ff
WD		 350 eecd = E1000_READ_REG(hw, EECD);
351
95186063 352 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
aa070789
RZ		 353 /* Request EEPROM Access */
354 if (hw->mac_type > e1000_82544) {
355 eecd |= E1000_EECD_REQ;
356 E1000_WRITE_REG(hw, EECD, eecd);
357 eecd = E1000_READ_REG(hw, EECD);
358 while ((!(eecd & E1000_EECD_GNT)) &&
359 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
360 i++;
361 udelay(5);
362 eecd = E1000_READ_REG(hw, EECD);
363 }
364 if (!(eecd & E1000_EECD_GNT)) {
365 eecd &= ~E1000_EECD_REQ;
366 E1000_WRITE_REG(hw, EECD, eecd);
367 DEBUGOUT("Could not acquire EEPROM grant\n");
368 return -E1000_ERR_EEPROM;
369 }
370 }
371 }
682011ff 372
aa070789 373 /* Setup EEPROM for Read/Write */
682011ff 374
aa070789
RZ		 375 if (eeprom->type == e1000_eeprom_microwire) {
376 /* Clear SK and DI */
377 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
378 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 379
aa070789
RZ		 380 /* Set CS */
381 eecd |= E1000_EECD_CS;
382 E1000_WRITE_REG(hw, EECD, eecd);
383 } else if (eeprom->type == e1000_eeprom_spi) {
384 /* Clear SK and CS */
385 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
386 E1000_WRITE_REG(hw, EECD, eecd);
387 udelay(1);
388 }
389
390 return E1000_SUCCESS;
682011ff
WD		 391}
392
393/******************************************************************************
aa070789
RZ		 394 * Sets up eeprom variables in the hw struct. Must be called after mac_type
395 * is configured. Additionally, if this is ICH8, the flash controller GbE
396 * registers must be mapped, or this will crash.
682011ff
WD		 397 *
398 * hw - Struct containing variables accessed by shared code
682011ff 399 *****************************************************************************/
aa070789 400static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
682011ff 401{
aa070789 402 struct e1000_eeprom_info *eeprom = &hw->eeprom;
95186063 403 uint32_t eecd;
aa070789
RZ		 404 int32_t ret_val = E1000_SUCCESS;
405 uint16_t eeprom_size;
682011ff 406
95186063
MV		 407 if (hw->mac_type == e1000_igb)
408 eecd = E1000_READ_REG(hw, I210_EECD);
409 else
410 eecd = E1000_READ_REG(hw, EECD);
411
f81ecb5d 412 DEBUGFUNC();
aa070789
RZ		 413
414 switch (hw->mac_type) {
415 case e1000_82542_rev2_0:
416 case e1000_82542_rev2_1:
417 case e1000_82543:
418 case e1000_82544:
419 eeprom->type = e1000_eeprom_microwire;
420 eeprom->word_size = 64;
421 eeprom->opcode_bits = 3;
422 eeprom->address_bits = 6;
423 eeprom->delay_usec = 50;
472d5460
YS		 424 eeprom->use_eerd = false;
425 eeprom->use_eewr = false;
aa070789
RZ		 426 break;
427 case e1000_82540:
428 case e1000_82545:
429 case e1000_82545_rev_3:
430 case e1000_82546:
431 case e1000_82546_rev_3:
432 eeprom->type = e1000_eeprom_microwire;
433 eeprom->opcode_bits = 3;
434 eeprom->delay_usec = 50;
435 if (eecd & E1000_EECD_SIZE) {
436 eeprom->word_size = 256;
437 eeprom->address_bits = 8;
438 } else {
439 eeprom->word_size = 64;
440 eeprom->address_bits = 6;
441 }
472d5460
YS		 442 eeprom->use_eerd = false;
443 eeprom->use_eewr = false;
aa070789
RZ		 444 break;
445 case e1000_82541:
446 case e1000_82541_rev_2:
447 case e1000_82547:
448 case e1000_82547_rev_2:
449 if (eecd & E1000_EECD_TYPE) {
450 eeprom->type = e1000_eeprom_spi;
451 eeprom->opcode_bits = 8;
452 eeprom->delay_usec = 1;
453 if (eecd & E1000_EECD_ADDR_BITS) {
454 eeprom->page_size = 32;
455 eeprom->address_bits = 16;
456 } else {
457 eeprom->page_size = 8;
458 eeprom->address_bits = 8;
459 }
460 } else {
461 eeprom->type = e1000_eeprom_microwire;
462 eeprom->opcode_bits = 3;
463 eeprom->delay_usec = 50;
464 if (eecd & E1000_EECD_ADDR_BITS) {
465 eeprom->word_size = 256;
466 eeprom->address_bits = 8;
467 } else {
468 eeprom->word_size = 64;
469 eeprom->address_bits = 6;
470 }
471 }
472d5460
YS		 472 eeprom->use_eerd = false;
473 eeprom->use_eewr = false;
aa070789
RZ		 474 break;
475 case e1000_82571:
476 case e1000_82572:
477 eeprom->type = e1000_eeprom_spi;
478 eeprom->opcode_bits = 8;
479 eeprom->delay_usec = 1;
480 if (eecd & E1000_EECD_ADDR_BITS) {
481 eeprom->page_size = 32;
482 eeprom->address_bits = 16;
483 } else {
484 eeprom->page_size = 8;
485 eeprom->address_bits = 8;
486 }
472d5460
YS		 487 eeprom->use_eerd = false;
488 eeprom->use_eewr = false;
aa070789
RZ		 489 break;
490 case e1000_82573:
2c2668f9 491 case e1000_82574:
aa070789
RZ		 492 eeprom->type = e1000_eeprom_spi;
493 eeprom->opcode_bits = 8;
494 eeprom->delay_usec = 1;
495 if (eecd & E1000_EECD_ADDR_BITS) {
496 eeprom->page_size = 32;
497 eeprom->address_bits = 16;
498 } else {
499 eeprom->page_size = 8;
500 eeprom->address_bits = 8;
682011ff 501 }
472d5460 502 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
95186063
MV		 503 eeprom->use_eerd = true;
504 eeprom->use_eewr = true;
505
aa070789
RZ		 506 eeprom->type = e1000_eeprom_flash;
507 eeprom->word_size = 2048;
508
509 /* Ensure that the Autonomous FLASH update bit is cleared due to
510 * Flash update issue on parts which use a FLASH for NVM. */
511 eecd &= ~E1000_EECD_AUPDEN;
682011ff 512 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 513 }
aa070789
RZ		 514 break;
515 case e1000_80003es2lan:
516 eeprom->type = e1000_eeprom_spi;
517 eeprom->opcode_bits = 8;
518 eeprom->delay_usec = 1;
519 if (eecd & E1000_EECD_ADDR_BITS) {
520 eeprom->page_size = 32;
521 eeprom->address_bits = 16;
522 } else {
523 eeprom->page_size = 8;
524 eeprom->address_bits = 8;
525 }
472d5460
YS		 526 eeprom->use_eerd = true;
527 eeprom->use_eewr = false;
aa070789 528 break;
95186063
MV		 529 case e1000_igb:
530 /* i210 has 4k of iNVM mapped as EEPROM */
531 eeprom->type = e1000_eeprom_invm;
532 eeprom->opcode_bits = 8;
533 eeprom->delay_usec = 1;
534 eeprom->page_size = 32;
535 eeprom->address_bits = 16;
536 eeprom->use_eerd = true;
537 eeprom->use_eewr = false;
538 break;
682011ff 539
aa070789
RZ		 540 /* ich8lan does not support currently. if needed, please
541 * add corresponding code and functions.
542 */
543#if 0
544 case e1000_ich8lan:
545 {
546 int32_t i = 0;
547
548 eeprom->type = e1000_eeprom_ich8;
472d5460
YS		 549 eeprom->use_eerd = false;
550 eeprom->use_eewr = false;
aa070789
RZ		 551 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
552 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
553 ICH_FLASH_GFPREG);
554 /* Zero the shadow RAM structure. But don't load it from NVM
555 * so as to save time for driver init */
556 if (hw->eeprom_shadow_ram != NULL) {
557 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
472d5460 558 hw->eeprom_shadow_ram[i].modified = false;
aa070789
RZ		 559 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
560 }
561 }
682011ff 562
aa070789
RZ		 563 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
564 ICH_FLASH_SECTOR_SIZE;
682011ff 565
aa070789
RZ		 566 hw->flash_bank_size = ((flash_size >> 16)
567 & ICH_GFPREG_BASE_MASK) + 1;
568 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
682011ff 569
aa070789 570 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
682011ff 571
aa070789
RZ		 572 hw->flash_bank_size /= 2 * sizeof(uint16_t);
573 break;
574 }
575#endif
576 default:
577 break;
682011ff
WD		 578 }
579
95186063
MV		 580 if (eeprom->type == e1000_eeprom_spi ||
581 eeprom->type == e1000_eeprom_invm) {
aa070789
RZ		 582 /* eeprom_size will be an enum [0..8] that maps
583 * to eeprom sizes 128B to
584 * 32KB (incremented by powers of 2).
585 */
586 if (hw->mac_type <= e1000_82547_rev_2) {
587 /* Set to default value for initial eeprom read. */
588 eeprom->word_size = 64;
589 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
590 &eeprom_size);
591 if (ret_val)
592 return ret_val;
593 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
594 >> EEPROM_SIZE_SHIFT;
595 /* 256B eeprom size was not supported in earlier
596 * hardware, so we bump eeprom_size up one to
597 * ensure that "1" (which maps to 256B) is never
598 * the result used in the shifting logic below. */
599 if (eeprom_size)
600 eeprom_size++;
601 } else {
602 eeprom_size = (uint16_t)((eecd &
603 E1000_EECD_SIZE_EX_MASK) >>
604 E1000_EECD_SIZE_EX_SHIFT);
605 }
606
607 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
608 }
609 return ret_val;
682011ff
WD		 610}
611
aa070789
RZ		 612/******************************************************************************
613 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
614 *
615 * hw - Struct containing variables accessed by shared code
616 *****************************************************************************/
617static int32_t
618e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
682011ff 619{
aa070789
RZ		 620 uint32_t attempts = 100000;
621 uint32_t i, reg = 0;
622 int32_t done = E1000_ERR_EEPROM;
682011ff 623
aa070789 624 for (i = 0; i < attempts; i++) {
95186063
MV		 625 if (eerd == E1000_EEPROM_POLL_READ) {
626 if (hw->mac_type == e1000_igb)
627 reg = E1000_READ_REG(hw, I210_EERD);
628 else
629 reg = E1000_READ_REG(hw, EERD);
630 } else {
631 if (hw->mac_type == e1000_igb)
632 reg = E1000_READ_REG(hw, I210_EEWR);
633 else
634 reg = E1000_READ_REG(hw, EEWR);
635 }
aa070789
RZ		 636
637 if (reg & E1000_EEPROM_RW_REG_DONE) {
638 done = E1000_SUCCESS;
639 break;
640 }
641 udelay(5);
642 }
643
644 return done;
682011ff
WD		 645}
646
aa070789
RZ		 647/******************************************************************************
648 * Reads a 16 bit word from the EEPROM using the EERD register.
649 *
650 * hw - Struct containing variables accessed by shared code
651 * offset - offset of word in the EEPROM to read
652 * data - word read from the EEPROM
653 * words - number of words to read
654 *****************************************************************************/
655static int32_t
656e1000_read_eeprom_eerd(struct e1000_hw *hw,
657 uint16_t offset,
658 uint16_t words,
659 uint16_t *data)
682011ff 660{
aa070789
RZ		 661 uint32_t i, eerd = 0;
662 int32_t error = 0;
663
664 for (i = 0; i < words; i++) {
665 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
666 E1000_EEPROM_RW_REG_START;
667
95186063
MV		 668 if (hw->mac_type == e1000_igb)
669 E1000_WRITE_REG(hw, I210_EERD, eerd);
670 else
671 E1000_WRITE_REG(hw, EERD, eerd);
672
aa070789
RZ		 673 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
674
675 if (error)
676 break;
95186063
MV		 677
678 if (hw->mac_type == e1000_igb) {
679 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
680 E1000_EEPROM_RW_REG_DATA);
681 } else {
682 data[i] = (E1000_READ_REG(hw, EERD) >>
aa070789 683 E1000_EEPROM_RW_REG_DATA);
95186063 684 }
682011ff 685
682011ff 686 }
aa070789
RZ		 687
688 return error;
682011ff
WD		 689}
690
2326a94d 691void e1000_release_eeprom(struct e1000_hw *hw)
682011ff
WD		 692{
693 uint32_t eecd;
682011ff 694
aa070789
RZ		 695 DEBUGFUNC();
696
697 eecd = E1000_READ_REG(hw, EECD);
698
699 if (hw->eeprom.type == e1000_eeprom_spi) {
700 eecd |= E1000_EECD_CS; /* Pull CS high */
701 eecd &= ~E1000_EECD_SK; /* Lower SCK */
702
682011ff 703 E1000_WRITE_REG(hw, EECD, eecd);
aa070789
RZ		 704
705 udelay(hw->eeprom.delay_usec);
706 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
707 /* cleanup eeprom */
708
709 /* CS on Microwire is active-high */
710 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
711
712 E1000_WRITE_REG(hw, EECD, eecd);
713
714 /* Rising edge of clock */
715 eecd |= E1000_EECD_SK;
716 E1000_WRITE_REG(hw, EECD, eecd);
717 E1000_WRITE_FLUSH(hw);
718 udelay(hw->eeprom.delay_usec);
719
720 /* Falling edge of clock */
721 eecd &= ~E1000_EECD_SK;
722 E1000_WRITE_REG(hw, EECD, eecd);
723 E1000_WRITE_FLUSH(hw);
724 udelay(hw->eeprom.delay_usec);
682011ff 725 }
682011ff
WD		 726
727 /* Stop requesting EEPROM access */
728 if (hw->mac_type > e1000_82544) {
682011ff
WD		 729 eecd &= ~E1000_EECD_REQ;
730 E1000_WRITE_REG(hw, EECD, eecd);
731 }
682011ff 732}
682011ff 733/******************************************************************************
aa070789 734 * Reads a 16 bit word from the EEPROM.
8bde7f77 735 *
682011ff 736 * hw - Struct containing variables accessed by shared code
682011ff 737 *****************************************************************************/
aa070789
RZ		 738static int32_t
739e1000_spi_eeprom_ready(struct e1000_hw *hw)
682011ff 740{
aa070789
RZ		 741 uint16_t retry_count = 0;
742 uint8_t spi_stat_reg;
682011ff
WD		 743
744 DEBUGFUNC();
745
aa070789
RZ		 746 /* Read "Status Register" repeatedly until the LSB is cleared. The
747 * EEPROM will signal that the command has been completed by clearing
748 * bit 0 of the internal status register. If it's not cleared within
749 * 5 milliseconds, then error out.
750 */
751 retry_count = 0;
752 do {
753 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
754 hw->eeprom.opcode_bits);
755 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
756 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
757 break;
8bde7f77 758
aa070789
RZ		 759 udelay(5);
760 retry_count += 5;
761
762 e1000_standby_eeprom(hw);
763 } while (retry_count < EEPROM_MAX_RETRY_SPI);
764
765 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
766 * only 0-5mSec on 5V devices)
767 */
768 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
769 DEBUGOUT("SPI EEPROM Status error\n");
682011ff
WD		 770 return -E1000_ERR_EEPROM;
771 }
aa070789
RZ		 772
773 return E1000_SUCCESS;
682011ff
WD		 774}
775
776/******************************************************************************
aa070789 777 * Reads a 16 bit word from the EEPROM.
682011ff 778 *
aa070789
RZ		 779 * hw - Struct containing variables accessed by shared code
780 * offset - offset of word in the EEPROM to read
781 * data - word read from the EEPROM
682011ff 782 *****************************************************************************/
aa070789
RZ		 783static int32_t
784e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
785 uint16_t words, uint16_t *data)
682011ff 786{
aa070789
RZ		 787 struct e1000_eeprom_info *eeprom = &hw->eeprom;
788 uint32_t i = 0;
682011ff
WD		 789
790 DEBUGFUNC();
791
aa070789
RZ		 792 /* If eeprom is not yet detected, do so now */
793 if (eeprom->word_size == 0)
794 e1000_init_eeprom_params(hw);
795
796 /* A check for invalid values: offset too large, too many words,
797 * and not enough words.
798 */
799 if ((offset >= eeprom->word_size) ||
800 (words > eeprom->word_size - offset) ||
801 (words == 0)) {
802 DEBUGOUT("\"words\" parameter out of bounds."
803 "Words = %d, size = %d\n", offset, eeprom->word_size);
804 return -E1000_ERR_EEPROM;
805 }
806
807 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
808 * directly. In this case, we need to acquire the EEPROM so that
809 * FW or other port software does not interrupt.
810 */
472d5460
YS		 811 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
812 hw->eeprom.use_eerd == false) {
aa070789
RZ		 813
814 /* Prepare the EEPROM for bit-bang reading */
815 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
816 return -E1000_ERR_EEPROM;
817 }
818
819 /* Eerd register EEPROM access requires no eeprom aquire/release */
472d5460 820 if (eeprom->use_eerd == true)
aa070789
RZ		 821 return e1000_read_eeprom_eerd(hw, offset, words, data);
822
823 /* ich8lan does not support currently. if needed, please
824 * add corresponding code and functions.
825 */
826#if 0
827 /* ICH EEPROM access is done via the ICH flash controller */
828 if (eeprom->type == e1000_eeprom_ich8)
829 return e1000_read_eeprom_ich8(hw, offset, words, data);
830#endif
831 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
832 * acquired the EEPROM at this point, so any returns should relase it */
833 if (eeprom->type == e1000_eeprom_spi) {
834 uint16_t word_in;
835 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
836
837 if (e1000_spi_eeprom_ready(hw)) {
838 e1000_release_eeprom(hw);
839 return -E1000_ERR_EEPROM;
840 }
841
842 e1000_standby_eeprom(hw);
843
844 /* Some SPI eeproms use the 8th address bit embedded in
845 * the opcode */
846 if ((eeprom->address_bits == 8) && (offset >= 128))
847 read_opcode |= EEPROM_A8_OPCODE_SPI;
848
849 /* Send the READ command (opcode + addr) */
850 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
851 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
852 eeprom->address_bits);
853
854 /* Read the data. The address of the eeprom internally
855 * increments with each byte (spi) being read, saving on the
856 * overhead of eeprom setup and tear-down. The address
857 * counter will roll over if reading beyond the size of
858 * the eeprom, thus allowing the entire memory to be read
859 * starting from any offset. */
860 for (i = 0; i < words; i++) {
861 word_in = e1000_shift_in_ee_bits(hw, 16);
862 data[i] = (word_in >> 8) | (word_in << 8);
863 }
864 } else if (eeprom->type == e1000_eeprom_microwire) {
865 for (i = 0; i < words; i++) {
866 /* Send the READ command (opcode + addr) */
867 e1000_shift_out_ee_bits(hw,
868 EEPROM_READ_OPCODE_MICROWIRE,
869 eeprom->opcode_bits);
870 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
871 eeprom->address_bits);
872
873 /* Read the data. For microwire, each word requires
874 * the overhead of eeprom setup and tear-down. */
875 data[i] = e1000_shift_in_ee_bits(hw, 16);
876 e1000_standby_eeprom(hw);
877 }
878 }
879
880 /* End this read operation */
881 e1000_release_eeprom(hw);
882
883 return E1000_SUCCESS;
884}
885
886/******************************************************************************
887 * Verifies that the EEPROM has a valid checksum
888 *
889 * hw - Struct containing variables accessed by shared code
890 *
891 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
892 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
893 * valid.
894 *****************************************************************************/
114d7fc0 895static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
aa070789 896{
114d7fc0 897 uint16_t i, checksum, checksum_reg, *buf;
aa070789
RZ		 898
899 DEBUGFUNC();
900
114d7fc0
KM		 901 /* Allocate a temporary buffer */
902 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
903 if (!buf) {
904 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
905 return -E1000_ERR_EEPROM;
aa070789
RZ		 906 }
907
114d7fc0
KM		 908 /* Read the EEPROM */
909 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
910 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
aa070789
RZ		 911 return -E1000_ERR_EEPROM;
912 }
114d7fc0
KM		 913
914 /* Compute the checksum */
7a341066 915 checksum = 0;
114d7fc0
KM		 916 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
917 checksum += buf[i];
918 checksum = ((uint16_t)EEPROM_SUM) - checksum;
919 checksum_reg = buf[i];
920
921 /* Verify it! */
922 if (checksum == checksum_reg)
923 return 0;
924
925 /* Hrm, verification failed, print an error */
926 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
927 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
928 checksum_reg, checksum);
929
930 return -E1000_ERR_EEPROM;
aa070789 931}
8712adfd 932#endif /* CONFIG_E1000_NO_NVM */
ecbd2078
RZ		 933
934/*****************************************************************************
935 * Set PHY to class A mode
936 * Assumes the following operations will follow to enable the new class mode.
937 * 1. Do a PHY soft reset
938 * 2. Restart auto-negotiation or force link.
939 *
940 * hw - Struct containing variables accessed by shared code
941 ****************************************************************************/
942static int32_t
943e1000_set_phy_mode(struct e1000_hw *hw)
944{
8712adfd 945#ifndef CONFIG_E1000_NO_NVM
ecbd2078
RZ		 946 int32_t ret_val;
947 uint16_t eeprom_data;
948
949 DEBUGFUNC();
950
951 if ((hw->mac_type == e1000_82545_rev_3) &&
952 (hw->media_type == e1000_media_type_copper)) {
953 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
954 1, &eeprom_data);
955 if (ret_val)
956 return ret_val;
957
958 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
959 (eeprom_data & EEPROM_PHY_CLASS_A)) {
960 ret_val = e1000_write_phy_reg(hw,
961 M88E1000_PHY_PAGE_SELECT, 0x000B);
962 if (ret_val)
963 return ret_val;
964 ret_val = e1000_write_phy_reg(hw,
965 M88E1000_PHY_GEN_CONTROL, 0x8104);
966 if (ret_val)
967 return ret_val;
968
472d5460 969 hw->phy_reset_disable = false;
ecbd2078
RZ		 970 }
971 }
8712adfd 972#endif
ecbd2078
RZ		 973 return E1000_SUCCESS;
974}
aa070789 975
8712adfd 976#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 977/***************************************************************************
978 *
979 * Obtaining software semaphore bit (SMBI) before resetting PHY.
980 *
981 * hw: Struct containing variables accessed by shared code
982 *
983 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
984 * E1000_SUCCESS at any other case.
985 *
986 ***************************************************************************/
987static int32_t
988e1000_get_software_semaphore(struct e1000_hw *hw)
989{
990 int32_t timeout = hw->eeprom.word_size + 1;
991 uint32_t swsm;
992
993 DEBUGFUNC();
994
95186063
MV		 995 swsm = E1000_READ_REG(hw, SWSM);
996 swsm &= ~E1000_SWSM_SMBI;
997 E1000_WRITE_REG(hw, SWSM, swsm);
998
aa070789
RZ		 999 if (hw->mac_type != e1000_80003es2lan)
1000 return E1000_SUCCESS;
1001
1002 while (timeout) {
1003 swsm = E1000_READ_REG(hw, SWSM);
1004 /* If SMBI bit cleared, it is now set and we hold
1005 * the semaphore */
1006 if (!(swsm & E1000_SWSM_SMBI))
1007 break;
1008 mdelay(1);
1009 timeout--;
1010 }
1011
1012 if (!timeout) {
1013 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1014 return -E1000_ERR_RESET;
1015 }
1016
1017 return E1000_SUCCESS;
1018}
8712adfd 1019#endif
aa070789
RZ		 1020
1021/***************************************************************************
1022 * This function clears HW semaphore bits.
1023 *
1024 * hw: Struct containing variables accessed by shared code
1025 *
1026 * returns: - None.
1027 *
1028 ***************************************************************************/
1029static void
1030e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1031{
8712adfd 1032#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1033 uint32_t swsm;
1034
1035 DEBUGFUNC();
1036
1037 if (!hw->eeprom_semaphore_present)
1038 return;
1039
1040 swsm = E1000_READ_REG(hw, SWSM);
1041 if (hw->mac_type == e1000_80003es2lan) {
1042 /* Release both semaphores. */
1043 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1044 } else
1045 swsm &= ~(E1000_SWSM_SWESMBI);
1046 E1000_WRITE_REG(hw, SWSM, swsm);
8712adfd 1047#endif
aa070789
RZ		 1048}
1049
1050/***************************************************************************
1051 *
1052 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1053 * adapter or Eeprom access.
1054 *
1055 * hw: Struct containing variables accessed by shared code
1056 *
1057 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1058 * E1000_SUCCESS at any other case.
1059 *
1060 ***************************************************************************/
1061static int32_t
1062e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1063{
8712adfd 1064#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1065 int32_t timeout;
1066 uint32_t swsm;
1067
1068 DEBUGFUNC();
1069
1070 if (!hw->eeprom_semaphore_present)
1071 return E1000_SUCCESS;
1072
1073 if (hw->mac_type == e1000_80003es2lan) {
1074 /* Get the SW semaphore. */
1075 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1076 return -E1000_ERR_EEPROM;
1077 }
1078
1079 /* Get the FW semaphore. */
1080 timeout = hw->eeprom.word_size + 1;
1081 while (timeout) {
1082 swsm = E1000_READ_REG(hw, SWSM);
1083 swsm |= E1000_SWSM_SWESMBI;
1084 E1000_WRITE_REG(hw, SWSM, swsm);
1085 /* if we managed to set the bit we got the semaphore. */
1086 swsm = E1000_READ_REG(hw, SWSM);
1087 if (swsm & E1000_SWSM_SWESMBI)
1088 break;
1089
1090 udelay(50);
1091 timeout--;
1092 }
1093
1094 if (!timeout) {
1095 /* Release semaphores */
1096 e1000_put_hw_eeprom_semaphore(hw);
1097 DEBUGOUT("Driver can't access the Eeprom - "
1098 "SWESMBI bit is set.\n");
1099 return -E1000_ERR_EEPROM;
1100 }
8712adfd 1101#endif
aa070789
RZ		 1102 return E1000_SUCCESS;
1103}
1104
1105static int32_t
1106e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1107{
1108 uint32_t swfw_sync = 0;
1109 uint32_t swmask = mask;
1110 uint32_t fwmask = mask << 16;
1111 int32_t timeout = 200;
1112
1113 DEBUGFUNC();
1114 while (timeout) {
1115 if (e1000_get_hw_eeprom_semaphore(hw))
1116 return -E1000_ERR_SWFW_SYNC;
1117
17da7120
MZ		 1118 if (hw->mac_type == e1000_igb)
1119 swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
1120 else
1121 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
76f8cdb2 1122 if (!(swfw_sync & (fwmask | swmask)))
aa070789
RZ		 1123 break;
1124
1125 /* firmware currently using resource (fwmask) */
1126 /* or other software thread currently using resource (swmask) */
1127 e1000_put_hw_eeprom_semaphore(hw);
1128 mdelay(5);
1129 timeout--;
1130 }
1131
1132 if (!timeout) {
1133 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1134 return -E1000_ERR_SWFW_SYNC;
1135 }
1136
1137 swfw_sync |= swmask;
1138 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1139
1140 e1000_put_hw_eeprom_semaphore(hw);
1141 return E1000_SUCCESS;
1142}
1143
472d5460 1144static bool e1000_is_second_port(struct e1000_hw *hw)
987b43a1
KM		 1145{
1146 switch (hw->mac_type) {
1147 case e1000_80003es2lan:
1148 case e1000_82546:
1149 case e1000_82571:
1150 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
472d5460 1151 return true;
987b43a1
KM		 1152 /* Fallthrough */
1153 default:
472d5460 1154 return false;
987b43a1
KM		 1155 }
1156}
1157
8712adfd 1158#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1159/******************************************************************************
1160 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1161 * second function of dual function devices
1162 *
1163 * nic - Struct containing variables accessed by shared code
1164 *****************************************************************************/
1165static int
1166e1000_read_mac_addr(struct eth_device *nic)
1167{
aa070789
RZ		 1168 struct e1000_hw *hw = nic->priv;
1169 uint16_t offset;
1170 uint16_t eeprom_data;
95186063 1171 uint32_t reg_data = 0;
aa070789
RZ		 1172 int i;
1173
1174 DEBUGFUNC();
1175
1176 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1177 offset = i >> 1;
95186063
MV		 1178 if (hw->mac_type == e1000_igb) {
1179 /* i210 preloads MAC address into RAL/RAH registers */
1180 if (offset == 0)
1181 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1182 else if (offset == 1)
1183 reg_data >>= 16;
1184 else if (offset == 2)
1185 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1186 eeprom_data = reg_data & 0xffff;
1187 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
682011ff
WD		 1188 DEBUGOUT("EEPROM Read Error\n");
1189 return -E1000_ERR_EEPROM;
1190 }
1191 nic->enetaddr[i] = eeprom_data & 0xff;
1192 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1193 }
987b43a1
KM		 1194
1195 /* Invert the last bit if this is the second device */
1196 if (e1000_is_second_port(hw))
1197 nic->enetaddr[5] ^= 1;
1198
ac3315c2 1199#ifdef CONFIG_E1000_FALLBACK_MAC
0adb5b76 1200 if (!is_valid_ethaddr(nic->enetaddr)) {
f2302d44
SR		 1201 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1202
1203 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1204 }
7521af1c 1205#endif
682011ff
WD		 1206 return 0;
1207}
8712adfd 1208#endif
682011ff
WD		 1209
1210/******************************************************************************
1211 * Initializes receive address filters.
1212 *
8bde7f77 1213 * hw - Struct containing variables accessed by shared code
682011ff
WD		 1214 *
1215 * Places the MAC address in receive address register 0 and clears the rest
1216 * of the receive addresss registers. Clears the multicast table. Assumes
1217 * the receiver is in reset when the routine is called.
1218 *****************************************************************************/
1219static void
1220e1000_init_rx_addrs(struct eth_device *nic)
1221{
1222 struct e1000_hw *hw = nic->priv;
1223 uint32_t i;
1224 uint32_t addr_low;
1225 uint32_t addr_high;
1226
1227 DEBUGFUNC();
1228
1229 /* Setup the receive address. */
1230 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1231 addr_low = (nic->enetaddr[0] |
1232 (nic->enetaddr[1] << 8) |
1233 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1234
1235 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1236
1237 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1238 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1239
1240 /* Zero out the other 15 receive addresses. */
1241 DEBUGOUT("Clearing RAR[1-15]\n");
1242 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1243 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1244 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1245 }
1246}
1247
1248/******************************************************************************
1249 * Clears the VLAN filer table
1250 *
1251 * hw - Struct containing variables accessed by shared code
1252 *****************************************************************************/
1253static void
1254e1000_clear_vfta(struct e1000_hw *hw)
1255{
1256 uint32_t offset;
1257
1258 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1259 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1260}
1261
1262/******************************************************************************
1263 * Set the mac type member in the hw struct.
8bde7f77 1264 *
682011ff
WD		 1265 * hw - Struct containing variables accessed by shared code
1266 *****************************************************************************/
aa070789 1267int32_t
682011ff
WD		 1268e1000_set_mac_type(struct e1000_hw *hw)
1269{
1270 DEBUGFUNC();
1271
1272 switch (hw->device_id) {
1273 case E1000_DEV_ID_82542:
1274 switch (hw->revision_id) {
1275 case E1000_82542_2_0_REV_ID:
1276 hw->mac_type = e1000_82542_rev2_0;
1277 break;
1278 case E1000_82542_2_1_REV_ID:
1279 hw->mac_type = e1000_82542_rev2_1;
1280 break;
1281 default:
1282 /* Invalid 82542 revision ID */
1283 return -E1000_ERR_MAC_TYPE;
1284 }
1285 break;
1286 case E1000_DEV_ID_82543GC_FIBER:
1287 case E1000_DEV_ID_82543GC_COPPER:
1288 hw->mac_type = e1000_82543;
1289 break;
1290 case E1000_DEV_ID_82544EI_COPPER:
1291 case E1000_DEV_ID_82544EI_FIBER:
1292 case E1000_DEV_ID_82544GC_COPPER:
1293 case E1000_DEV_ID_82544GC_LOM:
1294 hw->mac_type = e1000_82544;
1295 break;
1296 case E1000_DEV_ID_82540EM:
1297 case E1000_DEV_ID_82540EM_LOM:
aa070789
RZ		 1298 case E1000_DEV_ID_82540EP:
1299 case E1000_DEV_ID_82540EP_LOM:
1300 case E1000_DEV_ID_82540EP_LP:
682011ff
WD		 1301 hw->mac_type = e1000_82540;
1302 break;
1303 case E1000_DEV_ID_82545EM_COPPER:
1304 case E1000_DEV_ID_82545EM_FIBER:
1305 hw->mac_type = e1000_82545;
1306 break;
aa070789
RZ		 1307 case E1000_DEV_ID_82545GM_COPPER:
1308 case E1000_DEV_ID_82545GM_FIBER:
1309 case E1000_DEV_ID_82545GM_SERDES:
1310 hw->mac_type = e1000_82545_rev_3;
1311 break;
682011ff
WD		 1312 case E1000_DEV_ID_82546EB_COPPER:
1313 case E1000_DEV_ID_82546EB_FIBER:
aa070789 1314 case E1000_DEV_ID_82546EB_QUAD_COPPER:
682011ff
WD		 1315 hw->mac_type = e1000_82546;
1316 break;
aa070789
RZ		 1317 case E1000_DEV_ID_82546GB_COPPER:
1318 case E1000_DEV_ID_82546GB_FIBER:
1319 case E1000_DEV_ID_82546GB_SERDES:
1320 case E1000_DEV_ID_82546GB_PCIE:
1321 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1322 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1323 hw->mac_type = e1000_82546_rev_3;
1324 break;
1325 case E1000_DEV_ID_82541EI:
1326 case E1000_DEV_ID_82541EI_MOBILE:
1327 case E1000_DEV_ID_82541ER_LOM:
1328 hw->mac_type = e1000_82541;
1329 break;
ac3315c2 1330 case E1000_DEV_ID_82541ER:
aa070789 1331 case E1000_DEV_ID_82541GI:
aa3b8bf9 1332 case E1000_DEV_ID_82541GI_LF:
aa070789 1333 case E1000_DEV_ID_82541GI_MOBILE:
1aeed8d7
WD		 1334 hw->mac_type = e1000_82541_rev_2;
1335 break;
aa070789
RZ		 1336 case E1000_DEV_ID_82547EI:
1337 case E1000_DEV_ID_82547EI_MOBILE:
1338 hw->mac_type = e1000_82547;
1339 break;
1340 case E1000_DEV_ID_82547GI:
1341 hw->mac_type = e1000_82547_rev_2;
1342 break;
1343 case E1000_DEV_ID_82571EB_COPPER:
1344 case E1000_DEV_ID_82571EB_FIBER:
1345 case E1000_DEV_ID_82571EB_SERDES:
1346 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1347 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1348 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1349 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1350 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1351 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1352 hw->mac_type = e1000_82571;
1353 break;
1354 case E1000_DEV_ID_82572EI_COPPER:
1355 case E1000_DEV_ID_82572EI_FIBER:
1356 case E1000_DEV_ID_82572EI_SERDES:
1357 case E1000_DEV_ID_82572EI:
1358 hw->mac_type = e1000_82572;
1359 break;
1360 case E1000_DEV_ID_82573E:
1361 case E1000_DEV_ID_82573E_IAMT:
1362 case E1000_DEV_ID_82573L:
1363 hw->mac_type = e1000_82573;
1364 break;
2c2668f9
RZ		 1365 case E1000_DEV_ID_82574L:
1366 hw->mac_type = e1000_82574;
1367 break;
aa070789
RZ		 1368 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1369 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1370 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1371 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1372 hw->mac_type = e1000_80003es2lan;
1373 break;
1374 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1375 case E1000_DEV_ID_ICH8_IGP_AMT:
1376 case E1000_DEV_ID_ICH8_IGP_C:
1377 case E1000_DEV_ID_ICH8_IFE:
1378 case E1000_DEV_ID_ICH8_IFE_GT:
1379 case E1000_DEV_ID_ICH8_IFE_G:
1380 case E1000_DEV_ID_ICH8_IGP_M:
1381 hw->mac_type = e1000_ich8lan;
1382 break;
6c499abe
MZ		 1383 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1384 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
95186063 1385 case PCI_DEVICE_ID_INTEL_I210_COPPER:
6c499abe 1386 case PCI_DEVICE_ID_INTEL_I211_COPPER:
95186063
MV		 1387 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1388 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1389 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1390 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1391 hw->mac_type = e1000_igb;
1392 break;
682011ff
WD		 1393 default:
1394 /* Should never have loaded on this device */
1395 return -E1000_ERR_MAC_TYPE;
1396 }
1397 return E1000_SUCCESS;
1398}
1399
1400/******************************************************************************
1401 * Reset the transmit and receive units; mask and clear all interrupts.
1402 *
1403 * hw - Struct containing variables accessed by shared code
1404 *****************************************************************************/
1405void
1406e1000_reset_hw(struct e1000_hw *hw)
1407{
1408 uint32_t ctrl;
1409 uint32_t ctrl_ext;
682011ff 1410 uint32_t manc;
9ea005fb 1411 uint32_t pba = 0;
95186063 1412 uint32_t reg;
682011ff
WD		 1413
1414 DEBUGFUNC();
1415
9ea005fb
RZ		 1416 /* get the correct pba value for both PCI and PCIe*/
1417 if (hw->mac_type < e1000_82571)
1418 pba = E1000_DEFAULT_PCI_PBA;
1419 else
1420 pba = E1000_DEFAULT_PCIE_PBA;
1421
682011ff
WD		 1422 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1423 if (hw->mac_type == e1000_82542_rev2_0) {
1424 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1425 pci_write_config_word(hw->pdev, PCI_COMMAND,
aa070789 1426 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
682011ff
WD		 1427 }
1428
1429 /* Clear interrupt mask to stop board from generating interrupts */
1430 DEBUGOUT("Masking off all interrupts\n");
95186063
MV		 1431 if (hw->mac_type == e1000_igb)
1432 E1000_WRITE_REG(hw, I210_IAM, 0);
682011ff
WD		 1433 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1434
1435 /* Disable the Transmit and Receive units. Then delay to allow
1436 * any pending transactions to complete before we hit the MAC with
1437 * the global reset.
1438 */
1439 E1000_WRITE_REG(hw, RCTL, 0);
1440 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1441 E1000_WRITE_FLUSH(hw);
1442
1443 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
472d5460 1444 hw->tbi_compatibility_on = false;
682011ff
WD		 1445
1446 /* Delay to allow any outstanding PCI transactions to complete before
1447 * resetting the device
1448 */
1449 mdelay(10);
1450
1451 /* Issue a global reset to the MAC. This will reset the chip's
1452 * transmit, receive, DMA, and link units. It will not effect
1453 * the current PCI configuration. The global reset bit is self-
1454 * clearing, and should clear within a microsecond.
1455 */
1456 DEBUGOUT("Issuing a global reset to MAC\n");
1457 ctrl = E1000_READ_REG(hw, CTRL);
1458
aa070789 1459 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
682011ff
WD		 1460
1461 /* Force a reload from the EEPROM if necessary */
95186063
MV		 1462 if (hw->mac_type == e1000_igb) {
1463 mdelay(20);
1464 reg = E1000_READ_REG(hw, STATUS);
1465 if (reg & E1000_STATUS_PF_RST_DONE)
1466 DEBUGOUT("PF OK\n");
1467 reg = E1000_READ_REG(hw, I210_EECD);
1468 if (reg & E1000_EECD_AUTO_RD)
1469 DEBUGOUT("EEC OK\n");
1470 } else if (hw->mac_type < e1000_82540) {
682011ff
WD		 1471 /* Wait for reset to complete */
1472 udelay(10);
1473 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1474 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1475 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1476 E1000_WRITE_FLUSH(hw);
1477 /* Wait for EEPROM reload */
1478 mdelay(2);
1479 } else {
1480 /* Wait for EEPROM reload (it happens automatically) */
1481 mdelay(4);
1482 /* Dissable HW ARPs on ASF enabled adapters */
1483 manc = E1000_READ_REG(hw, MANC);
1484 manc &= ~(E1000_MANC_ARP_EN);
1485 E1000_WRITE_REG(hw, MANC, manc);
1486 }
1487
1488 /* Clear interrupt mask to stop board from generating interrupts */
1489 DEBUGOUT("Masking off all interrupts\n");
95186063
MV		 1490 if (hw->mac_type == e1000_igb)
1491 E1000_WRITE_REG(hw, I210_IAM, 0);
682011ff
WD		 1492 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1493
1494 /* Clear any pending interrupt events. */
56b13b1e 1495 E1000_READ_REG(hw, ICR);
682011ff
WD		 1496
1497 /* If MWI was previously enabled, reenable it. */
1498 if (hw->mac_type == e1000_82542_rev2_0) {
1499 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1500 }
95186063
MV		 1501 if (hw->mac_type != e1000_igb)
1502 E1000_WRITE_REG(hw, PBA, pba);
aa070789
RZ		 1503}
1504
1505/******************************************************************************
1506 *
1507 * Initialize a number of hardware-dependent bits
1508 *
1509 * hw: Struct containing variables accessed by shared code
1510 *
1511 * This function contains hardware limitation workarounds for PCI-E adapters
1512 *
1513 *****************************************************************************/
1514static void
1515e1000_initialize_hardware_bits(struct e1000_hw *hw)
1516{
1517 if ((hw->mac_type >= e1000_82571) &&
1518 (!hw->initialize_hw_bits_disable)) {
1519 /* Settings common to all PCI-express silicon */
1520 uint32_t reg_ctrl, reg_ctrl_ext;
1521 uint32_t reg_tarc0, reg_tarc1;
1522 uint32_t reg_tctl;
1523 uint32_t reg_txdctl, reg_txdctl1;
1524
1525 /* link autonegotiation/sync workarounds */
1526 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1527 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1528
1529 /* Enable not-done TX descriptor counting */
1530 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1531 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1532 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1533
1534 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1535 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1536 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1537
95186063
MV		 1538 /* IGB is cool */
1539 if (hw->mac_type == e1000_igb)
1540 return;
1541
aa070789
RZ		 1542 switch (hw->mac_type) {
1543 case e1000_82571:
1544 case e1000_82572:
1545 /* Clear PHY TX compatible mode bits */
1546 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1547 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1548
1549 /* link autonegotiation/sync workarounds */
1550 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1551
1552 /* TX ring control fixes */
1553 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1554
1555 /* Multiple read bit is reversed polarity */
1556 reg_tctl = E1000_READ_REG(hw, TCTL);
1557 if (reg_tctl & E1000_TCTL_MULR)
1558 reg_tarc1 &= ~(1 << 28);
1559 else
1560 reg_tarc1 |= (1 << 28);
1561
1562 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1563 break;
1564 case e1000_82573:
2c2668f9 1565 case e1000_82574:
aa070789
RZ		 1566 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1567 reg_ctrl_ext &= ~(1 << 23);
1568 reg_ctrl_ext |= (1 << 22);
1569
1570 /* TX byte count fix */
1571 reg_ctrl = E1000_READ_REG(hw, CTRL);
1572 reg_ctrl &= ~(1 << 29);
1573
1574 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1575 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1576 break;
1577 case e1000_80003es2lan:
1578 /* improve small packet performace for fiber/serdes */
1579 if ((hw->media_type == e1000_media_type_fiber)
1580 || (hw->media_type ==
1581 e1000_media_type_internal_serdes)) {
1582 reg_tarc0 &= ~(1 << 20);
1583 }
1584
1585 /* Multiple read bit is reversed polarity */
1586 reg_tctl = E1000_READ_REG(hw, TCTL);
1587 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1588 if (reg_tctl & E1000_TCTL_MULR)
1589 reg_tarc1 &= ~(1 << 28);
1590 else
1591 reg_tarc1 |= (1 << 28);
1592
1593 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1594 break;
1595 case e1000_ich8lan:
1596 /* Reduce concurrent DMA requests to 3 from 4 */
1597 if ((hw->revision_id < 3) ||
1598 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1599 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1600 reg_tarc0 |= ((1 << 29)|(1 << 28));
1601
1602 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1603 reg_ctrl_ext |= (1 << 22);
1604 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1605
1606 /* workaround TX hang with TSO=on */
1607 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1608
1609 /* Multiple read bit is reversed polarity */
1610 reg_tctl = E1000_READ_REG(hw, TCTL);
1611 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1612 if (reg_tctl & E1000_TCTL_MULR)
1613 reg_tarc1 &= ~(1 << 28);
1614 else
1615 reg_tarc1 |= (1 << 28);
1616
1617 /* workaround TX hang with TSO=on */
1618 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1619
1620 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1621 break;
1622 default:
1623 break;
1624 }
1625
1626 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1627 }
682011ff
WD		 1628}
1629
1630/******************************************************************************
1631 * Performs basic configuration of the adapter.
1632 *
1633 * hw - Struct containing variables accessed by shared code
8bde7f77
WD		 1634 *
1635 * Assumes that the controller has previously been reset and is in a
682011ff
WD		 1636 * post-reset uninitialized state. Initializes the receive address registers,
1637 * multicast table, and VLAN filter table. Calls routines to setup link
1638 * configuration and flow control settings. Clears all on-chip counters. Leaves
1639 * the transmit and receive units disabled and uninitialized.
1640 *****************************************************************************/
1641static int
1642e1000_init_hw(struct eth_device *nic)
1643{
1644 struct e1000_hw *hw = nic->priv;
aa070789 1645 uint32_t ctrl;
682011ff
WD		 1646 uint32_t i;
1647 int32_t ret_val;
1648 uint16_t pcix_cmd_word;
1649 uint16_t pcix_stat_hi_word;
1650 uint16_t cmd_mmrbc;
1651 uint16_t stat_mmrbc;
aa070789
RZ		 1652 uint32_t mta_size;
1653 uint32_t reg_data;
1654 uint32_t ctrl_ext;
682011ff 1655 DEBUGFUNC();
aa070789
RZ		 1656 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1657 if ((hw->mac_type == e1000_ich8lan) &&
1658 ((hw->revision_id < 3) ||
1659 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1660 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1661 reg_data = E1000_READ_REG(hw, STATUS);
1662 reg_data &= ~0x80000000;
1663 E1000_WRITE_REG(hw, STATUS, reg_data);
682011ff 1664 }
aa070789 1665 /* Do not need initialize Identification LED */
682011ff 1666
aa070789
RZ		 1667 /* Set the media type and TBI compatibility */
1668 e1000_set_media_type(hw);
1669
1670 /* Must be called after e1000_set_media_type
1671 * because media_type is used */
1672 e1000_initialize_hardware_bits(hw);
682011ff
WD		 1673
1674 /* Disabling VLAN filtering. */
1675 DEBUGOUT("Initializing the IEEE VLAN\n");
aa070789
RZ		 1676 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1677 if (hw->mac_type != e1000_ich8lan) {
1678 if (hw->mac_type < e1000_82545_rev_3)
1679 E1000_WRITE_REG(hw, VET, 0);
1680 e1000_clear_vfta(hw);
1681 }
682011ff
WD		 1682
1683 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1684 if (hw->mac_type == e1000_82542_rev2_0) {
1685 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1686 pci_write_config_word(hw->pdev, PCI_COMMAND,
1687 hw->
1688 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1689 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1690 E1000_WRITE_FLUSH(hw);
1691 mdelay(5);
1692 }
1693
1694 /* Setup the receive address. This involves initializing all of the Receive
1695 * Address Registers (RARs 0 - 15).
1696 */
1697 e1000_init_rx_addrs(nic);
1698
1699 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1700 if (hw->mac_type == e1000_82542_rev2_0) {
1701 E1000_WRITE_REG(hw, RCTL, 0);
1702 E1000_WRITE_FLUSH(hw);
1703 mdelay(1);
1704 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1705 }
1706
1707 /* Zero out the Multicast HASH table */
1708 DEBUGOUT("Zeroing the MTA\n");
aa070789
RZ		 1709 mta_size = E1000_MC_TBL_SIZE;
1710 if (hw->mac_type == e1000_ich8lan)
1711 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1712 for (i = 0; i < mta_size; i++) {
682011ff 1713 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
aa070789
RZ		 1714 /* use write flush to prevent Memory Write Block (MWB) from
1715 * occuring when accessing our register space */
1716 E1000_WRITE_FLUSH(hw);
1717 }
682011ff
WD		 1718#if 0
1719 /* Set the PCI priority bit correctly in the CTRL register. This
1720 * determines if the adapter gives priority to receives, or if it
aa070789
RZ		 1721 * gives equal priority to transmits and receives. Valid only on
1722 * 82542 and 82543 silicon.
682011ff 1723 */
aa070789 1724 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
682011ff
WD		 1725 ctrl = E1000_READ_REG(hw, CTRL);
1726 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1727 }
1728#endif
aa070789
RZ		 1729 switch (hw->mac_type) {
1730 case e1000_82545_rev_3:
1731 case e1000_82546_rev_3:
95186063 1732 case e1000_igb:
aa070789
RZ		 1733 break;
1734 default:
682011ff 1735 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
aa070789 1736 if (hw->bus_type == e1000_bus_type_pcix) {
682011ff
WD		 1737 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1738 &pcix_cmd_word);
1739 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1740 &pcix_stat_hi_word);
1741 cmd_mmrbc =
1742 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1743 PCIX_COMMAND_MMRBC_SHIFT;
1744 stat_mmrbc =
1745 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1746 PCIX_STATUS_HI_MMRBC_SHIFT;
1747 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1748 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1749 if (cmd_mmrbc > stat_mmrbc) {
1750 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1751 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1752 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1753 pcix_cmd_word);
1754 }
1755 }
aa070789
RZ		 1756 break;
1757 }
1758
1759 /* More time needed for PHY to initialize */
1760 if (hw->mac_type == e1000_ich8lan)
1761 mdelay(15);
95186063
MV		 1762 if (hw->mac_type == e1000_igb)
1763 mdelay(15);
682011ff
WD		 1764
1765 /* Call a subroutine to configure the link and setup flow control. */
1766 ret_val = e1000_setup_link(nic);
1767
1768 /* Set the transmit descriptor write-back policy */
1769 if (hw->mac_type > e1000_82544) {
1770 ctrl = E1000_READ_REG(hw, TXDCTL);
1771 ctrl =
1772 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1773 E1000_TXDCTL_FULL_TX_DESC_WB;
1774 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1775 }
aa070789 1776
776e66e8 1777 /* Set the receive descriptor write back policy */
776e66e8
RG		 1778 if (hw->mac_type >= e1000_82571) {
1779 ctrl = E1000_READ_REG(hw, RXDCTL);
1780 ctrl =
1781 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1782 E1000_RXDCTL_FULL_RX_DESC_WB;
1783 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1784 }
1785
aa070789
RZ		 1786 switch (hw->mac_type) {
1787 default:
1788 break;
1789 case e1000_80003es2lan:
1790 /* Enable retransmit on late collisions */
1791 reg_data = E1000_READ_REG(hw, TCTL);
1792 reg_data |= E1000_TCTL_RTLC;
1793 E1000_WRITE_REG(hw, TCTL, reg_data);
1794
1795 /* Configure Gigabit Carry Extend Padding */
1796 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1797 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1798 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1799 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1800
1801 /* Configure Transmit Inter-Packet Gap */
1802 reg_data = E1000_READ_REG(hw, TIPG);
1803 reg_data &= ~E1000_TIPG_IPGT_MASK;
1804 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1805 E1000_WRITE_REG(hw, TIPG, reg_data);
1806
1807 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1808 reg_data &= ~0x00100000;
1809 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1810 /* Fall through */
1811 case e1000_82571:
1812 case e1000_82572:
1813 case e1000_ich8lan:
1814 ctrl = E1000_READ_REG(hw, TXDCTL1);
1815 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1816 | E1000_TXDCTL_FULL_TX_DESC_WB;
1817 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1818 break;
2c2668f9
RZ		 1819 case e1000_82573:
1820 case e1000_82574:
1821 reg_data = E1000_READ_REG(hw, GCR);
1822 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1823 E1000_WRITE_REG(hw, GCR, reg_data);
95186063
MV		 1824 case e1000_igb:
1825 break;
aa070789
RZ		 1826 }
1827
682011ff
WD		 1828#if 0
1829 /* Clear all of the statistics registers (clear on read). It is
1830 * important that we do this after we have tried to establish link
1831 * because the symbol error count will increment wildly if there
1832 * is no link.
1833 */
1834 e1000_clear_hw_cntrs(hw);
aa070789
RZ		 1835
1836 /* ICH8 No-snoop bits are opposite polarity.
1837 * Set to snoop by default after reset. */
1838 if (hw->mac_type == e1000_ich8lan)
1839 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
682011ff
WD		 1840#endif
1841
aa070789
RZ		 1842 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1843 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1844 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1845 /* Relaxed ordering must be disabled to avoid a parity
1846 * error crash in a PCI slot. */
1847 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1848 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1849 }
1850
682011ff
WD		 1851 return ret_val;
1852}
1853
1854/******************************************************************************
1855 * Configures flow control and link settings.
8bde7f77 1856 *
682011ff 1857 * hw - Struct containing variables accessed by shared code
8bde7f77 1858 *
682011ff
WD		 1859 * Determines which flow control settings to use. Calls the apropriate media-
1860 * specific link configuration function. Configures the flow control settings.
1861 * Assuming the adapter has a valid link partner, a valid link should be
8bde7f77 1862 * established. Assumes the hardware has previously been reset and the
682011ff
WD		 1863 * transmitter and receiver are not enabled.
1864 *****************************************************************************/
1865static int
1866e1000_setup_link(struct eth_device *nic)
1867{
1868 struct e1000_hw *hw = nic->priv;
682011ff 1869 int32_t ret_val;
8712adfd
RI		 1870#ifndef CONFIG_E1000_NO_NVM
1871 uint32_t ctrl_ext;
682011ff 1872 uint16_t eeprom_data;
8712adfd 1873#endif
682011ff
WD		 1874
1875 DEBUGFUNC();
1876
aa070789
RZ		 1877 /* In the case of the phy reset being blocked, we already have a link.
1878 * We do not have to set it up again. */
1879 if (e1000_check_phy_reset_block(hw))
1880 return E1000_SUCCESS;
1881
8712adfd 1882#ifndef CONFIG_E1000_NO_NVM
682011ff
WD		 1883 /* Read and store word 0x0F of the EEPROM. This word contains bits
1884 * that determine the hardware's default PAUSE (flow control) mode,
1885 * a bit that determines whether the HW defaults to enabling or
1886 * disabling auto-negotiation, and the direction of the
1887 * SW defined pins. If there is no SW over-ride of the flow
1888 * control setting, then the variable hw->fc will
1889 * be initialized based on a value in the EEPROM.
1890 */
aa070789
RZ		 1891 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1892 &eeprom_data) < 0) {
682011ff
WD		 1893 DEBUGOUT("EEPROM Read Error\n");
1894 return -E1000_ERR_EEPROM;
1895 }
8712adfd 1896#endif
682011ff 1897 if (hw->fc == e1000_fc_default) {
aa070789
RZ		 1898 switch (hw->mac_type) {
1899 case e1000_ich8lan:
1900 case e1000_82573:
2c2668f9 1901 case e1000_82574:
95186063 1902 case e1000_igb:
682011ff 1903 hw->fc = e1000_fc_full;
aa070789
RZ		 1904 break;
1905 default:
8712adfd 1906#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1907 ret_val = e1000_read_eeprom(hw,
1908 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1909 if (ret_val) {
1910 DEBUGOUT("EEPROM Read Error\n");
1911 return -E1000_ERR_EEPROM;
1912 }
aa070789
RZ		 1913 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1914 hw->fc = e1000_fc_none;
1915 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1916 EEPROM_WORD0F_ASM_DIR)
1917 hw->fc = e1000_fc_tx_pause;
1918 else
8712adfd 1919#endif
aa070789
RZ		 1920 hw->fc = e1000_fc_full;
1921 break;
1922 }
682011ff
WD		 1923 }
1924
1925 /* We want to save off the original Flow Control configuration just
1926 * in case we get disconnected and then reconnected into a different
1927 * hub or switch with different Flow Control capabilities.
1928 */
1929 if (hw->mac_type == e1000_82542_rev2_0)
1930 hw->fc &= (~e1000_fc_tx_pause);
1931
1932 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1933 hw->fc &= (~e1000_fc_rx_pause);
1934
1935 hw->original_fc = hw->fc;
1936
1937 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1938
8712adfd 1939#ifndef CONFIG_E1000_NO_NVM
682011ff
WD		 1940 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1941 * polarity value for the SW controlled pins, and setup the
1942 * Extended Device Control reg with that info.
1943 * This is needed because one of the SW controlled pins is used for
1944 * signal detection. So this should be done before e1000_setup_pcs_link()
1945 * or e1000_phy_setup() is called.
1946 */
1947 if (hw->mac_type == e1000_82543) {
1948 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1949 SWDPIO__EXT_SHIFT);
1950 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1951 }
8712adfd 1952#endif
682011ff
WD		 1953
1954 /* Call the necessary subroutine to configure the link. */
1955 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1956 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1957 if (ret_val < 0) {
1958 return ret_val;
1959 }
1960
1961 /* Initialize the flow control address, type, and PAUSE timer
1962 * registers to their default values. This is done even if flow
1963 * control is disabled, because it does not hurt anything to
1964 * initialize these registers.
1965 */
aa070789
RZ		 1966 DEBUGOUT("Initializing the Flow Control address, type"
1967 "and timer regs\n");
1968
1969 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1970 if (hw->mac_type != e1000_ich8lan) {
1971 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1972 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1973 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1974 }
682011ff 1975
682011ff
WD		 1976 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1977
1978 /* Set the flow control receive threshold registers. Normally,
1979 * these registers will be set to a default threshold that may be
1980 * adjusted later by the driver's runtime code. However, if the
1981 * ability to transmit pause frames in not enabled, then these
8bde7f77 1982 * registers will be set to 0.
682011ff
WD		 1983 */
1984 if (!(hw->fc & e1000_fc_tx_pause)) {
1985 E1000_WRITE_REG(hw, FCRTL, 0);
1986 E1000_WRITE_REG(hw, FCRTH, 0);
1987 } else {
1988 /* We need to set up the Receive Threshold high and low water marks
1989 * as well as (optionally) enabling the transmission of XON frames.
1990 */
1991 if (hw->fc_send_xon) {
1992 E1000_WRITE_REG(hw, FCRTL,
1993 (hw->fc_low_water | E1000_FCRTL_XONE));
1994 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1995 } else {
1996 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1997 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1998 }
1999 }
2000 return ret_val;
2001}
2002
2003/******************************************************************************
2004 * Sets up link for a fiber based adapter
2005 *
2006 * hw - Struct containing variables accessed by shared code
2007 *
2008 * Manipulates Physical Coding Sublayer functions in order to configure
2009 * link. Assumes the hardware has been previously reset and the transmitter
2010 * and receiver are not enabled.
2011 *****************************************************************************/
2012static int
2013e1000_setup_fiber_link(struct eth_device *nic)
2014{
2015 struct e1000_hw *hw = nic->priv;
2016 uint32_t ctrl;
2017 uint32_t status;
2018 uint32_t txcw = 0;
2019 uint32_t i;
2020 uint32_t signal;
2021 int32_t ret_val;
2022
2023 DEBUGFUNC();
8bde7f77
WD		 2024 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2025 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 2026 * cleared when there is a signal
2027 */
2028 ctrl = E1000_READ_REG(hw, CTRL);
2029 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2030 signal = E1000_CTRL_SWDPIN1;
2031 else
2032 signal = 0;
2033
2034 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
2035 ctrl);
2036 /* Take the link out of reset */
2037 ctrl &= ~(E1000_CTRL_LRST);
2038
2039 e1000_config_collision_dist(hw);
2040
2041 /* Check for a software override of the flow control settings, and setup
2042 * the device accordingly. If auto-negotiation is enabled, then software
2043 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2044 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
8bde7f77 2045 * auto-negotiation is disabled, then software will have to manually
682011ff
WD		 2046 * configure the two flow control enable bits in the CTRL register.
2047 *
2048 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 2049 * 0: Flow control is completely disabled
2050 * 1: Rx flow control is enabled (we can receive pause frames, but
2051 * not send pause frames).
2052 * 2: Tx flow control is enabled (we can send pause frames but we do
2053 * not support receiving pause frames).
2054 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff
WD		 2055 */
2056 switch (hw->fc) {
2057 case e1000_fc_none:
2058 /* Flow control is completely disabled by a software over-ride. */
2059 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2060 break;
2061 case e1000_fc_rx_pause:
8bde7f77
WD		 2062 /* RX Flow control is enabled and TX Flow control is disabled by a
2063 * software over-ride. Since there really isn't a way to advertise
682011ff
WD		 2064 * that we are capable of RX Pause ONLY, we will advertise that we
2065 * support both symmetric and asymmetric RX PAUSE. Later, we will
2066 * disable the adapter's ability to send PAUSE frames.
2067 */
2068 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2069 break;
2070 case e1000_fc_tx_pause:
8bde7f77 2071 /* TX Flow control is enabled, and RX Flow control is disabled, by a
682011ff
WD		 2072 * software over-ride.
2073 */
2074 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2075 break;
2076 case e1000_fc_full:
2077 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2078 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2079 break;
2080 default:
2081 DEBUGOUT("Flow control param set incorrectly\n");
2082 return -E1000_ERR_CONFIG;
2083 break;
2084 }
2085
2086 /* Since auto-negotiation is enabled, take the link out of reset (the link
2087 * will be in reset, because we previously reset the chip). This will
2088 * restart auto-negotiation. If auto-neogtiation is successful then the
2089 * link-up status bit will be set and the flow control enable bits (RFCE
2090 * and TFCE) will be set according to their negotiated value.
2091 */
2092 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2093
2094 E1000_WRITE_REG(hw, TXCW, txcw);
2095 E1000_WRITE_REG(hw, CTRL, ctrl);
2096 E1000_WRITE_FLUSH(hw);
2097
2098 hw->txcw = txcw;
2099 mdelay(1);
2100
2101 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
8bde7f77
WD		 2102 * indication in the Device Status Register. Time-out if a link isn't
2103 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
682011ff
WD		 2104 * less than 500 milliseconds even if the other end is doing it in SW).
2105 */
2106 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2107 DEBUGOUT("Looking for Link\n");
2108 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2109 mdelay(10);
2110 status = E1000_READ_REG(hw, STATUS);
2111 if (status & E1000_STATUS_LU)
2112 break;
2113 }
2114 if (i == (LINK_UP_TIMEOUT / 10)) {
8bde7f77 2115 /* AutoNeg failed to achieve a link, so we'll call
682011ff
WD		 2116 * e1000_check_for_link. This routine will force the link up if we
2117 * detect a signal. This will allow us to communicate with
2118 * non-autonegotiating link partners.
2119 */
2120 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2121 hw->autoneg_failed = 1;
2122 ret_val = e1000_check_for_link(nic);
2123 if (ret_val < 0) {
2124 DEBUGOUT("Error while checking for link\n");
2125 return ret_val;
2126 }
2127 hw->autoneg_failed = 0;
2128 } else {
2129 hw->autoneg_failed = 0;
2130 DEBUGOUT("Valid Link Found\n");
2131 }
aa070789
RZ		 2132 } else {
2133 DEBUGOUT("No Signal Detected\n");
2134 return -E1000_ERR_NOLINK;
2135 }
2136 return 0;
2137}
2138
aa070789
RZ		 2139/******************************************************************************
2140* Make sure we have a valid PHY and change PHY mode before link setup.
2141*
2142* hw - Struct containing variables accessed by shared code
2143******************************************************************************/
2144static int32_t
2145e1000_copper_link_preconfig(struct e1000_hw *hw)
2146{
2147 uint32_t ctrl;
2148 int32_t ret_val;
2149 uint16_t phy_data;
2150
2151 DEBUGFUNC();
2152
2153 ctrl = E1000_READ_REG(hw, CTRL);
2154 /* With 82543, we need to force speed and duplex on the MAC equal to what
2155 * the PHY speed and duplex configuration is. In addition, we need to
2156 * perform a hardware reset on the PHY to take it out of reset.
2157 */
2158 if (hw->mac_type > e1000_82543) {
2159 ctrl |= E1000_CTRL_SLU;
2160 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2161 E1000_WRITE_REG(hw, CTRL, ctrl);
2162 } else {
2163 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2164 | E1000_CTRL_SLU);
2165 E1000_WRITE_REG(hw, CTRL, ctrl);
2166 ret_val = e1000_phy_hw_reset(hw);
2167 if (ret_val)
2168 return ret_val;
2169 }
2170
2171 /* Make sure we have a valid PHY */
2172 ret_val = e1000_detect_gig_phy(hw);
2173 if (ret_val) {
2174 DEBUGOUT("Error, did not detect valid phy.\n");
2175 return ret_val;
2176 }
2177 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2178
aa070789
RZ		 2179 /* Set PHY to class A mode (if necessary) */
2180 ret_val = e1000_set_phy_mode(hw);
2181 if (ret_val)
2182 return ret_val;
aa070789
RZ		 2183 if ((hw->mac_type == e1000_82545_rev_3) ||
2184 (hw->mac_type == e1000_82546_rev_3)) {
2185 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2186 &phy_data);
2187 phy_data |= 0x00000008;
2188 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2189 phy_data);
2190 }
2191
2192 if (hw->mac_type <= e1000_82543 ||
2193 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2194 hw->mac_type == e1000_82541_rev_2
2195 || hw->mac_type == e1000_82547_rev_2)
472d5460 2196 hw->phy_reset_disable = false;
aa070789
RZ		 2197
2198 return E1000_SUCCESS;
2199}
2200
2201/*****************************************************************************
2202 *
2203 * This function sets the lplu state according to the active flag. When
2204 * activating lplu this function also disables smart speed and vise versa.
2205 * lplu will not be activated unless the device autonegotiation advertisment
2206 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2207 * hw: Struct containing variables accessed by shared code
2208 * active - true to enable lplu false to disable lplu.
2209 *
2210 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2211 * E1000_SUCCESS at any other case.
2212 *
2213 ****************************************************************************/
2214
2215static int32_t
472d5460 2216e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
aa070789
RZ		 2217{
2218 uint32_t phy_ctrl = 0;
2219 int32_t ret_val;
2220 uint16_t phy_data;
2221 DEBUGFUNC();
2222
2223 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2224 && hw->phy_type != e1000_phy_igp_3)
2225 return E1000_SUCCESS;
2226
2227 /* During driver activity LPLU should not be used or it will attain link
2228 * from the lowest speeds starting from 10Mbps. The capability is used
2229 * for Dx transitions and states */
2230 if (hw->mac_type == e1000_82541_rev_2
2231 || hw->mac_type == e1000_82547_rev_2) {
2232 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2233 &phy_data);
2234 if (ret_val)
2235 return ret_val;
2236 } else if (hw->mac_type == e1000_ich8lan) {
2237 /* MAC writes into PHY register based on the state transition
2238 * and start auto-negotiation. SW driver can overwrite the
2239 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2240 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2241 } else {
2242 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2243 &phy_data);
2244 if (ret_val)
2245 return ret_val;
2246 }
2247
2248 if (!active) {
2249 if (hw->mac_type == e1000_82541_rev_2 ||
2250 hw->mac_type == e1000_82547_rev_2) {
2251 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2252 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2253 phy_data);
2254 if (ret_val)
2255 return ret_val;
2256 } else {
2257 if (hw->mac_type == e1000_ich8lan) {
2258 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2259 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2260 } else {
2261 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2262 ret_val = e1000_write_phy_reg(hw,
2263 IGP02E1000_PHY_POWER_MGMT, phy_data);
2264 if (ret_val)
2265 return ret_val;
2266 }
2267 }
2268
2269 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2270 * Dx states where the power conservation is most important. During
2271 * driver activity we should enable SmartSpeed, so performance is
2272 * maintained. */
2273 if (hw->smart_speed == e1000_smart_speed_on) {
2274 ret_val = e1000_read_phy_reg(hw,
2275 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2276 if (ret_val)
2277 return ret_val;
2278
2279 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2280 ret_val = e1000_write_phy_reg(hw,
2281 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2282 if (ret_val)
2283 return ret_val;
2284 } else if (hw->smart_speed == e1000_smart_speed_off) {
2285 ret_val = e1000_read_phy_reg(hw,
2286 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2287 if (ret_val)
2288 return ret_val;
2289
2290 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2291 ret_val = e1000_write_phy_reg(hw,
2292 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2293 if (ret_val)
2294 return ret_val;
2295 }
2296
2297 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2298 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2299 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2300
2301 if (hw->mac_type == e1000_82541_rev_2 ||
2302 hw->mac_type == e1000_82547_rev_2) {
2303 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2304 ret_val = e1000_write_phy_reg(hw,
2305 IGP01E1000_GMII_FIFO, phy_data);
2306 if (ret_val)
2307 return ret_val;
2308 } else {
2309 if (hw->mac_type == e1000_ich8lan) {
2310 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2311 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2312 } else {
2313 phy_data |= IGP02E1000_PM_D3_LPLU;
2314 ret_val = e1000_write_phy_reg(hw,
2315 IGP02E1000_PHY_POWER_MGMT, phy_data);
2316 if (ret_val)
2317 return ret_val;
2318 }
2319 }
2320
2321 /* When LPLU is enabled we should disable SmartSpeed */
2322 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2323 &phy_data);
2324 if (ret_val)
2325 return ret_val;
2326
2327 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2328 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2329 phy_data);
2330 if (ret_val)
2331 return ret_val;
2332 }
2333 return E1000_SUCCESS;
2334}
2335
2336/*****************************************************************************
2337 *
2338 * This function sets the lplu d0 state according to the active flag. When
2339 * activating lplu this function also disables smart speed and vise versa.
2340 * lplu will not be activated unless the device autonegotiation advertisment
2341 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2342 * hw: Struct containing variables accessed by shared code
2343 * active - true to enable lplu false to disable lplu.
2344 *
2345 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2346 * E1000_SUCCESS at any other case.
2347 *
2348 ****************************************************************************/
2349
2350static int32_t
472d5460 2351e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
aa070789
RZ		 2352{
2353 uint32_t phy_ctrl = 0;
2354 int32_t ret_val;
2355 uint16_t phy_data;
2356 DEBUGFUNC();
2357
2358 if (hw->mac_type <= e1000_82547_rev_2)
2359 return E1000_SUCCESS;
2360
2361 if (hw->mac_type == e1000_ich8lan) {
2362 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
95186063
MV		 2363 } else if (hw->mac_type == e1000_igb) {
2364 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
aa070789
RZ		 2365 } else {
2366 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2367 &phy_data);
2368 if (ret_val)
2369 return ret_val;
2370 }
2371
2372 if (!active) {
2373 if (hw->mac_type == e1000_ich8lan) {
2374 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2375 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
95186063
MV		 2376 } else if (hw->mac_type == e1000_igb) {
2377 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2378 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
aa070789
RZ		 2379 } else {
2380 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2381 ret_val = e1000_write_phy_reg(hw,
2382 IGP02E1000_PHY_POWER_MGMT, phy_data);
2383 if (ret_val)
2384 return ret_val;
2385 }
2386
95186063
MV		 2387 if (hw->mac_type == e1000_igb)
2388 return E1000_SUCCESS;
2389
aa070789
RZ		 2390 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2391 * Dx states where the power conservation is most important. During
2392 * driver activity we should enable SmartSpeed, so performance is
2393 * maintained. */
2394 if (hw->smart_speed == e1000_smart_speed_on) {
2395 ret_val = e1000_read_phy_reg(hw,
2396 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2397 if (ret_val)
2398 return ret_val;
2399
2400 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2401 ret_val = e1000_write_phy_reg(hw,
2402 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2403 if (ret_val)
2404 return ret_val;
2405 } else if (hw->smart_speed == e1000_smart_speed_off) {
2406 ret_val = e1000_read_phy_reg(hw,
2407 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2408 if (ret_val)
2409 return ret_val;
2410
2411 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2412 ret_val = e1000_write_phy_reg(hw,
2413 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2414 if (ret_val)
2415 return ret_val;
2416 }
2417
2418
2419 } else {
2420
2421 if (hw->mac_type == e1000_ich8lan) {
2422 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2423 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
95186063
MV		 2424 } else if (hw->mac_type == e1000_igb) {
2425 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2426 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
aa070789
RZ		 2427 } else {
2428 phy_data |= IGP02E1000_PM_D0_LPLU;
2429 ret_val = e1000_write_phy_reg(hw,
2430 IGP02E1000_PHY_POWER_MGMT, phy_data);
2431 if (ret_val)
2432 return ret_val;
2433 }
2434
95186063
MV		 2435 if (hw->mac_type == e1000_igb)
2436 return E1000_SUCCESS;
2437
aa070789
RZ		 2438 /* When LPLU is enabled we should disable SmartSpeed */
2439 ret_val = e1000_read_phy_reg(hw,
2440 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2441 if (ret_val)
2442 return ret_val;
2443
2444 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2445 ret_val = e1000_write_phy_reg(hw,
2446 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2447 if (ret_val)
2448 return ret_val;
2449
2450 }
2451 return E1000_SUCCESS;
2452}
2453
2454/********************************************************************
2455* Copper link setup for e1000_phy_igp series.
2456*
2457* hw - Struct containing variables accessed by shared code
2458*********************************************************************/
2459static int32_t
2460e1000_copper_link_igp_setup(struct e1000_hw *hw)
2461{
2462 uint32_t led_ctrl;
2463 int32_t ret_val;
2464 uint16_t phy_data;
2465
f81ecb5d 2466 DEBUGFUNC();
aa070789
RZ		 2467
2468 if (hw->phy_reset_disable)
2469 return E1000_SUCCESS;
2470
2471 ret_val = e1000_phy_reset(hw);
2472 if (ret_val) {
2473 DEBUGOUT("Error Resetting the PHY\n");
2474 return ret_val;
2475 }
2476
2477 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2478 mdelay(15);
2479 if (hw->mac_type != e1000_ich8lan) {
2480 /* Configure activity LED after PHY reset */
2481 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2482 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2483 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2484 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2485 }
2486
2487 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2488 if (hw->phy_type == e1000_phy_igp) {
2489 /* disable lplu d3 during driver init */
472d5460 2490 ret_val = e1000_set_d3_lplu_state(hw, false);
aa070789
RZ		 2491 if (ret_val) {
2492 DEBUGOUT("Error Disabling LPLU D3\n");
2493 return ret_val;
2494 }
2495 }
2496
2497 /* disable lplu d0 during driver init */
472d5460 2498 ret_val = e1000_set_d0_lplu_state(hw, false);
aa070789
RZ		 2499 if (ret_val) {
2500 DEBUGOUT("Error Disabling LPLU D0\n");
2501 return ret_val;
2502 }
2503 /* Configure mdi-mdix settings */
2504 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2505 if (ret_val)
2506 return ret_val;
2507
2508 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2509 hw->dsp_config_state = e1000_dsp_config_disabled;
2510 /* Force MDI for earlier revs of the IGP PHY */
2511 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2512 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2513 hw->mdix = 1;
2514
2515 } else {
2516 hw->dsp_config_state = e1000_dsp_config_enabled;
2517 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2518
2519 switch (hw->mdix) {
2520 case 1:
2521 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2522 break;
2523 case 2:
2524 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2525 break;
2526 case 0:
2527 default:
2528 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2529 break;
2530 }
2531 }
2532 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2533 if (ret_val)
2534 return ret_val;
2535
2536 /* set auto-master slave resolution settings */
2537 if (hw->autoneg) {
2538 e1000_ms_type phy_ms_setting = hw->master_slave;
2539
2540 if (hw->ffe_config_state == e1000_ffe_config_active)
2541 hw->ffe_config_state = e1000_ffe_config_enabled;
2542
2543 if (hw->dsp_config_state == e1000_dsp_config_activated)
2544 hw->dsp_config_state = e1000_dsp_config_enabled;
2545
2546 /* when autonegotiation advertisment is only 1000Mbps then we
2547 * should disable SmartSpeed and enable Auto MasterSlave
2548 * resolution as hardware default. */
2549 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2550 /* Disable SmartSpeed */
2551 ret_val = e1000_read_phy_reg(hw,
2552 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2553 if (ret_val)
2554 return ret_val;
2555 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2556 ret_val = e1000_write_phy_reg(hw,
2557 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2558 if (ret_val)
2559 return ret_val;
2560 /* Set auto Master/Slave resolution process */
2561 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2562 &phy_data);
2563 if (ret_val)
2564 return ret_val;
2565 phy_data &= ~CR_1000T_MS_ENABLE;
2566 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2567 phy_data);
2568 if (ret_val)
2569 return ret_val;
2570 }
2571
2572 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2573 if (ret_val)
2574 return ret_val;
2575
2576 /* load defaults for future use */
2577 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2578 ((phy_data & CR_1000T_MS_VALUE) ?
2579 e1000_ms_force_master :
2580 e1000_ms_force_slave) :
2581 e1000_ms_auto;
2582
2583 switch (phy_ms_setting) {
2584 case e1000_ms_force_master:
2585 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2586 break;
2587 case e1000_ms_force_slave:
2588 phy_data |= CR_1000T_MS_ENABLE;
2589 phy_data &= ~(CR_1000T_MS_VALUE);
2590 break;
2591 case e1000_ms_auto:
2592 phy_data &= ~CR_1000T_MS_ENABLE;
2593 default:
2594 break;
2595 }
2596 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2597 if (ret_val)
2598 return ret_val;
2599 }
2600
2601 return E1000_SUCCESS;
2602}
2603
2604/*****************************************************************************
2605 * This function checks the mode of the firmware.
2606 *
472d5460 2607 * returns - true when the mode is IAMT or false.
aa070789 2608 ****************************************************************************/
472d5460 2609bool
aa070789
RZ		 2610e1000_check_mng_mode(struct e1000_hw *hw)
2611{
2612 uint32_t fwsm;
2613 DEBUGFUNC();
2614
2615 fwsm = E1000_READ_REG(hw, FWSM);
2616
2617 if (hw->mac_type == e1000_ich8lan) {
2618 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2619 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
472d5460 2620 return true;
aa070789
RZ		 2621 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2622 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
472d5460 2623 return true;
aa070789 2624
472d5460 2625 return false;
aa070789
RZ		 2626}
2627
2628static int32_t
2629e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2630{
987b43a1 2631 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789 2632 uint32_t reg_val;
aa070789
RZ		 2633 DEBUGFUNC();
2634
987b43a1 2635 if (e1000_is_second_port(hw))
aa070789 2636 swfw = E1000_SWFW_PHY1_SM;
987b43a1 2637
aa070789
RZ		 2638 if (e1000_swfw_sync_acquire(hw, swfw))
2639 return -E1000_ERR_SWFW_SYNC;
2640
2641 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2642 & E1000_KUMCTRLSTA_OFFSET) | data;
2643 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2644 udelay(2);
2645
2646 return E1000_SUCCESS;
2647}
2648
2649static int32_t
2650e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2651{
987b43a1 2652 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789 2653 uint32_t reg_val;
aa070789
RZ		 2654 DEBUGFUNC();
2655
987b43a1 2656 if (e1000_is_second_port(hw))
aa070789 2657 swfw = E1000_SWFW_PHY1_SM;
987b43a1 2658
95186063
MV		 2659 if (e1000_swfw_sync_acquire(hw, swfw)) {
2660 debug("%s[%i]\n", __func__, __LINE__);
aa070789 2661 return -E1000_ERR_SWFW_SYNC;
95186063 2662 }
aa070789
RZ		 2663
2664 /* Write register address */
2665 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2666 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2667 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2668 udelay(2);
2669
2670 /* Read the data returned */
2671 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2672 *data = (uint16_t)reg_val;
2673
2674 return E1000_SUCCESS;
2675}
2676
2677/********************************************************************
2678* Copper link setup for e1000_phy_gg82563 series.
2679*
2680* hw - Struct containing variables accessed by shared code
2681*********************************************************************/
2682static int32_t
2683e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2684{
2685 int32_t ret_val;
2686 uint16_t phy_data;
2687 uint32_t reg_data;
2688
2689 DEBUGFUNC();
2690
2691 if (!hw->phy_reset_disable) {
2692 /* Enable CRS on TX for half-duplex operation. */
2693 ret_val = e1000_read_phy_reg(hw,
2694 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2695 if (ret_val)
2696 return ret_val;
2697
2698 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2699 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2700 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2701
2702 ret_val = e1000_write_phy_reg(hw,
2703 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2704 if (ret_val)
2705 return ret_val;
2706
2707 /* Options:
2708 * MDI/MDI-X = 0 (default)
2709 * 0 - Auto for all speeds
2710 * 1 - MDI mode
2711 * 2 - MDI-X mode
2712 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2713 */
2714 ret_val = e1000_read_phy_reg(hw,
2715 GG82563_PHY_SPEC_CTRL, &phy_data);
2716 if (ret_val)
2717 return ret_val;
2718
2719 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2720
2721 switch (hw->mdix) {
2722 case 1:
2723 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2724 break;
2725 case 2:
2726 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2727 break;
2728 case 0:
2729 default:
2730 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2731 break;
2732 }
2733
2734 /* Options:
2735 * disable_polarity_correction = 0 (default)
2736 * Automatic Correction for Reversed Cable Polarity
2737 * 0 - Disabled
2738 * 1 - Enabled
2739 */
2740 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2741 ret_val = e1000_write_phy_reg(hw,
2742 GG82563_PHY_SPEC_CTRL, phy_data);
2743
2744 if (ret_val)
2745 return ret_val;
2746
2747 /* SW Reset the PHY so all changes take effect */
2748 ret_val = e1000_phy_reset(hw);
2749 if (ret_val) {
2750 DEBUGOUT("Error Resetting the PHY\n");
2751 return ret_val;
2752 }
2753 } /* phy_reset_disable */
2754
2755 if (hw->mac_type == e1000_80003es2lan) {
2756 /* Bypass RX and TX FIFO's */
2757 ret_val = e1000_write_kmrn_reg(hw,
2758 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2759 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2760 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2761 if (ret_val)
2762 return ret_val;
2763
2764 ret_val = e1000_read_phy_reg(hw,
2765 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2766 if (ret_val)
2767 return ret_val;
2768
2769 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2770 ret_val = e1000_write_phy_reg(hw,
2771 GG82563_PHY_SPEC_CTRL_2, phy_data);
2772
2773 if (ret_val)
2774 return ret_val;
2775
2776 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2777 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2778 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2779
2780 ret_val = e1000_read_phy_reg(hw,
2781 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2782 if (ret_val)
2783 return ret_val;
2784
2785 /* Do not init these registers when the HW is in IAMT mode, since the
2786 * firmware will have already initialized them. We only initialize
2787 * them if the HW is not in IAMT mode.
2788 */
472d5460 2789 if (e1000_check_mng_mode(hw) == false) {
aa070789
RZ		 2790 /* Enable Electrical Idle on the PHY */
2791 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2792 ret_val = e1000_write_phy_reg(hw,
2793 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2794 if (ret_val)
2795 return ret_val;
2796
2797 ret_val = e1000_read_phy_reg(hw,
2798 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2799 if (ret_val)
2800 return ret_val;
2801
2802 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2803 ret_val = e1000_write_phy_reg(hw,
2804 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2805
2806 if (ret_val)
2807 return ret_val;
2808 }
2809
2810 /* Workaround: Disable padding in Kumeran interface in the MAC
2811 * and in the PHY to avoid CRC errors.
2812 */
2813 ret_val = e1000_read_phy_reg(hw,
2814 GG82563_PHY_INBAND_CTRL, &phy_data);
2815 if (ret_val)
2816 return ret_val;
2817 phy_data |= GG82563_ICR_DIS_PADDING;
2818 ret_val = e1000_write_phy_reg(hw,
2819 GG82563_PHY_INBAND_CTRL, phy_data);
2820 if (ret_val)
2821 return ret_val;
682011ff 2822 }
aa070789 2823 return E1000_SUCCESS;
682011ff
WD		 2824}
2825
aa070789
RZ		 2826/********************************************************************
2827* Copper link setup for e1000_phy_m88 series.
682011ff
WD		 2828*
2829* hw - Struct containing variables accessed by shared code
aa070789
RZ		 2830*********************************************************************/
2831static int32_t
2832e1000_copper_link_mgp_setup(struct e1000_hw *hw)
682011ff 2833{
682011ff 2834 int32_t ret_val;
682011ff
WD		 2835 uint16_t phy_data;
2836
2837 DEBUGFUNC();
2838
aa070789
RZ		 2839 if (hw->phy_reset_disable)
2840 return E1000_SUCCESS;
682011ff 2841
aa070789
RZ		 2842 /* Enable CRS on TX. This must be set for half-duplex operation. */
2843 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2844 if (ret_val)
682011ff 2845 return ret_val;
682011ff 2846
682011ff
WD		 2847 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2848
682011ff
WD		 2849 /* Options:
2850 * MDI/MDI-X = 0 (default)
2851 * 0 - Auto for all speeds
2852 * 1 - MDI mode
2853 * 2 - MDI-X mode
2854 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2855 */
2856 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
aa070789 2857
682011ff
WD		 2858 switch (hw->mdix) {
2859 case 1:
2860 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2861 break;
2862 case 2:
2863 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2864 break;
2865 case 3:
2866 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2867 break;
2868 case 0:
2869 default:
2870 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2871 break;
2872 }
682011ff 2873
682011ff
WD		 2874 /* Options:
2875 * disable_polarity_correction = 0 (default)
aa070789 2876 * Automatic Correction for Reversed Cable Polarity
682011ff
WD		 2877 * 0 - Disabled
2878 * 1 - Enabled
2879 */
2880 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
aa070789
RZ		 2881 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2882 if (ret_val)
2883 return ret_val;
682011ff 2884
aa070789
RZ		 2885 if (hw->phy_revision < M88E1011_I_REV_4) {
2886 /* Force TX_CLK in the Extended PHY Specific Control Register
2887 * to 25MHz clock.
2888 */
2889 ret_val = e1000_read_phy_reg(hw,
2890 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2891 if (ret_val)
2892 return ret_val;
2893
2894 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2895
2896 if ((hw->phy_revision == E1000_REVISION_2) &&
2897 (hw->phy_id == M88E1111_I_PHY_ID)) {
2898 /* Vidalia Phy, set the downshift counter to 5x */
2899 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2900 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2901 ret_val = e1000_write_phy_reg(hw,
2902 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2903 if (ret_val)
2904 return ret_val;
2905 } else {
2906 /* Configure Master and Slave downshift values */
2907 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2908 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2909 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2910 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2911 ret_val = e1000_write_phy_reg(hw,
2912 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2913 if (ret_val)
2914 return ret_val;
2915 }
682011ff
WD		 2916 }
2917
2918 /* SW Reset the PHY so all changes take effect */
2919 ret_val = e1000_phy_reset(hw);
aa070789 2920 if (ret_val) {
682011ff
WD		 2921 DEBUGOUT("Error Resetting the PHY\n");
2922 return ret_val;
2923 }
2924
aa070789
RZ		 2925 return E1000_SUCCESS;
2926}
2927
2928/********************************************************************
2929* Setup auto-negotiation and flow control advertisements,
2930* and then perform auto-negotiation.
2931*
2932* hw - Struct containing variables accessed by shared code
2933*********************************************************************/
2934static int32_t
2935e1000_copper_link_autoneg(struct e1000_hw *hw)
2936{
2937 int32_t ret_val;
2938 uint16_t phy_data;
2939
2940 DEBUGFUNC();
682011ff 2941
682011ff
WD		 2942 /* Perform some bounds checking on the hw->autoneg_advertised
2943 * parameter. If this variable is zero, then set it to the default.
2944 */
2945 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2946
2947 /* If autoneg_advertised is zero, we assume it was not defaulted
2948 * by the calling code so we set to advertise full capability.
2949 */
2950 if (hw->autoneg_advertised == 0)
2951 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2952
aa070789
RZ		 2953 /* IFE phy only supports 10/100 */
2954 if (hw->phy_type == e1000_phy_ife)
2955 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2956
682011ff
WD		 2957 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2958 ret_val = e1000_phy_setup_autoneg(hw);
aa070789 2959 if (ret_val) {
682011ff
WD		 2960 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2961 return ret_val;
2962 }
2963 DEBUGOUT("Restarting Auto-Neg\n");
2964
2965 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2966 * the Auto Neg Restart bit in the PHY control register.
2967 */
aa070789
RZ		 2968 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2969 if (ret_val)
2970 return ret_val;
2971
682011ff 2972 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
aa070789
RZ		 2973 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2974 if (ret_val)
2975 return ret_val;
2976
682011ff
WD		 2977 /* Does the user want to wait for Auto-Neg to complete here, or
2978 * check at a later time (for example, callback routine).
2979 */
aa070789
RZ		 2980 /* If we do not wait for autonegtation to complete I
2981 * do not see a valid link status.
2982 * wait_autoneg_complete = 1 .
2983 */
682011ff
WD		 2984 if (hw->wait_autoneg_complete) {
2985 ret_val = e1000_wait_autoneg(hw);
aa070789
RZ		 2986 if (ret_val) {
2987 DEBUGOUT("Error while waiting for autoneg"
2988 "to complete\n");
682011ff
WD		 2989 return ret_val;
2990 }
2991 }
aa070789 2992
472d5460 2993 hw->get_link_status = true;
aa070789
RZ		 2994
2995 return E1000_SUCCESS;
2996}
2997
2998/******************************************************************************
2999* Config the MAC and the PHY after link is up.
3000* 1) Set up the MAC to the current PHY speed/duplex
3001* if we are on 82543. If we
3002* are on newer silicon, we only need to configure
3003* collision distance in the Transmit Control Register.
3004* 2) Set up flow control on the MAC to that established with
3005* the link partner.
3006* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3007*
3008* hw - Struct containing variables accessed by shared code
3009******************************************************************************/
3010static int32_t
3011e1000_copper_link_postconfig(struct e1000_hw *hw)
3012{
3013 int32_t ret_val;
3014 DEBUGFUNC();
3015
3016 if (hw->mac_type >= e1000_82544) {
3017 e1000_config_collision_dist(hw);
3018 } else {
3019 ret_val = e1000_config_mac_to_phy(hw);
3020 if (ret_val) {
3021 DEBUGOUT("Error configuring MAC to PHY settings\n");
3022 return ret_val;
3023 }
3024 }
3025 ret_val = e1000_config_fc_after_link_up(hw);
3026 if (ret_val) {
3027 DEBUGOUT("Error Configuring Flow Control\n");
682011ff
WD		 3028 return ret_val;
3029 }
aa070789
RZ		 3030 return E1000_SUCCESS;
3031}
3032
3033/******************************************************************************
3034* Detects which PHY is present and setup the speed and duplex
3035*
3036* hw - Struct containing variables accessed by shared code
3037******************************************************************************/
3038static int
3039e1000_setup_copper_link(struct eth_device *nic)
3040{
3041 struct e1000_hw *hw = nic->priv;
3042 int32_t ret_val;
3043 uint16_t i;
3044 uint16_t phy_data;
3045 uint16_t reg_data;
3046
3047 DEBUGFUNC();
3048
3049 switch (hw->mac_type) {
3050 case e1000_80003es2lan:
3051 case e1000_ich8lan:
3052 /* Set the mac to wait the maximum time between each
3053 * iteration and increase the max iterations when
3054 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3055 ret_val = e1000_write_kmrn_reg(hw,
3056 GG82563_REG(0x34, 4), 0xFFFF);
3057 if (ret_val)
3058 return ret_val;
3059 ret_val = e1000_read_kmrn_reg(hw,
3060 GG82563_REG(0x34, 9), &reg_data);
3061 if (ret_val)
3062 return ret_val;
3063 reg_data |= 0x3F;
3064 ret_val = e1000_write_kmrn_reg(hw,
3065 GG82563_REG(0x34, 9), reg_data);
3066 if (ret_val)
3067 return ret_val;
3068 default:
3069 break;
3070 }
3071
3072 /* Check if it is a valid PHY and set PHY mode if necessary. */
3073 ret_val = e1000_copper_link_preconfig(hw);
3074 if (ret_val)
3075 return ret_val;
3076 switch (hw->mac_type) {
3077 case e1000_80003es2lan:
3078 /* Kumeran registers are written-only */
3079 reg_data =
3080 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3081 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3082 ret_val = e1000_write_kmrn_reg(hw,
3083 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3084 if (ret_val)
3085 return ret_val;
3086 break;
3087 default:
3088 break;
3089 }
3090
3091 if (hw->phy_type == e1000_phy_igp ||
3092 hw->phy_type == e1000_phy_igp_3 ||
3093 hw->phy_type == e1000_phy_igp_2) {
3094 ret_val = e1000_copper_link_igp_setup(hw);
3095 if (ret_val)
3096 return ret_val;
95186063
MV		 3097 } else if (hw->phy_type == e1000_phy_m88 ||
3098 hw->phy_type == e1000_phy_igb) {
aa070789
RZ		 3099 ret_val = e1000_copper_link_mgp_setup(hw);
3100 if (ret_val)
3101 return ret_val;
3102 } else if (hw->phy_type == e1000_phy_gg82563) {
3103 ret_val = e1000_copper_link_ggp_setup(hw);
3104 if (ret_val)
3105 return ret_val;
3106 }
3107
3108 /* always auto */
3109 /* Setup autoneg and flow control advertisement
3110 * and perform autonegotiation */
3111 ret_val = e1000_copper_link_autoneg(hw);
3112 if (ret_val)
3113 return ret_val;
682011ff
WD		 3114
3115 /* Check link status. Wait up to 100 microseconds for link to become
3116 * valid.
3117 */
3118 for (i = 0; i < 10; i++) {
aa070789
RZ		 3119 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3120 if (ret_val)
3121 return ret_val;
3122 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3123 if (ret_val)
3124 return ret_val;
3125
682011ff 3126 if (phy_data & MII_SR_LINK_STATUS) {
aa070789
RZ		 3127 /* Config the MAC and PHY after link is up */
3128 ret_val = e1000_copper_link_postconfig(hw);
3129 if (ret_val)
682011ff 3130 return ret_val;
aa070789 3131
682011ff 3132 DEBUGOUT("Valid link established!!!\n");
aa070789 3133 return E1000_SUCCESS;
682011ff
WD		 3134 }
3135 udelay(10);
3136 }
3137
3138 DEBUGOUT("Unable to establish link!!!\n");
aa070789 3139 return E1000_SUCCESS;
682011ff
WD		 3140}
3141
3142/******************************************************************************
3143* Configures PHY autoneg and flow control advertisement settings
3144*
3145* hw - Struct containing variables accessed by shared code
3146******************************************************************************/
aa070789 3147int32_t
682011ff
WD		 3148e1000_phy_setup_autoneg(struct e1000_hw *hw)
3149{
aa070789 3150 int32_t ret_val;
682011ff
WD		 3151 uint16_t mii_autoneg_adv_reg;
3152 uint16_t mii_1000t_ctrl_reg;
3153
3154 DEBUGFUNC();
3155
3156 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
aa070789
RZ		 3157 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3158 if (ret_val)
3159 return ret_val;
682011ff 3160
aa070789
RZ		 3161 if (hw->phy_type != e1000_phy_ife) {
3162 /* Read the MII 1000Base-T Control Register (Address 9). */
3163 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3164 &mii_1000t_ctrl_reg);
3165 if (ret_val)
3166 return ret_val;
3167 } else
3168 mii_1000t_ctrl_reg = 0;
682011ff
WD		 3169
3170 /* Need to parse both autoneg_advertised and fc and set up
3171 * the appropriate PHY registers. First we will parse for
3172 * autoneg_advertised software override. Since we can advertise
3173 * a plethora of combinations, we need to check each bit
3174 * individually.
3175 */
3176
3177 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3178 * Advertisement Register (Address 4) and the 1000 mb speed bits in
aa070789 3179 * the 1000Base-T Control Register (Address 9).
682011ff
WD		 3180 */
3181 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3182 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3183
3184 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3185
3186 /* Do we want to advertise 10 Mb Half Duplex? */
3187 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3188 DEBUGOUT("Advertise 10mb Half duplex\n");
3189 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3190 }
3191
3192 /* Do we want to advertise 10 Mb Full Duplex? */
3193 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3194 DEBUGOUT("Advertise 10mb Full duplex\n");
3195 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3196 }
3197
3198 /* Do we want to advertise 100 Mb Half Duplex? */
3199 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3200 DEBUGOUT("Advertise 100mb Half duplex\n");
3201 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3202 }
3203
3204 /* Do we want to advertise 100 Mb Full Duplex? */
3205 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3206 DEBUGOUT("Advertise 100mb Full duplex\n");
3207 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3208 }
3209
3210 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3211 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3212 DEBUGOUT
3213 ("Advertise 1000mb Half duplex requested, request denied!\n");
3214 }
3215
3216 /* Do we want to advertise 1000 Mb Full Duplex? */
3217 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3218 DEBUGOUT("Advertise 1000mb Full duplex\n");
3219 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3220 }
3221
3222 /* Check for a software override of the flow control settings, and
3223 * setup the PHY advertisement registers accordingly. If
3224 * auto-negotiation is enabled, then software will have to set the
3225 * "PAUSE" bits to the correct value in the Auto-Negotiation
3226 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3227 *
3228 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3229 * 0: Flow control is completely disabled
3230 * 1: Rx flow control is enabled (we can receive pause frames
3231 * but not send pause frames).
3232 * 2: Tx flow control is enabled (we can send pause frames
3233 * but we do not support receiving pause frames).
3234 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff 3235 * other: No software override. The flow control configuration
1aeed8d7 3236 * in the EEPROM is used.
682011ff
WD		 3237 */
3238 switch (hw->fc) {
3239 case e1000_fc_none: /* 0 */
3240 /* Flow control (RX & TX) is completely disabled by a
3241 * software over-ride.
3242 */
3243 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3244 break;
3245 case e1000_fc_rx_pause: /* 1 */
3246 /* RX Flow control is enabled, and TX Flow control is
3247 * disabled, by a software over-ride.
3248 */
3249 /* Since there really isn't a way to advertise that we are
3250 * capable of RX Pause ONLY, we will advertise that we
3251 * support both symmetric and asymmetric RX PAUSE. Later
3252 * (in e1000_config_fc_after_link_up) we will disable the
3253 *hw's ability to send PAUSE frames.
3254 */
3255 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3256 break;
3257 case e1000_fc_tx_pause: /* 2 */
3258 /* TX Flow control is enabled, and RX Flow control is
3259 * disabled, by a software over-ride.
3260 */
3261 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3262 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3263 break;
3264 case e1000_fc_full: /* 3 */
3265 /* Flow control (both RX and TX) is enabled by a software
3266 * over-ride.
3267 */
3268 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3269 break;
3270 default:
3271 DEBUGOUT("Flow control param set incorrectly\n");
3272 return -E1000_ERR_CONFIG;
3273 }
3274
aa070789
RZ		 3275 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3276 if (ret_val)
3277 return ret_val;
682011ff
WD		 3278
3279 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3280
aa070789
RZ		 3281 if (hw->phy_type != e1000_phy_ife) {
3282 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3283 mii_1000t_ctrl_reg);
3284 if (ret_val)
3285 return ret_val;
682011ff 3286 }
aa070789
RZ		 3287
3288 return E1000_SUCCESS;
682011ff
WD		 3289}
3290
3291/******************************************************************************
3292* Sets the collision distance in the Transmit Control register
3293*
3294* hw - Struct containing variables accessed by shared code
3295*
3296* Link should have been established previously. Reads the speed and duplex
3297* information from the Device Status register.
3298******************************************************************************/
3299static void
3300e1000_config_collision_dist(struct e1000_hw *hw)
3301{
aa070789
RZ		 3302 uint32_t tctl, coll_dist;
3303
3304 DEBUGFUNC();
3305
3306 if (hw->mac_type < e1000_82543)
3307 coll_dist = E1000_COLLISION_DISTANCE_82542;
3308 else
3309 coll_dist = E1000_COLLISION_DISTANCE;
682011ff
WD		 3310
3311 tctl = E1000_READ_REG(hw, TCTL);
3312
3313 tctl &= ~E1000_TCTL_COLD;
aa070789 3314 tctl |= coll_dist << E1000_COLD_SHIFT;
682011ff
WD		 3315
3316 E1000_WRITE_REG(hw, TCTL, tctl);
3317 E1000_WRITE_FLUSH(hw);
3318}
3319
3320/******************************************************************************
3321* Sets MAC speed and duplex settings to reflect the those in the PHY
3322*
3323* hw - Struct containing variables accessed by shared code
3324* mii_reg - data to write to the MII control register
3325*
3326* The contents of the PHY register containing the needed information need to
3327* be passed in.
3328******************************************************************************/
3329static int
3330e1000_config_mac_to_phy(struct e1000_hw *hw)
3331{
3332 uint32_t ctrl;
3333 uint16_t phy_data;
3334
3335 DEBUGFUNC();
3336
3337 /* Read the Device Control Register and set the bits to Force Speed
3338 * and Duplex.
3339 */
3340 ctrl = E1000_READ_REG(hw, CTRL);
3341 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
95186063
MV		 3342 ctrl &= ~(E1000_CTRL_ILOS);
3343 ctrl |= (E1000_CTRL_SPD_SEL);
682011ff
WD		 3344
3345 /* Set up duplex in the Device Control and Transmit Control
3346 * registers depending on negotiated values.
3347 */
3348 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3349 DEBUGOUT("PHY Read Error\n");
3350 return -E1000_ERR_PHY;
3351 }
3352 if (phy_data & M88E1000_PSSR_DPLX)
3353 ctrl |= E1000_CTRL_FD;
3354 else
3355 ctrl &= ~E1000_CTRL_FD;
3356
3357 e1000_config_collision_dist(hw);
3358
3359 /* Set up speed in the Device Control register depending on
3360 * negotiated values.
3361 */
3362 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3363 ctrl |= E1000_CTRL_SPD_1000;
3364 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3365 ctrl |= E1000_CTRL_SPD_100;
3366 /* Write the configured values back to the Device Control Reg. */
3367 E1000_WRITE_REG(hw, CTRL, ctrl);
3368 return 0;
3369}
3370
3371/******************************************************************************
3372 * Forces the MAC's flow control settings.
8bde7f77 3373 *
682011ff
WD		 3374 * hw - Struct containing variables accessed by shared code
3375 *
3376 * Sets the TFCE and RFCE bits in the device control register to reflect
3377 * the adapter settings. TFCE and RFCE need to be explicitly set by
3378 * software when a Copper PHY is used because autonegotiation is managed
3379 * by the PHY rather than the MAC. Software must also configure these
3380 * bits when link is forced on a fiber connection.
3381 *****************************************************************************/
3382static int
3383e1000_force_mac_fc(struct e1000_hw *hw)
3384{
3385 uint32_t ctrl;
3386
3387 DEBUGFUNC();
3388
3389 /* Get the current configuration of the Device Control Register */
3390 ctrl = E1000_READ_REG(hw, CTRL);
3391
3392 /* Because we didn't get link via the internal auto-negotiation
3393 * mechanism (we either forced link or we got link via PHY
3394 * auto-neg), we have to manually enable/disable transmit an
3395 * receive flow control.
3396 *
3397 * The "Case" statement below enables/disable flow control
3398 * according to the "hw->fc" parameter.
3399 *
3400 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3401 * 0: Flow control is completely disabled
3402 * 1: Rx flow control is enabled (we can receive pause
3403 * frames but not send pause frames).
3404 * 2: Tx flow control is enabled (we can send pause frames
3405 * frames but we do not receive pause frames).
3406 * 3: Both Rx and TX flow control (symmetric) is enabled.
682011ff
WD		 3407 * other: No other values should be possible at this point.
3408 */
3409
3410 switch (hw->fc) {
3411 case e1000_fc_none:
3412 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3413 break;
3414 case e1000_fc_rx_pause:
3415 ctrl &= (~E1000_CTRL_TFCE);
3416 ctrl |= E1000_CTRL_RFCE;
3417 break;
3418 case e1000_fc_tx_pause:
3419 ctrl &= (~E1000_CTRL_RFCE);
3420 ctrl |= E1000_CTRL_TFCE;
3421 break;
3422 case e1000_fc_full:
3423 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3424 break;
3425 default:
3426 DEBUGOUT("Flow control param set incorrectly\n");
3427 return -E1000_ERR_CONFIG;
3428 }
3429
3430 /* Disable TX Flow Control for 82542 (rev 2.0) */
3431 if (hw->mac_type == e1000_82542_rev2_0)
3432 ctrl &= (~E1000_CTRL_TFCE);
3433
3434 E1000_WRITE_REG(hw, CTRL, ctrl);
3435 return 0;
3436}
3437
3438/******************************************************************************
3439 * Configures flow control settings after link is established
8bde7f77 3440 *
682011ff
WD		 3441 * hw - Struct containing variables accessed by shared code
3442 *
3443 * Should be called immediately after a valid link has been established.
3444 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3445 * and autonegotiation is enabled, the MAC flow control settings will be set
3446 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3447 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3448 *****************************************************************************/
aa070789 3449static int32_t
682011ff
WD		 3450e1000_config_fc_after_link_up(struct e1000_hw *hw)
3451{
3452 int32_t ret_val;
3453 uint16_t mii_status_reg;
3454 uint16_t mii_nway_adv_reg;
3455 uint16_t mii_nway_lp_ability_reg;
3456 uint16_t speed;
3457 uint16_t duplex;
3458
3459 DEBUGFUNC();
3460
3461 /* Check for the case where we have fiber media and auto-neg failed
3462 * so we had to force link. In this case, we need to force the
3463 * configuration of the MAC to match the "fc" parameter.
3464 */
aa070789
RZ		 3465 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3466 || ((hw->media_type == e1000_media_type_internal_serdes)
3467 && (hw->autoneg_failed))
3468 || ((hw->media_type == e1000_media_type_copper)
3469 && (!hw->autoneg))) {
682011ff
WD		 3470 ret_val = e1000_force_mac_fc(hw);
3471 if (ret_val < 0) {
3472 DEBUGOUT("Error forcing flow control settings\n");
3473 return ret_val;
3474 }
3475 }
3476
3477 /* Check for the case where we have copper media and auto-neg is
3478 * enabled. In this case, we need to check and see if Auto-Neg
3479 * has completed, and if so, how the PHY and link partner has
3480 * flow control configured.
3481 */
3482 if (hw->media_type == e1000_media_type_copper) {
3483 /* Read the MII Status Register and check to see if AutoNeg
3484 * has completed. We read this twice because this reg has
3485 * some "sticky" (latched) bits.
3486 */
3487 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3488 DEBUGOUT("PHY Read Error \n");
3489 return -E1000_ERR_PHY;
3490 }
3491 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3492 DEBUGOUT("PHY Read Error \n");
3493 return -E1000_ERR_PHY;
3494 }
3495
3496 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3497 /* The AutoNeg process has completed, so we now need to
3498 * read both the Auto Negotiation Advertisement Register
3499 * (Address 4) and the Auto_Negotiation Base Page Ability
3500 * Register (Address 5) to determine how flow control was
3501 * negotiated.
3502 */
3503 if (e1000_read_phy_reg
3504 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3505 DEBUGOUT("PHY Read Error\n");
3506 return -E1000_ERR_PHY;
3507 }
3508 if (e1000_read_phy_reg
3509 (hw, PHY_LP_ABILITY,
3510 &mii_nway_lp_ability_reg) < 0) {
3511 DEBUGOUT("PHY Read Error\n");
3512 return -E1000_ERR_PHY;
3513 }
3514
3515 /* Two bits in the Auto Negotiation Advertisement Register
3516 * (Address 4) and two bits in the Auto Negotiation Base
3517 * Page Ability Register (Address 5) determine flow control
3518 * for both the PHY and the link partner. The following
3519 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3520 * 1999, describes these PAUSE resolution bits and how flow
3521 * control is determined based upon these settings.
3522 * NOTE: DC = Don't Care
3523 *
3524 * LOCAL DEVICE | LINK PARTNER
3525 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3526 *-------|---------|-------|---------|--------------------
1aeed8d7
WD		 3527 * 0 | 0 | DC | DC | e1000_fc_none
3528 * 0 | 1 | 0 | DC | e1000_fc_none
3529 * 0 | 1 | 1 | 0 | e1000_fc_none
3530 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3531 * 1 | 0 | 0 | DC | e1000_fc_none
3532 * 1 | DC | 1 | DC | e1000_fc_full
3533 * 1 | 1 | 0 | 0 | e1000_fc_none
3534 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3535 *
3536 */
3537 /* Are both PAUSE bits set to 1? If so, this implies
3538 * Symmetric Flow Control is enabled at both ends. The
3539 * ASM_DIR bits are irrelevant per the spec.
3540 *
3541 * For Symmetric Flow Control:
3542 *
3543 * LOCAL DEVICE | LINK PARTNER
3544 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3545 *-------|---------|-------|---------|--------------------
1aeed8d7 3546 * 1 | DC | 1 | DC | e1000_fc_full
682011ff
WD		 3547 *
3548 */
3549 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3550 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3551 /* Now we need to check if the user selected RX ONLY
3552 * of pause frames. In this case, we had to advertise
3553 * FULL flow control because we could not advertise RX
3554 * ONLY. Hence, we must now check to see if we need to
3555 * turn OFF the TRANSMISSION of PAUSE frames.
3556 */
3557 if (hw->original_fc == e1000_fc_full) {
3558 hw->fc = e1000_fc_full;
3559 DEBUGOUT("Flow Control = FULL.\r\n");
3560 } else {
3561 hw->fc = e1000_fc_rx_pause;
3562 DEBUGOUT
3563 ("Flow Control = RX PAUSE frames only.\r\n");
3564 }
3565 }
3566 /* For receiving PAUSE frames ONLY.
3567 *
3568 * LOCAL DEVICE | LINK PARTNER
3569 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3570 *-------|---------|-------|---------|--------------------
1aeed8d7 3571 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
682011ff
WD		 3572 *
3573 */
3574 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3575 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3576 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3577 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3578 {
3579 hw->fc = e1000_fc_tx_pause;
3580 DEBUGOUT
3581 ("Flow Control = TX PAUSE frames only.\r\n");
3582 }
3583 /* For transmitting PAUSE frames ONLY.
3584 *
3585 * LOCAL DEVICE | LINK PARTNER
3586 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3587 *-------|---------|-------|---------|--------------------
1aeed8d7 3588 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3589 *
3590 */
3591 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3592 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3593 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3594 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3595 {
3596 hw->fc = e1000_fc_rx_pause;
3597 DEBUGOUT
3598 ("Flow Control = RX PAUSE frames only.\r\n");
3599 }
3600 /* Per the IEEE spec, at this point flow control should be
3601 * disabled. However, we want to consider that we could
3602 * be connected to a legacy switch that doesn't advertise
3603 * desired flow control, but can be forced on the link
3604 * partner. So if we advertised no flow control, that is
3605 * what we will resolve to. If we advertised some kind of
3606 * receive capability (Rx Pause Only or Full Flow Control)
3607 * and the link partner advertised none, we will configure
3608 * ourselves to enable Rx Flow Control only. We can do
3609 * this safely for two reasons: If the link partner really
3610 * didn't want flow control enabled, and we enable Rx, no
3611 * harm done since we won't be receiving any PAUSE frames
3612 * anyway. If the intent on the link partner was to have
3613 * flow control enabled, then by us enabling RX only, we
3614 * can at least receive pause frames and process them.
3615 * This is a good idea because in most cases, since we are
3616 * predominantly a server NIC, more times than not we will
3617 * be asked to delay transmission of packets than asking
3618 * our link partner to pause transmission of frames.
3619 */
3620 else if (hw->original_fc == e1000_fc_none ||
3621 hw->original_fc == e1000_fc_tx_pause) {
3622 hw->fc = e1000_fc_none;
3623 DEBUGOUT("Flow Control = NONE.\r\n");
3624 } else {
3625 hw->fc = e1000_fc_rx_pause;
3626 DEBUGOUT
3627 ("Flow Control = RX PAUSE frames only.\r\n");
3628 }
3629
1aeed8d7 3630 /* Now we need to do one last check... If we auto-
682011ff
WD		 3631 * negotiated to HALF DUPLEX, flow control should not be
3632 * enabled per IEEE 802.3 spec.
3633 */
3634 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3635
3636 if (duplex == HALF_DUPLEX)
3637 hw->fc = e1000_fc_none;
3638
3639 /* Now we call a subroutine to actually force the MAC
3640 * controller to use the correct flow control settings.
3641 */
3642 ret_val = e1000_force_mac_fc(hw);
3643 if (ret_val < 0) {
3644 DEBUGOUT
3645 ("Error forcing flow control settings\n");
3646 return ret_val;
3647 }
3648 } else {
3649 DEBUGOUT
3650 ("Copper PHY and Auto Neg has not completed.\r\n");
3651 }
3652 }
aa070789 3653 return E1000_SUCCESS;
682011ff
WD		 3654}
3655
3656/******************************************************************************
3657 * Checks to see if the link status of the hardware has changed.
3658 *
3659 * hw - Struct containing variables accessed by shared code
3660 *
3661 * Called by any function that needs to check the link status of the adapter.
3662 *****************************************************************************/
3663static int
3664e1000_check_for_link(struct eth_device *nic)
3665{
3666 struct e1000_hw *hw = nic->priv;
3667 uint32_t rxcw;
3668 uint32_t ctrl;
3669 uint32_t status;
3670 uint32_t rctl;
3671 uint32_t signal;
3672 int32_t ret_val;
3673 uint16_t phy_data;
3674 uint16_t lp_capability;
3675
3676 DEBUGFUNC();
3677
8bde7f77
WD		 3678 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3679 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 3680 * cleared when there is a signal
3681 */
3682 ctrl = E1000_READ_REG(hw, CTRL);
3683 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3684 signal = E1000_CTRL_SWDPIN1;
3685 else
3686 signal = 0;
3687
3688 status = E1000_READ_REG(hw, STATUS);
3689 rxcw = E1000_READ_REG(hw, RXCW);
3690 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3691
3692 /* If we have a copper PHY then we only want to go out to the PHY
3693 * registers to see if Auto-Neg has completed and/or if our link
1aeed8d7 3694 * status has changed. The get_link_status flag will be set if we
682011ff
WD		 3695 * receive a Link Status Change interrupt or we have Rx Sequence
3696 * Errors.
3697 */
3698 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3699 /* First we want to see if the MII Status Register reports
3700 * link. If so, then we want to get the current speed/duplex
3701 * of the PHY.
3702 * Read the register twice since the link bit is sticky.
3703 */
3704 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3705 DEBUGOUT("PHY Read Error\n");
3706 return -E1000_ERR_PHY;
3707 }
3708 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3709 DEBUGOUT("PHY Read Error\n");
3710 return -E1000_ERR_PHY;
3711 }
3712
3713 if (phy_data & MII_SR_LINK_STATUS) {
472d5460 3714 hw->get_link_status = false;
682011ff
WD		 3715 } else {
3716 /* No link detected */
3717 return -E1000_ERR_NOLINK;
3718 }
3719
3720 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3721 * have Si on board that is 82544 or newer, Auto
3722 * Speed Detection takes care of MAC speed/duplex
3723 * configuration. So we only need to configure Collision
3724 * Distance in the MAC. Otherwise, we need to force
3725 * speed/duplex on the MAC to the current PHY speed/duplex
3726 * settings.
3727 */
3728 if (hw->mac_type >= e1000_82544)
3729 e1000_config_collision_dist(hw);
3730 else {
3731 ret_val = e1000_config_mac_to_phy(hw);
3732 if (ret_val < 0) {
3733 DEBUGOUT
3734 ("Error configuring MAC to PHY settings\n");
3735 return ret_val;
3736 }
3737 }
3738
8bde7f77 3739 /* Configure Flow Control now that Auto-Neg has completed. First, we
682011ff
WD		 3740 * need to restore the desired flow control settings because we may
3741 * have had to re-autoneg with a different link partner.
3742 */
3743 ret_val = e1000_config_fc_after_link_up(hw);
3744 if (ret_val < 0) {
3745 DEBUGOUT("Error configuring flow control\n");
3746 return ret_val;
3747 }
3748
3749 /* At this point we know that we are on copper and we have
3750 * auto-negotiated link. These are conditions for checking the link
1aeed8d7 3751 * parter capability register. We use the link partner capability to
682011ff
WD		 3752 * determine if TBI Compatibility needs to be turned on or off. If
3753 * the link partner advertises any speed in addition to Gigabit, then
3754 * we assume that they are GMII-based, and TBI compatibility is not
3755 * needed. If no other speeds are advertised, we assume the link
3756 * partner is TBI-based, and we turn on TBI Compatibility.
3757 */
3758 if (hw->tbi_compatibility_en) {
3759 if (e1000_read_phy_reg
3760 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3761 DEBUGOUT("PHY Read Error\n");
3762 return -E1000_ERR_PHY;
3763 }
3764 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3765 NWAY_LPAR_10T_FD_CAPS |
3766 NWAY_LPAR_100TX_HD_CAPS |
3767 NWAY_LPAR_100TX_FD_CAPS |
3768 NWAY_LPAR_100T4_CAPS)) {
8bde7f77 3769 /* If our link partner advertises anything in addition to
682011ff
WD		 3770 * gigabit, we do not need to enable TBI compatibility.
3771 */
3772 if (hw->tbi_compatibility_on) {
3773 /* If we previously were in the mode, turn it off. */
3774 rctl = E1000_READ_REG(hw, RCTL);
3775 rctl &= ~E1000_RCTL_SBP;
3776 E1000_WRITE_REG(hw, RCTL, rctl);
472d5460 3777 hw->tbi_compatibility_on = false;
682011ff
WD		 3778 }
3779 } else {
3780 /* If TBI compatibility is was previously off, turn it on. For
3781 * compatibility with a TBI link partner, we will store bad
3782 * packets. Some frames have an additional byte on the end and
3783 * will look like CRC errors to to the hardware.
3784 */
3785 if (!hw->tbi_compatibility_on) {
472d5460 3786 hw->tbi_compatibility_on = true;
682011ff
WD		 3787 rctl = E1000_READ_REG(hw, RCTL);
3788 rctl |= E1000_RCTL_SBP;
3789 E1000_WRITE_REG(hw, RCTL, rctl);
3790 }
3791 }
3792 }
3793 }
3794 /* If we don't have link (auto-negotiation failed or link partner cannot
3795 * auto-negotiate), the cable is plugged in (we have signal), and our
3796 * link partner is not trying to auto-negotiate with us (we are receiving
3797 * idles or data), we need to force link up. We also need to give
3798 * auto-negotiation time to complete, in case the cable was just plugged
3799 * in. The autoneg_failed flag does this.
3800 */
3801 else if ((hw->media_type == e1000_media_type_fiber) &&
3802 (!(status & E1000_STATUS_LU)) &&
3803 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3804 (!(rxcw & E1000_RXCW_C))) {
3805 if (hw->autoneg_failed == 0) {
3806 hw->autoneg_failed = 1;
3807 return 0;
3808 }
3809 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3810
3811 /* Disable auto-negotiation in the TXCW register */
3812 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3813
3814 /* Force link-up and also force full-duplex. */
3815 ctrl = E1000_READ_REG(hw, CTRL);
3816 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3817 E1000_WRITE_REG(hw, CTRL, ctrl);
3818
3819 /* Configure Flow Control after forcing link up. */
3820 ret_val = e1000_config_fc_after_link_up(hw);
3821 if (ret_val < 0) {
3822 DEBUGOUT("Error configuring flow control\n");
3823 return ret_val;
3824 }
3825 }
3826 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3827 * auto-negotiation in the TXCW register and disable forced link in the
3828 * Device Control register in an attempt to auto-negotiate with our link
3829 * partner.
3830 */
3831 else if ((hw->media_type == e1000_media_type_fiber) &&
3832 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3833 DEBUGOUT
3834 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3835 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3836 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3837 }
3838 return 0;
3839}
3840
aa070789
RZ		 3841/******************************************************************************
3842* Configure the MAC-to-PHY interface for 10/100Mbps
3843*
3844* hw - Struct containing variables accessed by shared code
3845******************************************************************************/
3846static int32_t
3847e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3848{
3849 int32_t ret_val = E1000_SUCCESS;
3850 uint32_t tipg;
3851 uint16_t reg_data;
3852
3853 DEBUGFUNC();
3854
3855 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3856 ret_val = e1000_write_kmrn_reg(hw,
3857 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3858 if (ret_val)
3859 return ret_val;
3860
3861 /* Configure Transmit Inter-Packet Gap */
3862 tipg = E1000_READ_REG(hw, TIPG);
3863 tipg &= ~E1000_TIPG_IPGT_MASK;
3864 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3865 E1000_WRITE_REG(hw, TIPG, tipg);
3866
3867 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3868
3869 if (ret_val)
3870 return ret_val;
3871
3872 if (duplex == HALF_DUPLEX)
3873 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3874 else
3875 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3876
3877 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3878
3879 return ret_val;
3880}
3881
3882static int32_t
3883e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3884{
3885 int32_t ret_val = E1000_SUCCESS;
3886 uint16_t reg_data;
3887 uint32_t tipg;
3888
3889 DEBUGFUNC();
3890
3891 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3892 ret_val = e1000_write_kmrn_reg(hw,
3893 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3894 if (ret_val)
3895 return ret_val;
3896
3897 /* Configure Transmit Inter-Packet Gap */
3898 tipg = E1000_READ_REG(hw, TIPG);
3899 tipg &= ~E1000_TIPG_IPGT_MASK;
3900 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3901 E1000_WRITE_REG(hw, TIPG, tipg);
3902
3903 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3904
3905 if (ret_val)
3906 return ret_val;
3907
3908 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3909 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3910
3911 return ret_val;
3912}
3913
682011ff
WD		 3914/******************************************************************************
3915 * Detects the current speed and duplex settings of the hardware.
3916 *
3917 * hw - Struct containing variables accessed by shared code
3918 * speed - Speed of the connection
3919 * duplex - Duplex setting of the connection
3920 *****************************************************************************/
aa070789
RZ		 3921static int
3922e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3923 uint16_t *duplex)
682011ff
WD		 3924{
3925 uint32_t status;
aa070789
RZ		 3926 int32_t ret_val;
3927 uint16_t phy_data;
682011ff
WD		 3928
3929 DEBUGFUNC();
3930
3931 if (hw->mac_type >= e1000_82543) {
3932 status = E1000_READ_REG(hw, STATUS);
3933 if (status & E1000_STATUS_SPEED_1000) {
3934 *speed = SPEED_1000;
3935 DEBUGOUT("1000 Mbs, ");
3936 } else if (status & E1000_STATUS_SPEED_100) {
3937 *speed = SPEED_100;
3938 DEBUGOUT("100 Mbs, ");
3939 } else {
3940 *speed = SPEED_10;
3941 DEBUGOUT("10 Mbs, ");
3942 }
3943
3944 if (status & E1000_STATUS_FD) {
3945 *duplex = FULL_DUPLEX;
3946 DEBUGOUT("Full Duplex\r\n");
3947 } else {
3948 *duplex = HALF_DUPLEX;
3949 DEBUGOUT(" Half Duplex\r\n");
3950 }
3951 } else {
3952 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3953 *speed = SPEED_1000;
3954 *duplex = FULL_DUPLEX;
3955 }
aa070789
RZ		 3956
3957 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3958 * even if it is operating at half duplex. Here we set the duplex
3959 * settings to match the duplex in the link partner's capabilities.
3960 */
3961 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3962 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3963 if (ret_val)
3964 return ret_val;
3965
3966 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3967 *duplex = HALF_DUPLEX;
3968 else {
3969 ret_val = e1000_read_phy_reg(hw,
3970 PHY_LP_ABILITY, &phy_data);
3971 if (ret_val)
3972 return ret_val;
3973 if ((*speed == SPEED_100 &&
3974 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3975 || (*speed == SPEED_10
3976 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3977 *duplex = HALF_DUPLEX;
3978 }
3979 }
3980
3981 if ((hw->mac_type == e1000_80003es2lan) &&
3982 (hw->media_type == e1000_media_type_copper)) {
3983 if (*speed == SPEED_1000)
3984 ret_val = e1000_configure_kmrn_for_1000(hw);
3985 else
3986 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3987 if (ret_val)
3988 return ret_val;
3989 }
3990 return E1000_SUCCESS;
682011ff
WD		 3991}
3992
3993/******************************************************************************
3994* Blocks until autoneg completes or times out (~4.5 seconds)
3995*
3996* hw - Struct containing variables accessed by shared code
3997******************************************************************************/
3998static int
3999e1000_wait_autoneg(struct e1000_hw *hw)
4000{
4001 uint16_t i;
4002 uint16_t phy_data;
4003
4004 DEBUGFUNC();
4005 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4006
4007 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4008 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4009 /* Read the MII Status Register and wait for Auto-Neg
4010 * Complete bit to be set.
4011 */
4012 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4013 DEBUGOUT("PHY Read Error\n");
4014 return -E1000_ERR_PHY;
4015 }
4016 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4017 DEBUGOUT("PHY Read Error\n");
4018 return -E1000_ERR_PHY;
4019 }
4020 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4021 DEBUGOUT("Auto-Neg complete.\n");
4022 return 0;
4023 }
4024 mdelay(100);
4025 }
4026 DEBUGOUT("Auto-Neg timedout.\n");
4027 return -E1000_ERR_TIMEOUT;
4028}
4029
4030/******************************************************************************
4031* Raises the Management Data Clock
4032*
4033* hw - Struct containing variables accessed by shared code
4034* ctrl - Device control register's current value
4035******************************************************************************/
4036static void
4037e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4038{
4039 /* Raise the clock input to the Management Data Clock (by setting the MDC
4040 * bit), and then delay 2 microseconds.
4041 */
4042 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4043 E1000_WRITE_FLUSH(hw);
4044 udelay(2);
4045}
4046
4047/******************************************************************************
4048* Lowers the Management Data Clock
4049*
4050* hw - Struct containing variables accessed by shared code
4051* ctrl - Device control register's current value
4052******************************************************************************/
4053static void
4054e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4055{
4056 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4057 * bit), and then delay 2 microseconds.
4058 */
4059 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4060 E1000_WRITE_FLUSH(hw);
4061 udelay(2);
4062}
4063
4064/******************************************************************************
4065* Shifts data bits out to the PHY
4066*
4067* hw - Struct containing variables accessed by shared code
4068* data - Data to send out to the PHY
4069* count - Number of bits to shift out
4070*
4071* Bits are shifted out in MSB to LSB order.
4072******************************************************************************/
4073static void
4074e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4075{
4076 uint32_t ctrl;
4077 uint32_t mask;
4078
4079 /* We need to shift "count" number of bits out to the PHY. So, the value
8bde7f77 4080 * in the "data" parameter will be shifted out to the PHY one bit at a
682011ff
WD		 4081 * time. In order to do this, "data" must be broken down into bits.
4082 */
4083 mask = 0x01;
4084 mask <<= (count - 1);
4085
4086 ctrl = E1000_READ_REG(hw, CTRL);
4087
4088 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4089 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4090
4091 while (mask) {
4092 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4093 * then raising and lowering the Management Data Clock. A "0" is
4094 * shifted out to the PHY by setting the MDIO bit to "0" and then
4095 * raising and lowering the clock.
4096 */
4097 if (data & mask)
4098 ctrl |= E1000_CTRL_MDIO;
4099 else
4100 ctrl &= ~E1000_CTRL_MDIO;
4101
4102 E1000_WRITE_REG(hw, CTRL, ctrl);
4103 E1000_WRITE_FLUSH(hw);
4104
4105 udelay(2);
4106
4107 e1000_raise_mdi_clk(hw, &ctrl);
4108 e1000_lower_mdi_clk(hw, &ctrl);
4109
4110 mask = mask >> 1;
4111 }
4112}
4113
4114/******************************************************************************
4115* Shifts data bits in from the PHY
4116*
4117* hw - Struct containing variables accessed by shared code
4118*
8bde7f77 4119* Bits are shifted in in MSB to LSB order.
682011ff
WD		 4120******************************************************************************/
4121static uint16_t
4122e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4123{
4124 uint32_t ctrl;
4125 uint16_t data = 0;
4126 uint8_t i;
4127
4128 /* In order to read a register from the PHY, we need to shift in a total
4129 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4130 * to avoid contention on the MDIO pin when a read operation is performed.
4131 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4132 * by raising the input to the Management Data Clock (setting the MDC bit),
4133 * and then reading the value of the MDIO bit.
4134 */
4135 ctrl = E1000_READ_REG(hw, CTRL);
4136
4137 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4138 ctrl &= ~E1000_CTRL_MDIO_DIR;
4139 ctrl &= ~E1000_CTRL_MDIO;
4140
4141 E1000_WRITE_REG(hw, CTRL, ctrl);
4142 E1000_WRITE_FLUSH(hw);
4143
4144 /* Raise and Lower the clock before reading in the data. This accounts for
4145 * the turnaround bits. The first clock occurred when we clocked out the
4146 * last bit of the Register Address.
4147 */
4148 e1000_raise_mdi_clk(hw, &ctrl);
4149 e1000_lower_mdi_clk(hw, &ctrl);
4150
4151 for (data = 0, i = 0; i < 16; i++) {
4152 data = data << 1;
4153 e1000_raise_mdi_clk(hw, &ctrl);
4154 ctrl = E1000_READ_REG(hw, CTRL);
4155 /* Check to see if we shifted in a "1". */
4156 if (ctrl & E1000_CTRL_MDIO)
4157 data |= 1;
4158 e1000_lower_mdi_clk(hw, &ctrl);
4159 }
4160
4161 e1000_raise_mdi_clk(hw, &ctrl);
4162 e1000_lower_mdi_clk(hw, &ctrl);
4163
4164 return data;
4165}
4166
4167/*****************************************************************************
4168* Reads the value from a PHY register
4169*
4170* hw - Struct containing variables accessed by shared code
4171* reg_addr - address of the PHY register to read
4172******************************************************************************/
4173static int
4174e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4175{
4176 uint32_t i;
4177 uint32_t mdic = 0;
4178 const uint32_t phy_addr = 1;
4179
4180 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4181 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4182 return -E1000_ERR_PARAM;
4183 }
4184
4185 if (hw->mac_type > e1000_82543) {
4186 /* Set up Op-code, Phy Address, and register address in the MDI
4187 * Control register. The MAC will take care of interfacing with the
4188 * PHY to retrieve the desired data.
4189 */
4190 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4191 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4192 (E1000_MDIC_OP_READ));
4193
4194 E1000_WRITE_REG(hw, MDIC, mdic);
4195
4196 /* Poll the ready bit to see if the MDI read completed */
4197 for (i = 0; i < 64; i++) {
4198 udelay(10);
4199 mdic = E1000_READ_REG(hw, MDIC);
4200 if (mdic & E1000_MDIC_READY)
4201 break;
4202 }
4203 if (!(mdic & E1000_MDIC_READY)) {
4204 DEBUGOUT("MDI Read did not complete\n");
4205 return -E1000_ERR_PHY;
4206 }
4207 if (mdic & E1000_MDIC_ERROR) {
4208 DEBUGOUT("MDI Error\n");
4209 return -E1000_ERR_PHY;
4210 }
4211 *phy_data = (uint16_t) mdic;
4212 } else {
4213 /* We must first send a preamble through the MDIO pin to signal the
4214 * beginning of an MII instruction. This is done by sending 32
4215 * consecutive "1" bits.
4216 */
4217 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4218
4219 /* Now combine the next few fields that are required for a read
4220 * operation. We use this method instead of calling the
4221 * e1000_shift_out_mdi_bits routine five different times. The format of
4222 * a MII read instruction consists of a shift out of 14 bits and is
4223 * defined as follows:
4224 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4225 * followed by a shift in of 18 bits. This first two bits shifted in
4226 * are TurnAround bits used to avoid contention on the MDIO pin when a
4227 * READ operation is performed. These two bits are thrown away
4228 * followed by a shift in of 16 bits which contains the desired data.
4229 */
4230 mdic = ((reg_addr) | (phy_addr << 5) |
4231 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4232
4233 e1000_shift_out_mdi_bits(hw, mdic, 14);
4234
4235 /* Now that we've shifted out the read command to the MII, we need to
4236 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4237 * register address.
4238 */
4239 *phy_data = e1000_shift_in_mdi_bits(hw);
4240 }
4241 return 0;
4242}
4243
4244/******************************************************************************
4245* Writes a value to a PHY register
4246*
4247* hw - Struct containing variables accessed by shared code
4248* reg_addr - address of the PHY register to write
4249* data - data to write to the PHY
4250******************************************************************************/
4251static int
4252e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4253{
4254 uint32_t i;
4255 uint32_t mdic = 0;
4256 const uint32_t phy_addr = 1;
4257
4258 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4259 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4260 return -E1000_ERR_PARAM;
4261 }
4262
4263 if (hw->mac_type > e1000_82543) {
4264 /* Set up Op-code, Phy Address, register address, and data intended
4265 * for the PHY register in the MDI Control register. The MAC will take
4266 * care of interfacing with the PHY to send the desired data.
4267 */
4268 mdic = (((uint32_t) phy_data) |
4269 (reg_addr << E1000_MDIC_REG_SHIFT) |
4270 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4271 (E1000_MDIC_OP_WRITE));
4272
4273 E1000_WRITE_REG(hw, MDIC, mdic);
4274
4275 /* Poll the ready bit to see if the MDI read completed */
4276 for (i = 0; i < 64; i++) {
4277 udelay(10);
4278 mdic = E1000_READ_REG(hw, MDIC);
4279 if (mdic & E1000_MDIC_READY)
4280 break;
4281 }
4282 if (!(mdic & E1000_MDIC_READY)) {
4283 DEBUGOUT("MDI Write did not complete\n");
4284 return -E1000_ERR_PHY;
4285 }
4286 } else {
4287 /* We'll need to use the SW defined pins to shift the write command
4288 * out to the PHY. We first send a preamble to the PHY to signal the
8bde7f77 4289 * beginning of the MII instruction. This is done by sending 32
682011ff
WD		 4290 * consecutive "1" bits.
4291 */
4292 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4293
8bde7f77 4294 /* Now combine the remaining required fields that will indicate a
682011ff
WD		 4295 * write operation. We use this method instead of calling the
4296 * e1000_shift_out_mdi_bits routine for each field in the command. The
4297 * format of a MII write instruction is as follows:
4298 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4299 */
4300 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4301 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4302 mdic <<= 16;
4303 mdic |= (uint32_t) phy_data;
4304
4305 e1000_shift_out_mdi_bits(hw, mdic, 32);
4306 }
4307 return 0;
4308}
4309
aa070789
RZ		 4310/******************************************************************************
4311 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4312 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4313 * the caller to figure out how to deal with it.
4314 *
4315 * hw - Struct containing variables accessed by shared code
4316 *
4317 * returns: - E1000_BLK_PHY_RESET
4318 * E1000_SUCCESS
4319 *
4320 *****************************************************************************/
4321int32_t
4322e1000_check_phy_reset_block(struct e1000_hw *hw)
4323{
4324 uint32_t manc = 0;
4325 uint32_t fwsm = 0;
4326
4327 if (hw->mac_type == e1000_ich8lan) {
4328 fwsm = E1000_READ_REG(hw, FWSM);
4329 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4330 : E1000_BLK_PHY_RESET;
4331 }
4332
4333 if (hw->mac_type > e1000_82547_rev_2)
4334 manc = E1000_READ_REG(hw, MANC);
4335 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4336 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4337}
4338
4339/***************************************************************************
4340 * Checks if the PHY configuration is done
4341 *
4342 * hw: Struct containing variables accessed by shared code
4343 *
4344 * returns: - E1000_ERR_RESET if fail to reset MAC
4345 * E1000_SUCCESS at any other case.
4346 *
4347 ***************************************************************************/
4348static int32_t
4349e1000_get_phy_cfg_done(struct e1000_hw *hw)
4350{
4351 int32_t timeout = PHY_CFG_TIMEOUT;
4352 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4353
4354 DEBUGFUNC();
4355
4356 switch (hw->mac_type) {
4357 default:
4358 mdelay(10);
4359 break;
987b43a1 4360
aa070789
RZ		 4361 case e1000_80003es2lan:
4362 /* Separate *_CFG_DONE_* bit for each port */
987b43a1 4363 if (e1000_is_second_port(hw))
aa070789 4364 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
987b43a1
KM		 4365 /* Fall Through */
4366
aa070789
RZ		 4367 case e1000_82571:
4368 case e1000_82572:
95186063 4369 case e1000_igb:
aa070789 4370 while (timeout) {
95186063
MV		 4371 if (hw->mac_type == e1000_igb) {
4372 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4373 break;
4374 } else {
4375 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4376 break;
4377 }
4378 mdelay(1);
aa070789
RZ		 4379 timeout--;
4380 }
4381 if (!timeout) {
4382 DEBUGOUT("MNG configuration cycle has not "
4383 "completed.\n");
4384 return -E1000_ERR_RESET;
4385 }
4386 break;
4387 }
4388
4389 return E1000_SUCCESS;
4390}
4391
682011ff
WD		 4392/******************************************************************************
4393* Returns the PHY to the power-on reset state
4394*
4395* hw - Struct containing variables accessed by shared code
4396******************************************************************************/
aa070789 4397int32_t
682011ff
WD		 4398e1000_phy_hw_reset(struct e1000_hw *hw)
4399{
987b43a1 4400 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789
RZ		 4401 uint32_t ctrl, ctrl_ext;
4402 uint32_t led_ctrl;
4403 int32_t ret_val;
682011ff
WD		 4404
4405 DEBUGFUNC();
4406
aa070789
RZ		 4407 /* In the case of the phy reset being blocked, it's not an error, we
4408 * simply return success without performing the reset. */
4409 ret_val = e1000_check_phy_reset_block(hw);
4410 if (ret_val)
4411 return E1000_SUCCESS;
4412
682011ff
WD		 4413 DEBUGOUT("Resetting Phy...\n");
4414
4415 if (hw->mac_type > e1000_82543) {
987b43a1 4416 if (e1000_is_second_port(hw))
aa070789 4417 swfw = E1000_SWFW_PHY1_SM;
987b43a1 4418
aa070789
RZ		 4419 if (e1000_swfw_sync_acquire(hw, swfw)) {
4420 DEBUGOUT("Unable to acquire swfw sync\n");
4421 return -E1000_ERR_SWFW_SYNC;
4422 }
987b43a1 4423
682011ff
WD		 4424 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4425 * bit. Then, take it out of reset.
4426 */
4427 ctrl = E1000_READ_REG(hw, CTRL);
4428 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4429 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4430
4431 if (hw->mac_type < e1000_82571)
4432 udelay(10);
4433 else
4434 udelay(100);
4435
682011ff
WD		 4436 E1000_WRITE_REG(hw, CTRL, ctrl);
4437 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4438
4439 if (hw->mac_type >= e1000_82571)
4440 mdelay(10);
682011ff
WD		 4441 } else {
4442 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4443 * bit to put the PHY into reset. Then, take it out of reset.
4444 */
4445 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4446 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4447 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4448 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4449 E1000_WRITE_FLUSH(hw);
4450 mdelay(10);
4451 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4452 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4453 E1000_WRITE_FLUSH(hw);
4454 }
4455 udelay(150);
aa070789
RZ		 4456
4457 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4458 /* Configure activity LED after PHY reset */
4459 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4460 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4461 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4462 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4463 }
4464
4465 /* Wait for FW to finish PHY configuration. */
4466 ret_val = e1000_get_phy_cfg_done(hw);
4467 if (ret_val != E1000_SUCCESS)
4468 return ret_val;
4469
4470 return ret_val;
4471}
4472
4473/******************************************************************************
4474 * IGP phy init script - initializes the GbE PHY
4475 *
4476 * hw - Struct containing variables accessed by shared code
4477 *****************************************************************************/
4478static void
4479e1000_phy_init_script(struct e1000_hw *hw)
4480{
4481 uint32_t ret_val;
4482 uint16_t phy_saved_data;
4483 DEBUGFUNC();
4484
4485 if (hw->phy_init_script) {
4486 mdelay(20);
4487
4488 /* Save off the current value of register 0x2F5B to be
4489 * restored at the end of this routine. */
4490 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4491
4492 /* Disabled the PHY transmitter */
4493 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4494
4495 mdelay(20);
4496
4497 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4498
4499 mdelay(5);
4500
4501 switch (hw->mac_type) {
4502 case e1000_82541:
4503 case e1000_82547:
4504 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4505
4506 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4507
4508 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4509
4510 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4511
4512 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4513
4514 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4515
4516 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4517
4518 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4519
4520 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4521 break;
4522
4523 case e1000_82541_rev_2:
4524 case e1000_82547_rev_2:
4525 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4526 break;
4527 default:
4528 break;
4529 }
4530
4531 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4532
4533 mdelay(20);
4534
4535 /* Now enable the transmitter */
56b13b1e
ZRR		 4536 if (!ret_val)
4537 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
aa070789
RZ		 4538
4539 if (hw->mac_type == e1000_82547) {
4540 uint16_t fused, fine, coarse;
4541
4542 /* Move to analog registers page */
4543 e1000_read_phy_reg(hw,
4544 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4545
4546 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4547 e1000_read_phy_reg(hw,
4548 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4549
4550 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4551 coarse = fused
4552 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4553
4554 if (coarse >
4555 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4556 coarse -=
4557 IGP01E1000_ANALOG_FUSE_COARSE_10;
4558 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4559 } else if (coarse
4560 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4561 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4562
4563 fused = (fused
4564 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4565 (fine
4566 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4567 (coarse
4568 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4569
4570 e1000_write_phy_reg(hw,
4571 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4572 e1000_write_phy_reg(hw,
4573 IGP01E1000_ANALOG_FUSE_BYPASS,
4574 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4575 }
4576 }
4577 }
682011ff
WD		 4578}
4579
4580/******************************************************************************
4581* Resets the PHY
4582*
4583* hw - Struct containing variables accessed by shared code
4584*
aa070789 4585* Sets bit 15 of the MII Control register
682011ff 4586******************************************************************************/
aa070789 4587int32_t
682011ff
WD		 4588e1000_phy_reset(struct e1000_hw *hw)
4589{
aa070789 4590 int32_t ret_val;
682011ff
WD		 4591 uint16_t phy_data;
4592
4593 DEBUGFUNC();
4594
aa070789
RZ		 4595 /* In the case of the phy reset being blocked, it's not an error, we
4596 * simply return success without performing the reset. */
4597 ret_val = e1000_check_phy_reset_block(hw);
4598 if (ret_val)
4599 return E1000_SUCCESS;
4600
4601 switch (hw->phy_type) {
4602 case e1000_phy_igp:
4603 case e1000_phy_igp_2:
4604 case e1000_phy_igp_3:
4605 case e1000_phy_ife:
95186063 4606 case e1000_phy_igb:
aa070789
RZ		 4607 ret_val = e1000_phy_hw_reset(hw);
4608 if (ret_val)
4609 return ret_val;
4610 break;
4611 default:
4612 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4613 if (ret_val)
4614 return ret_val;
4615
4616 phy_data |= MII_CR_RESET;
4617 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4618 if (ret_val)
4619 return ret_val;
4620
4621 udelay(1);
4622 break;
682011ff 4623 }
aa070789
RZ		 4624
4625 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4626 e1000_phy_init_script(hw);
4627
4628 return E1000_SUCCESS;
682011ff
WD		 4629}
4630
1aeed8d7 4631static int e1000_set_phy_type (struct e1000_hw *hw)
ac3315c2 4632{
1aeed8d7
WD		 4633 DEBUGFUNC ();
4634
4635 if (hw->mac_type == e1000_undefined)
4636 return -E1000_ERR_PHY_TYPE;
4637
4638 switch (hw->phy_id) {
4639 case M88E1000_E_PHY_ID:
4640 case M88E1000_I_PHY_ID:
4641 case M88E1011_I_PHY_ID:
aa070789 4642 case M88E1111_I_PHY_ID:
1aeed8d7
WD		 4643 hw->phy_type = e1000_phy_m88;
4644 break;
4645 case IGP01E1000_I_PHY_ID:
4646 if (hw->mac_type == e1000_82541 ||
aa070789
RZ		 4647 hw->mac_type == e1000_82541_rev_2 ||
4648 hw->mac_type == e1000_82547 ||
4649 hw->mac_type == e1000_82547_rev_2) {
1aeed8d7 4650 hw->phy_type = e1000_phy_igp;
aa070789
RZ		 4651 break;
4652 }
4653 case IGP03E1000_E_PHY_ID:
4654 hw->phy_type = e1000_phy_igp_3;
4655 break;
4656 case IFE_E_PHY_ID:
4657 case IFE_PLUS_E_PHY_ID:
4658 case IFE_C_E_PHY_ID:
4659 hw->phy_type = e1000_phy_ife;
4660 break;
4661 case GG82563_E_PHY_ID:
4662 if (hw->mac_type == e1000_80003es2lan) {
4663 hw->phy_type = e1000_phy_gg82563;
1aeed8d7
WD		 4664 break;
4665 }
2c2668f9
RZ		 4666 case BME1000_E_PHY_ID:
4667 hw->phy_type = e1000_phy_bm;
4668 break;
95186063
MV		 4669 case I210_I_PHY_ID:
4670 hw->phy_type = e1000_phy_igb;
4671 break;
1aeed8d7
WD		 4672 /* Fall Through */
4673 default:
4674 /* Should never have loaded on this device */
4675 hw->phy_type = e1000_phy_undefined;
4676 return -E1000_ERR_PHY_TYPE;
4677 }
4678
4679 return E1000_SUCCESS;
ac3315c2
AS		 4680}
4681
682011ff
WD		 4682/******************************************************************************
4683* Probes the expected PHY address for known PHY IDs
4684*
4685* hw - Struct containing variables accessed by shared code
4686******************************************************************************/
aa070789 4687static int32_t
682011ff
WD		 4688e1000_detect_gig_phy(struct e1000_hw *hw)
4689{
aa070789 4690 int32_t phy_init_status, ret_val;
682011ff 4691 uint16_t phy_id_high, phy_id_low;
472d5460 4692 bool match = false;
682011ff
WD		 4693
4694 DEBUGFUNC();
4695
aa070789
RZ		 4696 /* The 82571 firmware may still be configuring the PHY. In this
4697 * case, we cannot access the PHY until the configuration is done. So
4698 * we explicitly set the PHY values. */
4699 if (hw->mac_type == e1000_82571 ||
4700 hw->mac_type == e1000_82572) {
4701 hw->phy_id = IGP01E1000_I_PHY_ID;
4702 hw->phy_type = e1000_phy_igp_2;
4703 return E1000_SUCCESS;
682011ff 4704 }
aa070789
RZ		 4705
4706 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4707 * work- around that forces PHY page 0 to be set or the reads fail.
4708 * The rest of the code in this routine uses e1000_read_phy_reg to
4709 * read the PHY ID. So for ESB-2 we need to have this set so our
4710 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4711 * the routines below will figure this out as well. */
4712 if (hw->mac_type == e1000_80003es2lan)
4713 hw->phy_type = e1000_phy_gg82563;
4714
4715 /* Read the PHY ID Registers to identify which PHY is onboard. */
4716 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4717 if (ret_val)
4718 return ret_val;
4719
682011ff 4720 hw->phy_id = (uint32_t) (phy_id_high << 16);
aa070789
RZ		 4721 udelay(20);
4722 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4723 if (ret_val)
4724 return ret_val;
4725
682011ff 4726 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
aa070789 4727 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
682011ff
WD		 4728
4729 switch (hw->mac_type) {
4730 case e1000_82543:
4731 if (hw->phy_id == M88E1000_E_PHY_ID)
472d5460 4732 match = true;
682011ff
WD		 4733 break;
4734 case e1000_82544:
4735 if (hw->phy_id == M88E1000_I_PHY_ID)
472d5460 4736 match = true;
682011ff
WD		 4737 break;
4738 case e1000_82540:
4739 case e1000_82545:
aa070789 4740 case e1000_82545_rev_3:
682011ff 4741 case e1000_82546:
aa070789 4742 case e1000_82546_rev_3:
682011ff 4743 if (hw->phy_id == M88E1011_I_PHY_ID)
472d5460 4744 match = true;
682011ff 4745 break;
aa070789 4746 case e1000_82541:
ac3315c2 4747 case e1000_82541_rev_2:
aa070789
RZ		 4748 case e1000_82547:
4749 case e1000_82547_rev_2:
ac3315c2 4750 if(hw->phy_id == IGP01E1000_I_PHY_ID)
472d5460 4751 match = true;
ac3315c2
AS		 4752
4753 break;
aa070789
RZ		 4754 case e1000_82573:
4755 if (hw->phy_id == M88E1111_I_PHY_ID)
472d5460 4756 match = true;
aa070789 4757 break;
2c2668f9
RZ		 4758 case e1000_82574:
4759 if (hw->phy_id == BME1000_E_PHY_ID)
472d5460 4760 match = true;
2c2668f9 4761 break;
aa070789
RZ		 4762 case e1000_80003es2lan:
4763 if (hw->phy_id == GG82563_E_PHY_ID)
472d5460 4764 match = true;
aa070789
RZ		 4765 break;
4766 case e1000_ich8lan:
4767 if (hw->phy_id == IGP03E1000_E_PHY_ID)
472d5460 4768 match = true;
aa070789 4769 if (hw->phy_id == IFE_E_PHY_ID)
472d5460 4770 match = true;
aa070789 4771 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
472d5460 4772 match = true;
aa070789 4773 if (hw->phy_id == IFE_C_E_PHY_ID)
472d5460 4774 match = true;
aa070789 4775 break;
95186063
MV		 4776 case e1000_igb:
4777 if (hw->phy_id == I210_I_PHY_ID)
4778 match = true;
4779 break;
682011ff
WD		 4780 default:
4781 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4782 return -E1000_ERR_CONFIG;
4783 }
ac3315c2
AS		 4784
4785 phy_init_status = e1000_set_phy_type(hw);
4786
4787 if ((match) && (phy_init_status == E1000_SUCCESS)) {
682011ff
WD		 4788 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4789 return 0;
4790 }
4791 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4792 return -E1000_ERR_PHY;
4793}
4794
aa070789
RZ		 4795/*****************************************************************************
4796 * Set media type and TBI compatibility.
4797 *
4798 * hw - Struct containing variables accessed by shared code
4799 * **************************************************************************/
4800void
4801e1000_set_media_type(struct e1000_hw *hw)
4802{
4803 uint32_t status;
4804
4805 DEBUGFUNC();
4806
4807 if (hw->mac_type != e1000_82543) {
4808 /* tbi_compatibility is only valid on 82543 */
472d5460 4809 hw->tbi_compatibility_en = false;
aa070789
RZ		 4810 }
4811
4812 switch (hw->device_id) {
4813 case E1000_DEV_ID_82545GM_SERDES:
4814 case E1000_DEV_ID_82546GB_SERDES:
4815 case E1000_DEV_ID_82571EB_SERDES:
4816 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4817 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4818 case E1000_DEV_ID_82572EI_SERDES:
4819 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4820 hw->media_type = e1000_media_type_internal_serdes;
4821 break;
4822 default:
4823 switch (hw->mac_type) {
4824 case e1000_82542_rev2_0:
4825 case e1000_82542_rev2_1:
4826 hw->media_type = e1000_media_type_fiber;
4827 break;
4828 case e1000_ich8lan:
4829 case e1000_82573:
2c2668f9 4830 case e1000_82574:
95186063 4831 case e1000_igb:
aa070789
RZ		 4832 /* The STATUS_TBIMODE bit is reserved or reused
4833 * for the this device.
4834 */
4835 hw->media_type = e1000_media_type_copper;
4836 break;
4837 default:
4838 status = E1000_READ_REG(hw, STATUS);
4839 if (status & E1000_STATUS_TBIMODE) {
4840 hw->media_type = e1000_media_type_fiber;
4841 /* tbi_compatibility not valid on fiber */
472d5460 4842 hw->tbi_compatibility_en = false;
aa070789
RZ		 4843 } else {
4844 hw->media_type = e1000_media_type_copper;
4845 }
4846 break;
4847 }
4848 }
4849}
4850
682011ff
WD		 4851/**
4852 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4853 *
4854 * e1000_sw_init initializes the Adapter private data structure.
4855 * Fields are initialized based on PCI device information and
4856 * OS network device settings (MTU size).
4857 **/
4858
4859static int
d60626f8 4860e1000_sw_init(struct eth_device *nic)
682011ff
WD		 4861{
4862 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4863 int result;
4864
4865 /* PCI config space info */
4866 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4867 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4868 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4869 &hw->subsystem_vendor_id);
4870 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4871
4872 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4873 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4874
4875 /* identify the MAC */
4876 result = e1000_set_mac_type(hw);
4877 if (result) {
d60626f8 4878 E1000_ERR(hw->nic, "Unknown MAC Type\n");
682011ff
WD		 4879 return result;
4880 }
4881
aa070789
RZ		 4882 switch (hw->mac_type) {
4883 default:
4884 break;
4885 case e1000_82541:
4886 case e1000_82547:
4887 case e1000_82541_rev_2:
4888 case e1000_82547_rev_2:
4889 hw->phy_init_script = 1;
4890 break;
4891 }
4892
682011ff
WD		 4893 /* flow control settings */
4894 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4895 hw->fc_low_water = E1000_FC_LOW_THRESH;
4896 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4897 hw->fc_send_xon = 1;
4898
4899 /* Media type - copper or fiber */
95186063 4900 hw->tbi_compatibility_en = true;
aa070789 4901 e1000_set_media_type(hw);
682011ff
WD		 4902
4903 if (hw->mac_type >= e1000_82543) {
4904 uint32_t status = E1000_READ_REG(hw, STATUS);
4905
4906 if (status & E1000_STATUS_TBIMODE) {
4907 DEBUGOUT("fiber interface\n");
4908 hw->media_type = e1000_media_type_fiber;
4909 } else {
4910 DEBUGOUT("copper interface\n");
4911 hw->media_type = e1000_media_type_copper;
4912 }
4913 } else {
4914 hw->media_type = e1000_media_type_fiber;
4915 }
4916
472d5460 4917 hw->wait_autoneg_complete = true;
682011ff
WD		 4918 if (hw->mac_type < e1000_82543)
4919 hw->report_tx_early = 0;
4920 else
4921 hw->report_tx_early = 1;
4922
682011ff
WD		 4923 return E1000_SUCCESS;
4924}
4925
4926void
4927fill_rx(struct e1000_hw *hw)
4928{
4929 struct e1000_rx_desc *rd;
06e07f65 4930 unsigned long flush_start, flush_end;
682011ff
WD		 4931
4932 rx_last = rx_tail;
4933 rd = rx_base + rx_tail;
4934 rx_tail = (rx_tail + 1) % 8;
4935 memset(rd, 0, 16);
06e07f65 4936 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
873e8e01
MV		 4937
4938 /*
4939 * Make sure there are no stale data in WB over this area, which
4940 * might get written into the memory while the e1000 also writes
4941 * into the same memory area.
4942 */
06e07f65
ML		 4943 invalidate_dcache_range((unsigned long)packet,
4944 (unsigned long)packet + 4096);
873e8e01 4945 /* Dump the DMA descriptor into RAM. */
06e07f65 4946 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 4947 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4948 flush_dcache_range(flush_start, flush_end);
4949
682011ff
WD		 4950 E1000_WRITE_REG(hw, RDT, rx_tail);
4951}
4952
4953/**
4954 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4955 * @adapter: board private structure
4956 *
4957 * Configure the Tx unit of the MAC after a reset.
4958 **/
4959
4960static void
4961e1000_configure_tx(struct e1000_hw *hw)
4962{
682011ff 4963 unsigned long tctl;
aa070789
RZ		 4964 unsigned long tipg, tarc;
4965 uint32_t ipgr1, ipgr2;
682011ff 4966
06e07f65 4967 E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base);
682011ff
WD		 4968 E1000_WRITE_REG(hw, TDBAH, 0);
4969
4970 E1000_WRITE_REG(hw, TDLEN, 128);
4971
4972 /* Setup the HW Tx Head and Tail descriptor pointers */
4973 E1000_WRITE_REG(hw, TDH, 0);
4974 E1000_WRITE_REG(hw, TDT, 0);
4975 tx_tail = 0;
4976
aa070789
RZ		 4977 /* Set the default values for the Tx Inter Packet Gap timer */
4978 if (hw->mac_type <= e1000_82547_rev_2 &&
4979 (hw->media_type == e1000_media_type_fiber ||
4980 hw->media_type == e1000_media_type_internal_serdes))
4981 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4982 else
4983 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4984
682011ff
WD		 4985 /* Set the default values for the Tx Inter Packet Gap timer */
4986 switch (hw->mac_type) {
4987 case e1000_82542_rev2_0:
4988 case e1000_82542_rev2_1:
4989 tipg = DEFAULT_82542_TIPG_IPGT;
aa070789
RZ		 4990 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4991 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4992 break;
4993 case e1000_80003es2lan:
4994 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4995 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
682011ff
WD		 4996 break;
4997 default:
aa070789
RZ		 4998 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4999 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5000 break;
682011ff 5001 }
aa070789
RZ		 5002 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5003 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
682011ff 5004 E1000_WRITE_REG(hw, TIPG, tipg);
682011ff
WD		 5005 /* Program the Transmit Control Register */
5006 tctl = E1000_READ_REG(hw, TCTL);
5007 tctl &= ~E1000_TCTL_CT;
5008 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5009 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
aa070789
RZ		 5010
5011 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5012 tarc = E1000_READ_REG(hw, TARC0);
5013 /* set the speed mode bit, we'll clear it if we're not at
5014 * gigabit link later */
5015 /* git bit can be set to 1*/
5016 } else if (hw->mac_type == e1000_80003es2lan) {
5017 tarc = E1000_READ_REG(hw, TARC0);
5018 tarc |= 1;
5019 E1000_WRITE_REG(hw, TARC0, tarc);
5020 tarc = E1000_READ_REG(hw, TARC1);
5021 tarc |= 1;
5022 E1000_WRITE_REG(hw, TARC1, tarc);
5023 }
5024
682011ff
WD		 5025
5026 e1000_config_collision_dist(hw);
aa070789
RZ		 5027 /* Setup Transmit Descriptor Settings for eop descriptor */
5028 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
682011ff 5029
aa070789
RZ		 5030 /* Need to set up RS bit */
5031 if (hw->mac_type < e1000_82543)
5032 hw->txd_cmd |= E1000_TXD_CMD_RPS;
682011ff 5033 else
aa070789 5034 hw->txd_cmd |= E1000_TXD_CMD_RS;
95186063
MV		 5035
5036
5037 if (hw->mac_type == e1000_igb) {
5038 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5039
5040 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5041 reg_txdctl |= 1 << 25;
5042 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5043 mdelay(20);
5044 }
5045
5046
5047
aa070789 5048 E1000_WRITE_REG(hw, TCTL, tctl);
95186063
MV		 5049
5050
682011ff
WD		 5051}
5052
5053/**
5054 * e1000_setup_rctl - configure the receive control register
5055 * @adapter: Board private structure
5056 **/
5057static void
5058e1000_setup_rctl(struct e1000_hw *hw)
5059{
5060 uint32_t rctl;
5061
5062 rctl = E1000_READ_REG(hw, RCTL);
5063
5064 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5065
aa070789
RZ		 5066 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5067 | E1000_RCTL_RDMTS_HALF; /* |
5068 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
682011ff
WD		 5069
5070 if (hw->tbi_compatibility_on == 1)
5071 rctl |= E1000_RCTL_SBP;
5072 else
5073 rctl &= ~E1000_RCTL_SBP;
5074
5075 rctl &= ~(E1000_RCTL_SZ_4096);
682011ff
WD		 5076 rctl |= E1000_RCTL_SZ_2048;
5077 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
682011ff
WD		 5078 E1000_WRITE_REG(hw, RCTL, rctl);
5079}
5080
5081/**
5082 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5083 * @adapter: board private structure
5084 *
5085 * Configure the Rx unit of the MAC after a reset.
5086 **/
5087static void
5088e1000_configure_rx(struct e1000_hw *hw)
5089{
aa070789 5090 unsigned long rctl, ctrl_ext;
682011ff
WD		 5091 rx_tail = 0;
5092 /* make sure receives are disabled while setting up the descriptors */
5093 rctl = E1000_READ_REG(hw, RCTL);
5094 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
682011ff 5095 if (hw->mac_type >= e1000_82540) {
682011ff
WD		 5096 /* Set the interrupt throttling rate. Value is calculated
5097 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
1aeed8d7
WD		 5098#define MAX_INTS_PER_SEC 8000
5099#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
682011ff
WD		 5100 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5101 }
5102
aa070789
RZ		 5103 if (hw->mac_type >= e1000_82571) {
5104 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5105 /* Reset delay timers after every interrupt */
5106 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5107 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5108 E1000_WRITE_FLUSH(hw);
5109 }
682011ff 5110 /* Setup the Base and Length of the Rx Descriptor Ring */
06e07f65 5111 E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base);
682011ff
WD		 5112 E1000_WRITE_REG(hw, RDBAH, 0);
5113
5114 E1000_WRITE_REG(hw, RDLEN, 128);
5115
5116 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5117 E1000_WRITE_REG(hw, RDH, 0);
5118 E1000_WRITE_REG(hw, RDT, 0);
682011ff
WD		 5119 /* Enable Receives */
5120
95186063
MV		 5121 if (hw->mac_type == e1000_igb) {
5122
5123 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5124 reg_rxdctl |= 1 << 25;
5125 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5126 mdelay(20);
5127 }
5128
682011ff 5129 E1000_WRITE_REG(hw, RCTL, rctl);
95186063 5130
682011ff
WD		 5131 fill_rx(hw);
5132}
5133
5134/**************************************************************************
5135POLL - Wait for a frame
5136***************************************************************************/
5137static int
5138e1000_poll(struct eth_device *nic)
5139{
5140 struct e1000_hw *hw = nic->priv;
5141 struct e1000_rx_desc *rd;
06e07f65 5142 unsigned long inval_start, inval_end;
873e8e01
MV		 5143 uint32_t len;
5144
682011ff
WD		 5145 /* return true if there's an ethernet packet ready to read */
5146 rd = rx_base + rx_last;
873e8e01
MV		 5147
5148 /* Re-load the descriptor from RAM. */
06e07f65 5149 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5150 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5151 invalidate_dcache_range(inval_start, inval_end);
5152
682011ff
WD		 5153 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5154 return 0;
5155 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
873e8e01
MV		 5156 /* Packet received, make sure the data are re-loaded from RAM. */
5157 len = le32_to_cpu(rd->length);
06e07f65
ML		 5158 invalidate_dcache_range((unsigned long)packet,
5159 (unsigned long)packet +
5160 roundup(len, ARCH_DMA_MINALIGN));
1fd92db8 5161 net_process_received_packet((uchar *)packet, len);
682011ff
WD		 5162 fill_rx(hw);
5163 return 1;
5164}
5165
5166/**************************************************************************
5167TRANSMIT - Transmit a frame
5168***************************************************************************/
873e8e01 5169static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
682011ff 5170{
873e8e01 5171 void *nv_packet = (void *)txpacket;
682011ff
WD		 5172 struct e1000_hw *hw = nic->priv;
5173 struct e1000_tx_desc *txp;
5174 int i = 0;
06e07f65 5175 unsigned long flush_start, flush_end;
682011ff
WD		 5176
5177 txp = tx_base + tx_tail;
5178 tx_tail = (tx_tail + 1) % 8;
5179
8aa858cb 5180 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
aa070789 5181 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
682011ff 5182 txp->upper.data = 0;
873e8e01
MV		 5183
5184 /* Dump the packet into RAM so e1000 can pick them. */
06e07f65
ML		 5185 flush_dcache_range((unsigned long)nv_packet,
5186 (unsigned long)nv_packet +
5187 roundup(length, ARCH_DMA_MINALIGN));
873e8e01 5188 /* Dump the descriptor into RAM as well. */
06e07f65 5189 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5190 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5191 flush_dcache_range(flush_start, flush_end);
5192
682011ff
WD		 5193 E1000_WRITE_REG(hw, TDT, tx_tail);
5194
aa070789 5195 E1000_WRITE_FLUSH(hw);
873e8e01
MV		 5196 while (1) {
5197 invalidate_dcache_range(flush_start, flush_end);
5198 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5199 break;
682011ff
WD		 5200 if (i++ > TOUT_LOOP) {
5201 DEBUGOUT("e1000: tx timeout\n");
5202 return 0;
5203 }
5204 udelay(10); /* give the nic a chance to write to the register */
5205 }
5206 return 1;
5207}
5208
5209/*reset function*/
5210static inline int
5211e1000_reset(struct eth_device *nic)
5212{
5213 struct e1000_hw *hw = nic->priv;
5214
5215 e1000_reset_hw(hw);
5216 if (hw->mac_type >= e1000_82544) {
5217 E1000_WRITE_REG(hw, WUC, 0);
5218 }
5219 return e1000_init_hw(nic);
5220}
5221
5222/**************************************************************************
5223DISABLE - Turn off ethernet interface
5224***************************************************************************/
5225static void
5226e1000_disable(struct eth_device *nic)
5227{
5228 struct e1000_hw *hw = nic->priv;
5229
5230 /* Turn off the ethernet interface */
5231 E1000_WRITE_REG(hw, RCTL, 0);
5232 E1000_WRITE_REG(hw, TCTL, 0);
5233
5234 /* Clear the transmit ring */
5235 E1000_WRITE_REG(hw, TDH, 0);
5236 E1000_WRITE_REG(hw, TDT, 0);
5237
5238 /* Clear the receive ring */
5239 E1000_WRITE_REG(hw, RDH, 0);
5240 E1000_WRITE_REG(hw, RDT, 0);
5241
5242 /* put the card in its initial state */
5243#if 0
5244 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5245#endif
5246 mdelay(10);
5247
5248}
5249
5250/**************************************************************************
5251INIT - set up ethernet interface(s)
5252***************************************************************************/
5253static int
5254e1000_init(struct eth_device *nic, bd_t * bis)
5255{
5256 struct e1000_hw *hw = nic->priv;
5257 int ret_val = 0;
5258
5259 ret_val = e1000_reset(nic);
5260 if (ret_val < 0) {
5261 if ((ret_val == -E1000_ERR_NOLINK) ||
5262 (ret_val == -E1000_ERR_TIMEOUT)) {
d60626f8 5263 E1000_ERR(hw->nic, "Valid Link not detected\n");
682011ff 5264 } else {
d60626f8 5265 E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
682011ff
WD		 5266 }
5267 return 0;
5268 }
5269 e1000_configure_tx(hw);
5270 e1000_setup_rctl(hw);
5271 e1000_configure_rx(hw);
5272 return 1;
5273}
5274
aa070789
RZ		 5275/******************************************************************************
5276 * Gets the current PCI bus type of hardware
5277 *
5278 * hw - Struct containing variables accessed by shared code
5279 *****************************************************************************/
5280void e1000_get_bus_type(struct e1000_hw *hw)
5281{
5282 uint32_t status;
5283
5284 switch (hw->mac_type) {
5285 case e1000_82542_rev2_0:
5286 case e1000_82542_rev2_1:
5287 hw->bus_type = e1000_bus_type_pci;
5288 break;
5289 case e1000_82571:
5290 case e1000_82572:
5291 case e1000_82573:
2c2668f9 5292 case e1000_82574:
aa070789 5293 case e1000_80003es2lan:
aa070789 5294 case e1000_ich8lan:
95186063 5295 case e1000_igb:
aa070789
RZ		 5296 hw->bus_type = e1000_bus_type_pci_express;
5297 break;
5298 default:
5299 status = E1000_READ_REG(hw, STATUS);
5300 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5301 e1000_bus_type_pcix : e1000_bus_type_pci;
5302 break;
5303 }
5304}
5305
ce5207e1
KM		 5306/* A list of all registered e1000 devices */
5307static LIST_HEAD(e1000_hw_list);
5308
682011ff
WD		 5309/**************************************************************************
5310PROBE - Look for an adapter, this routine's visible to the outside
5311You should omit the last argument struct pci_device * for a non-PCI NIC
5312***************************************************************************/
5313int
5314e1000_initialize(bd_t * bis)
5315{
d60626f8 5316 unsigned int i;
682011ff 5317 pci_dev_t devno;
682011ff 5318
f81ecb5d
TT		 5319 DEBUGFUNC();
5320
d60626f8
KM		 5321 /* Find and probe all the matching PCI devices */
5322 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5323 u32 val;
4b29bdb0 5324
d60626f8
KM		 5325 /*
5326 * These will never get freed due to errors, this allows us to
5327 * perform SPI EEPROM programming from U-boot, for example.
5328 */
5329 struct eth_device *nic = malloc(sizeof(*nic));
5330 struct e1000_hw *hw = malloc(sizeof(*hw));
5331 if (!nic || !hw) {
5332 printf("e1000#%u: Out of Memory!\n", i);
4b29bdb0 5333 free(nic);
d60626f8
KM		 5334 free(hw);
5335 continue;
4b29bdb0
KG		 5336 }
5337
d60626f8 5338 /* Make sure all of the fields are initially zeroed */
f7ac99fd 5339 memset(nic, 0, sizeof(*nic));
4b29bdb0
KG		 5340 memset(hw, 0, sizeof(*hw));
5341
d60626f8
KM		 5342 /* Assign the passed-in values */
5343 hw->cardnum = i;
682011ff 5344 hw->pdev = devno;
d60626f8 5345 hw->nic = nic;
682011ff 5346 nic->priv = hw;
682011ff 5347
d60626f8
KM		 5348 /* Generate a card name */
5349 sprintf(nic->name, "e1000#%u", hw->cardnum);
5350
5351 /* Print a debug message with the IO base address */
5352 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5353 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5354
5355 /* Try to enable I/O accesses and bus-mastering */
5356 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5357 pci_write_config_dword(devno, PCI_COMMAND, val);
5358
5359 /* Make sure it worked */
5360 pci_read_config_dword(devno, PCI_COMMAND, &val);
5361 if (!(val & PCI_COMMAND_MEMORY)) {
5362 E1000_ERR(nic, "Can't enable I/O memory\n");
5363 continue;
5364 }
5365 if (!(val & PCI_COMMAND_MASTER)) {
5366 E1000_ERR(nic, "Can't enable bus-mastering\n");
5367 continue;
5368 }
682011ff
WD		 5369
5370 /* Are these variables needed? */
682011ff
WD		 5371 hw->fc = e1000_fc_default;
5372 hw->original_fc = e1000_fc_default;
682011ff 5373 hw->autoneg_failed = 0;
aa070789 5374 hw->autoneg = 1;
472d5460 5375 hw->get_link_status = true;
a4277200 5376#ifndef CONFIG_E1000_NO_NVM
95186063 5377 hw->eeprom_semaphore_present = true;
a4277200 5378#endif
d60626f8
KM		 5379 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5380 PCI_REGION_MEM);
682011ff
WD		 5381 hw->mac_type = e1000_undefined;
5382
5383 /* MAC and Phy settings */
d60626f8
KM		 5384 if (e1000_sw_init(nic) < 0) {
5385 E1000_ERR(nic, "Software init failed\n");
5386 continue;
682011ff 5387 }
aa070789 5388 if (e1000_check_phy_reset_block(hw))
d60626f8
KM		 5389 E1000_ERR(nic, "PHY Reset is blocked!\n");
5390
ce5207e1 5391 /* Basic init was OK, reset the hardware and allow SPI access */
aa070789 5392 e1000_reset_hw(hw);
ce5207e1 5393 list_add_tail(&hw->list_node, &e1000_hw_list);
d60626f8 5394
8712adfd 5395#ifndef CONFIG_E1000_NO_NVM
d60626f8 5396 /* Validate the EEPROM and get chipset information */
a821d08d 5397#if !defined(CONFIG_MVBC_1G)
aa070789 5398 if (e1000_init_eeprom_params(hw)) {
d60626f8
KM		 5399 E1000_ERR(nic, "EEPROM is invalid!\n");
5400 continue;
aa070789 5401 }
95186063
MV		 5402 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5403 e1000_validate_eeprom_checksum(hw))
d60626f8 5404 continue;
7521af1c 5405#endif
682011ff 5406 e1000_read_mac_addr(nic);
8712adfd 5407#endif
aa070789 5408 e1000_get_bus_type(hw);
682011ff 5409
8712adfd 5410#ifndef CONFIG_E1000_NO_NVM
d60626f8 5411 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
682011ff
WD		 5412 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5413 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
8712adfd
RI		 5414#else
5415 memset(nic->enetaddr, 0, 6);
5416 printf("e1000: no NVM\n");
5417#endif
682011ff 5418
d60626f8 5419 /* Set up the function pointers and register the device */
682011ff
WD		 5420 nic->init = e1000_init;
5421 nic->recv = e1000_poll;
5422 nic->send = e1000_transmit;
5423 nic->halt = e1000_disable;
682011ff 5424 eth_register(nic);
682011ff 5425 }
d60626f8
KM		 5426
5427 return i;
682011ff 5428}
ce5207e1
KM		 5429
5430struct e1000_hw *e1000_find_card(unsigned int cardnum)
5431{
5432 struct e1000_hw *hw;
5433
5434 list_for_each_entry(hw, &e1000_hw_list, list_node)
5435 if (hw->cardnum == cardnum)
5436 return hw;
5437
5438 return NULL;
5439}
5440
5441#ifdef CONFIG_CMD_E1000
5442static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5443 int argc, char * const argv[])
5444{
5445 struct e1000_hw *hw;
5446
5447 if (argc < 3) {
5448 cmd_usage(cmdtp);
5449 return 1;
5450 }
5451
5452 /* Make sure we can find the requested e1000 card */
5453 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5454 if (!hw) {
5455 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5456 return 1;
5457 }
5458
5459 if (!strcmp(argv[2], "print-mac-address")) {
5460 unsigned char *mac = hw->nic->enetaddr;
5461 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5462 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5463 return 0;
5464 }
5465
5466#ifdef CONFIG_E1000_SPI
5467 /* Handle the "SPI" subcommand */
5468 if (!strcmp(argv[2], "spi"))
5469 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5470#endif
5471
5472 cmd_usage(cmdtp);
5473 return 1;
5474}
5475
5476U_BOOT_CMD(
5477 e1000, 7, 0, do_e1000,
5478 "Intel e1000 controller management",
5479 /* */"<card#> print-mac-address\n"
5480#ifdef CONFIG_E1000_SPI
5481 "e1000 <card#> spi show [<offset> [<length>]]\n"
5482 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5483 "e1000 <card#> spi program <addr> <offset> <length>\n"
5484 "e1000 <card#> spi checksum [update]\n"
5485#endif
5486 " - Manage the Intel E1000 PCI device"
5487);
5488#endif /* not CONFIG_CMD_E1000 */
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