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Net: Add Intel E1000 82574L PCIe card support
[people/ms/u-boot.git] / drivers / net / e1000.c
CommitLineData
682011ff 1/**************************************************************************
ac3315c2 2Intel Pro 1000 for ppcboot/das-u-boot
682011ff
WD		 3Drivers are port from Intel's Linux driver e1000-4.3.15
4and from Etherboot pro 1000 driver by mrakes at vivato dot net
5tested on both gig copper and gig fiber boards
6***************************************************************************/
7/*******************************************************************************
8
8bde7f77 9
682011ff 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
8bde7f77
WD		 11
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the Free
14 Software Foundation; either version 2 of the License, or (at your option)
682011ff 15 any later version.
8bde7f77
WD		 16
17 This program is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
682011ff 20 more details.
8bde7f77 21
682011ff 22 You should have received a copy of the GNU General Public License along with
8bde7f77 23 this program; if not, write to the Free Software Foundation, Inc., 59
1aeed8d7 24 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
8bde7f77 25
682011ff
WD		 26 The full GNU General Public License is included in this distribution in the
27 file called LICENSE.
8bde7f77 28
682011ff
WD		 29 Contact Information:
30 Linux NICS <linux.nics@intel.com>
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33*******************************************************************************/
34/*
35 * Copyright (C) Archway Digital Solutions.
36 *
37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38 * 2/9/2002
39 *
40 * Copyright (C) Linux Networx.
41 * Massive upgrade to work with the new intel gigabit NICs.
42 * <ebiederman at lnxi dot com>
2c2668f9
RZ		 43 *
44 * Copyright 2011 Freescale Semiconductor, Inc.
682011ff
WD		 45 */
46
47#include "e1000.h"
48
682011ff
WD		 49#define TOUT_LOOP 100000
50
f81ecb5d 51#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
682011ff 52#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
1aeed8d7 53#define mdelay(n) udelay((n)*1000)
682011ff 54
9ea005fb
RZ		 55#define E1000_DEFAULT_PCI_PBA 0x00000030
56#define E1000_DEFAULT_PCIE_PBA 0x000a0026
682011ff
WD		 57
58/* NIC specific static variables go here */
59
60static char tx_pool[128 + 16];
61static char rx_pool[128 + 16];
62static char packet[2096];
63
64static struct e1000_tx_desc *tx_base;
65static struct e1000_rx_desc *rx_base;
66
67static int tx_tail;
68static int rx_tail, rx_last;
69
70static struct pci_device_id supported[] = {
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
8915f118 80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
682011ff
WD		 81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
2ab4a4d0 84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
682011ff 85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
ac3315c2 86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
aa3b8bf9 87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
aa070789
RZ		 88 /* E1000 PCIe card */
89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
2c2668f9 105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
aa070789
RZ		 106 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
107 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
108 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
109 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
110 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
1bc43437 111 {}
682011ff
WD		 112};
113
114/* Function forward declarations */
115static int e1000_setup_link(struct eth_device *nic);
116static int e1000_setup_fiber_link(struct eth_device *nic);
117static int e1000_setup_copper_link(struct eth_device *nic);
118static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
119static void e1000_config_collision_dist(struct e1000_hw *hw);
120static int e1000_config_mac_to_phy(struct e1000_hw *hw);
121static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
122static int e1000_check_for_link(struct eth_device *nic);
123static int e1000_wait_autoneg(struct e1000_hw *hw);
aa070789 124static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
682011ff
WD		 125 uint16_t * duplex);
126static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
127 uint16_t * phy_data);
128static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
129 uint16_t phy_data);
aa070789 130static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
682011ff
WD		 131static int e1000_phy_reset(struct e1000_hw *hw);
132static int e1000_detect_gig_phy(struct e1000_hw *hw);
aa070789
RZ		 133static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
134static void e1000_set_media_type(struct e1000_hw *hw);
135
136static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
137static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
682011ff
WD		 138#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
139#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
140#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
141 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
142#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
8bde7f77 143 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
682011ff
WD		 144#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
145
7521af1c 146#ifndef CONFIG_AP1000 /* remove for warnings */
ecbd2078
RZ		 147static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
148 uint16_t words,
149 uint16_t *data);
682011ff
WD		 150/******************************************************************************
151 * Raises the EEPROM's clock input.
152 *
153 * hw - Struct containing variables accessed by shared code
154 * eecd - EECD's current value
155 *****************************************************************************/
156static void
157e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
158{
159 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
160 * wait 50 microseconds.
161 */
162 *eecd = *eecd | E1000_EECD_SK;
163 E1000_WRITE_REG(hw, EECD, *eecd);
164 E1000_WRITE_FLUSH(hw);
165 udelay(50);
166}
167
168/******************************************************************************
169 * Lowers the EEPROM's clock input.
170 *
8bde7f77 171 * hw - Struct containing variables accessed by shared code
682011ff
WD		 172 * eecd - EECD's current value
173 *****************************************************************************/
174static void
175e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
176{
8bde7f77
WD		 177 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
178 * wait 50 microseconds.
682011ff
WD		 179 */
180 *eecd = *eecd & ~E1000_EECD_SK;
181 E1000_WRITE_REG(hw, EECD, *eecd);
182 E1000_WRITE_FLUSH(hw);
183 udelay(50);
184}
185
186/******************************************************************************
187 * Shift data bits out to the EEPROM.
188 *
189 * hw - Struct containing variables accessed by shared code
190 * data - data to send to the EEPROM
191 * count - number of bits to shift out
192 *****************************************************************************/
193static void
194e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
195{
196 uint32_t eecd;
197 uint32_t mask;
198
199 /* We need to shift "count" bits out to the EEPROM. So, value in the
200 * "data" parameter will be shifted out to the EEPROM one bit at a time.
8bde7f77 201 * In order to do this, "data" must be broken down into bits.
682011ff
WD		 202 */
203 mask = 0x01 << (count - 1);
204 eecd = E1000_READ_REG(hw, EECD);
205 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
206 do {
207 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
208 * and then raising and then lowering the clock (the SK bit controls
209 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
210 * by setting "DI" to "0" and then raising and then lowering the clock.
211 */
212 eecd &= ~E1000_EECD_DI;
213
214 if (data & mask)
215 eecd |= E1000_EECD_DI;
216
217 E1000_WRITE_REG(hw, EECD, eecd);
218 E1000_WRITE_FLUSH(hw);
219
220 udelay(50);
221
222 e1000_raise_ee_clk(hw, &eecd);
223 e1000_lower_ee_clk(hw, &eecd);
224
225 mask = mask >> 1;
226
227 } while (mask);
228
229 /* We leave the "DI" bit set to "0" when we leave this routine. */
230 eecd &= ~E1000_EECD_DI;
231 E1000_WRITE_REG(hw, EECD, eecd);
232}
233
234/******************************************************************************
235 * Shift data bits in from the EEPROM
236 *
237 * hw - Struct containing variables accessed by shared code
238 *****************************************************************************/
239static uint16_t
aa070789 240e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
682011ff
WD		 241{
242 uint32_t eecd;
243 uint32_t i;
244 uint16_t data;
245
aa070789
RZ		 246 /* In order to read a register from the EEPROM, we need to shift 'count'
247 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
248 * input to the EEPROM (setting the SK bit), and then reading the
249 * value of the "DO" bit. During this "shifting in" process the
250 * "DI" bit should always be clear.
682011ff
WD		 251 */
252
253 eecd = E1000_READ_REG(hw, EECD);
254
255 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
256 data = 0;
257
aa070789 258 for (i = 0; i < count; i++) {
682011ff
WD		 259 data = data << 1;
260 e1000_raise_ee_clk(hw, &eecd);
261
262 eecd = E1000_READ_REG(hw, EECD);
263
264 eecd &= ~(E1000_EECD_DI);
265 if (eecd & E1000_EECD_DO)
266 data |= 1;
267
268 e1000_lower_ee_clk(hw, &eecd);
269 }
270
271 return data;
272}
273
274/******************************************************************************
aa070789 275 * Returns EEPROM to a "standby" state
682011ff
WD		 276 *
277 * hw - Struct containing variables accessed by shared code
682011ff
WD		 278 *****************************************************************************/
279static void
aa070789 280e1000_standby_eeprom(struct e1000_hw *hw)
682011ff 281{
aa070789 282 struct e1000_eeprom_info *eeprom = &hw->eeprom;
682011ff
WD		 283 uint32_t eecd;
284
285 eecd = E1000_READ_REG(hw, EECD);
286
aa070789
RZ		 287 if (eeprom->type == e1000_eeprom_microwire) {
288 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
289 E1000_WRITE_REG(hw, EECD, eecd);
290 E1000_WRITE_FLUSH(hw);
291 udelay(eeprom->delay_usec);
682011ff 292
aa070789
RZ		 293 /* Clock high */
294 eecd |= E1000_EECD_SK;
295 E1000_WRITE_REG(hw, EECD, eecd);
296 E1000_WRITE_FLUSH(hw);
297 udelay(eeprom->delay_usec);
298
299 /* Select EEPROM */
300 eecd |= E1000_EECD_CS;
301 E1000_WRITE_REG(hw, EECD, eecd);
302 E1000_WRITE_FLUSH(hw);
303 udelay(eeprom->delay_usec);
304
305 /* Clock low */
306 eecd &= ~E1000_EECD_SK;
307 E1000_WRITE_REG(hw, EECD, eecd);
308 E1000_WRITE_FLUSH(hw);
309 udelay(eeprom->delay_usec);
310 } else if (eeprom->type == e1000_eeprom_spi) {
311 /* Toggle CS to flush commands */
312 eecd |= E1000_EECD_CS;
313 E1000_WRITE_REG(hw, EECD, eecd);
314 E1000_WRITE_FLUSH(hw);
315 udelay(eeprom->delay_usec);
316 eecd &= ~E1000_EECD_CS;
317 E1000_WRITE_REG(hw, EECD, eecd);
318 E1000_WRITE_FLUSH(hw);
319 udelay(eeprom->delay_usec);
320 }
321}
322
323/***************************************************************************
324* Description: Determines if the onboard NVM is FLASH or EEPROM.
325*
326* hw - Struct containing variables accessed by shared code
327****************************************************************************/
328static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
329{
330 uint32_t eecd = 0;
331
332 DEBUGFUNC();
333
334 if (hw->mac_type == e1000_ich8lan)
335 return FALSE;
336
2c2668f9 337 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
aa070789
RZ		 338 eecd = E1000_READ_REG(hw, EECD);
339
340 /* Isolate bits 15 & 16 */
341 eecd = ((eecd >> 15) & 0x03);
342
343 /* If both bits are set, device is Flash type */
344 if (eecd == 0x03)
345 return FALSE;
346 }
347 return TRUE;
682011ff
WD		 348}
349
350/******************************************************************************
aa070789 351 * Prepares EEPROM for access
8bde7f77 352 *
682011ff 353 * hw - Struct containing variables accessed by shared code
aa070789
RZ		 354 *
355 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
356 * function should be called before issuing a command to the EEPROM.
682011ff 357 *****************************************************************************/
aa070789
RZ		 358static int32_t
359e1000_acquire_eeprom(struct e1000_hw *hw)
682011ff 360{
aa070789
RZ		 361 struct e1000_eeprom_info *eeprom = &hw->eeprom;
362 uint32_t eecd, i = 0;
682011ff 363
f81ecb5d 364 DEBUGFUNC();
aa070789
RZ		 365
366 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
367 return -E1000_ERR_SWFW_SYNC;
682011ff
WD		 368 eecd = E1000_READ_REG(hw, EECD);
369
2c2668f9 370 if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
aa070789
RZ		 371 /* Request EEPROM Access */
372 if (hw->mac_type > e1000_82544) {
373 eecd |= E1000_EECD_REQ;
374 E1000_WRITE_REG(hw, EECD, eecd);
375 eecd = E1000_READ_REG(hw, EECD);
376 while ((!(eecd & E1000_EECD_GNT)) &&
377 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
378 i++;
379 udelay(5);
380 eecd = E1000_READ_REG(hw, EECD);
381 }
382 if (!(eecd & E1000_EECD_GNT)) {
383 eecd &= ~E1000_EECD_REQ;
384 E1000_WRITE_REG(hw, EECD, eecd);
385 DEBUGOUT("Could not acquire EEPROM grant\n");
386 return -E1000_ERR_EEPROM;
387 }
388 }
389 }
682011ff 390
aa070789 391 /* Setup EEPROM for Read/Write */
682011ff 392
aa070789
RZ		 393 if (eeprom->type == e1000_eeprom_microwire) {
394 /* Clear SK and DI */
395 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
396 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 397
aa070789
RZ		 398 /* Set CS */
399 eecd |= E1000_EECD_CS;
400 E1000_WRITE_REG(hw, EECD, eecd);
401 } else if (eeprom->type == e1000_eeprom_spi) {
402 /* Clear SK and CS */
403 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
404 E1000_WRITE_REG(hw, EECD, eecd);
405 udelay(1);
406 }
407
408 return E1000_SUCCESS;
682011ff
WD		 409}
410
411/******************************************************************************
aa070789
RZ		 412 * Sets up eeprom variables in the hw struct. Must be called after mac_type
413 * is configured. Additionally, if this is ICH8, the flash controller GbE
414 * registers must be mapped, or this will crash.
682011ff
WD		 415 *
416 * hw - Struct containing variables accessed by shared code
682011ff 417 *****************************************************************************/
aa070789 418static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
682011ff 419{
aa070789
RZ		 420 struct e1000_eeprom_info *eeprom = &hw->eeprom;
421 uint32_t eecd = E1000_READ_REG(hw, EECD);
422 int32_t ret_val = E1000_SUCCESS;
423 uint16_t eeprom_size;
682011ff 424
f81ecb5d 425 DEBUGFUNC();
aa070789
RZ		 426
427 switch (hw->mac_type) {
428 case e1000_82542_rev2_0:
429 case e1000_82542_rev2_1:
430 case e1000_82543:
431 case e1000_82544:
432 eeprom->type = e1000_eeprom_microwire;
433 eeprom->word_size = 64;
434 eeprom->opcode_bits = 3;
435 eeprom->address_bits = 6;
436 eeprom->delay_usec = 50;
437 eeprom->use_eerd = FALSE;
438 eeprom->use_eewr = FALSE;
439 break;
440 case e1000_82540:
441 case e1000_82545:
442 case e1000_82545_rev_3:
443 case e1000_82546:
444 case e1000_82546_rev_3:
445 eeprom->type = e1000_eeprom_microwire;
446 eeprom->opcode_bits = 3;
447 eeprom->delay_usec = 50;
448 if (eecd & E1000_EECD_SIZE) {
449 eeprom->word_size = 256;
450 eeprom->address_bits = 8;
451 } else {
452 eeprom->word_size = 64;
453 eeprom->address_bits = 6;
454 }
455 eeprom->use_eerd = FALSE;
456 eeprom->use_eewr = FALSE;
457 break;
458 case e1000_82541:
459 case e1000_82541_rev_2:
460 case e1000_82547:
461 case e1000_82547_rev_2:
462 if (eecd & E1000_EECD_TYPE) {
463 eeprom->type = e1000_eeprom_spi;
464 eeprom->opcode_bits = 8;
465 eeprom->delay_usec = 1;
466 if (eecd & E1000_EECD_ADDR_BITS) {
467 eeprom->page_size = 32;
468 eeprom->address_bits = 16;
469 } else {
470 eeprom->page_size = 8;
471 eeprom->address_bits = 8;
472 }
473 } else {
474 eeprom->type = e1000_eeprom_microwire;
475 eeprom->opcode_bits = 3;
476 eeprom->delay_usec = 50;
477 if (eecd & E1000_EECD_ADDR_BITS) {
478 eeprom->word_size = 256;
479 eeprom->address_bits = 8;
480 } else {
481 eeprom->word_size = 64;
482 eeprom->address_bits = 6;
483 }
484 }
485 eeprom->use_eerd = FALSE;
486 eeprom->use_eewr = FALSE;
487 break;
488 case e1000_82571:
489 case e1000_82572:
490 eeprom->type = e1000_eeprom_spi;
491 eeprom->opcode_bits = 8;
492 eeprom->delay_usec = 1;
493 if (eecd & E1000_EECD_ADDR_BITS) {
494 eeprom->page_size = 32;
495 eeprom->address_bits = 16;
496 } else {
497 eeprom->page_size = 8;
498 eeprom->address_bits = 8;
499 }
500 eeprom->use_eerd = FALSE;
501 eeprom->use_eewr = FALSE;
502 break;
503 case e1000_82573:
2c2668f9 504 case e1000_82574:
aa070789
RZ		 505 eeprom->type = e1000_eeprom_spi;
506 eeprom->opcode_bits = 8;
507 eeprom->delay_usec = 1;
508 if (eecd & E1000_EECD_ADDR_BITS) {
509 eeprom->page_size = 32;
510 eeprom->address_bits = 16;
511 } else {
512 eeprom->page_size = 8;
513 eeprom->address_bits = 8;
682011ff 514 }
aa070789
RZ		 515 eeprom->use_eerd = TRUE;
516 eeprom->use_eewr = TRUE;
517 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
518 eeprom->type = e1000_eeprom_flash;
519 eeprom->word_size = 2048;
520
521 /* Ensure that the Autonomous FLASH update bit is cleared due to
522 * Flash update issue on parts which use a FLASH for NVM. */
523 eecd &= ~E1000_EECD_AUPDEN;
682011ff 524 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 525 }
aa070789
RZ		 526 break;
527 case e1000_80003es2lan:
528 eeprom->type = e1000_eeprom_spi;
529 eeprom->opcode_bits = 8;
530 eeprom->delay_usec = 1;
531 if (eecd & E1000_EECD_ADDR_BITS) {
532 eeprom->page_size = 32;
533 eeprom->address_bits = 16;
534 } else {
535 eeprom->page_size = 8;
536 eeprom->address_bits = 8;
537 }
538 eeprom->use_eerd = TRUE;
539 eeprom->use_eewr = FALSE;
540 break;
682011ff 541
aa070789
RZ		 542 /* ich8lan does not support currently. if needed, please
543 * add corresponding code and functions.
544 */
545#if 0
546 case e1000_ich8lan:
547 {
548 int32_t i = 0;
549
550 eeprom->type = e1000_eeprom_ich8;
551 eeprom->use_eerd = FALSE;
552 eeprom->use_eewr = FALSE;
553 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
554 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
555 ICH_FLASH_GFPREG);
556 /* Zero the shadow RAM structure. But don't load it from NVM
557 * so as to save time for driver init */
558 if (hw->eeprom_shadow_ram != NULL) {
559 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
560 hw->eeprom_shadow_ram[i].modified = FALSE;
561 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
562 }
563 }
682011ff 564
aa070789
RZ		 565 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
566 ICH_FLASH_SECTOR_SIZE;
682011ff 567
aa070789
RZ		 568 hw->flash_bank_size = ((flash_size >> 16)
569 & ICH_GFPREG_BASE_MASK) + 1;
570 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
682011ff 571
aa070789 572 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
682011ff 573
aa070789
RZ		 574 hw->flash_bank_size /= 2 * sizeof(uint16_t);
575 break;
576 }
577#endif
578 default:
579 break;
682011ff
WD		 580 }
581
aa070789
RZ		 582 if (eeprom->type == e1000_eeprom_spi) {
583 /* eeprom_size will be an enum [0..8] that maps
584 * to eeprom sizes 128B to
585 * 32KB (incremented by powers of 2).
586 */
587 if (hw->mac_type <= e1000_82547_rev_2) {
588 /* Set to default value for initial eeprom read. */
589 eeprom->word_size = 64;
590 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
591 &eeprom_size);
592 if (ret_val)
593 return ret_val;
594 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
595 >> EEPROM_SIZE_SHIFT;
596 /* 256B eeprom size was not supported in earlier
597 * hardware, so we bump eeprom_size up one to
598 * ensure that "1" (which maps to 256B) is never
599 * the result used in the shifting logic below. */
600 if (eeprom_size)
601 eeprom_size++;
602 } else {
603 eeprom_size = (uint16_t)((eecd &
604 E1000_EECD_SIZE_EX_MASK) >>
605 E1000_EECD_SIZE_EX_SHIFT);
606 }
607
608 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
609 }
610 return ret_val;
682011ff
WD		 611}
612
aa070789
RZ		 613/******************************************************************************
614 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
615 *
616 * hw - Struct containing variables accessed by shared code
617 *****************************************************************************/
618static int32_t
619e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
682011ff 620{
aa070789
RZ		 621 uint32_t attempts = 100000;
622 uint32_t i, reg = 0;
623 int32_t done = E1000_ERR_EEPROM;
682011ff 624
aa070789
RZ		 625 for (i = 0; i < attempts; i++) {
626 if (eerd == E1000_EEPROM_POLL_READ)
627 reg = E1000_READ_REG(hw, EERD);
628 else
629 reg = E1000_READ_REG(hw, EEWR);
630
631 if (reg & E1000_EEPROM_RW_REG_DONE) {
632 done = E1000_SUCCESS;
633 break;
634 }
635 udelay(5);
636 }
637
638 return done;
682011ff
WD		 639}
640
aa070789
RZ		 641/******************************************************************************
642 * Reads a 16 bit word from the EEPROM using the EERD register.
643 *
644 * hw - Struct containing variables accessed by shared code
645 * offset - offset of word in the EEPROM to read
646 * data - word read from the EEPROM
647 * words - number of words to read
648 *****************************************************************************/
649static int32_t
650e1000_read_eeprom_eerd(struct e1000_hw *hw,
651 uint16_t offset,
652 uint16_t words,
653 uint16_t *data)
682011ff 654{
aa070789
RZ		 655 uint32_t i, eerd = 0;
656 int32_t error = 0;
657
658 for (i = 0; i < words; i++) {
659 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
660 E1000_EEPROM_RW_REG_START;
661
662 E1000_WRITE_REG(hw, EERD, eerd);
663 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
664
665 if (error)
666 break;
667 data[i] = (E1000_READ_REG(hw, EERD) >>
668 E1000_EEPROM_RW_REG_DATA);
682011ff 669
682011ff 670 }
aa070789
RZ		 671
672 return error;
682011ff
WD		 673}
674
aa070789
RZ		 675static void
676e1000_release_eeprom(struct e1000_hw *hw)
682011ff
WD		 677{
678 uint32_t eecd;
682011ff 679
aa070789
RZ		 680 DEBUGFUNC();
681
682 eecd = E1000_READ_REG(hw, EECD);
683
684 if (hw->eeprom.type == e1000_eeprom_spi) {
685 eecd |= E1000_EECD_CS; /* Pull CS high */
686 eecd &= ~E1000_EECD_SK; /* Lower SCK */
687
682011ff 688 E1000_WRITE_REG(hw, EECD, eecd);
aa070789
RZ		 689
690 udelay(hw->eeprom.delay_usec);
691 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
692 /* cleanup eeprom */
693
694 /* CS on Microwire is active-high */
695 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
696
697 E1000_WRITE_REG(hw, EECD, eecd);
698
699 /* Rising edge of clock */
700 eecd |= E1000_EECD_SK;
701 E1000_WRITE_REG(hw, EECD, eecd);
702 E1000_WRITE_FLUSH(hw);
703 udelay(hw->eeprom.delay_usec);
704
705 /* Falling edge of clock */
706 eecd &= ~E1000_EECD_SK;
707 E1000_WRITE_REG(hw, EECD, eecd);
708 E1000_WRITE_FLUSH(hw);
709 udelay(hw->eeprom.delay_usec);
682011ff 710 }
682011ff
WD		 711
712 /* Stop requesting EEPROM access */
713 if (hw->mac_type > e1000_82544) {
682011ff
WD		 714 eecd &= ~E1000_EECD_REQ;
715 E1000_WRITE_REG(hw, EECD, eecd);
716 }
682011ff 717}
682011ff 718/******************************************************************************
aa070789 719 * Reads a 16 bit word from the EEPROM.
8bde7f77 720 *
682011ff 721 * hw - Struct containing variables accessed by shared code
682011ff 722 *****************************************************************************/
aa070789
RZ		 723static int32_t
724e1000_spi_eeprom_ready(struct e1000_hw *hw)
682011ff 725{
aa070789
RZ		 726 uint16_t retry_count = 0;
727 uint8_t spi_stat_reg;
682011ff
WD		 728
729 DEBUGFUNC();
730
aa070789
RZ		 731 /* Read "Status Register" repeatedly until the LSB is cleared. The
732 * EEPROM will signal that the command has been completed by clearing
733 * bit 0 of the internal status register. If it's not cleared within
734 * 5 milliseconds, then error out.
735 */
736 retry_count = 0;
737 do {
738 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
739 hw->eeprom.opcode_bits);
740 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
741 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
742 break;
8bde7f77 743
aa070789
RZ		 744 udelay(5);
745 retry_count += 5;
746
747 e1000_standby_eeprom(hw);
748 } while (retry_count < EEPROM_MAX_RETRY_SPI);
749
750 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
751 * only 0-5mSec on 5V devices)
752 */
753 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
754 DEBUGOUT("SPI EEPROM Status error\n");
682011ff
WD		 755 return -E1000_ERR_EEPROM;
756 }
aa070789
RZ		 757
758 return E1000_SUCCESS;
682011ff
WD		 759}
760
761/******************************************************************************
aa070789 762 * Reads a 16 bit word from the EEPROM.
682011ff 763 *
aa070789
RZ		 764 * hw - Struct containing variables accessed by shared code
765 * offset - offset of word in the EEPROM to read
766 * data - word read from the EEPROM
682011ff 767 *****************************************************************************/
aa070789
RZ		 768static int32_t
769e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
770 uint16_t words, uint16_t *data)
682011ff 771{
aa070789
RZ		 772 struct e1000_eeprom_info *eeprom = &hw->eeprom;
773 uint32_t i = 0;
682011ff
WD		 774
775 DEBUGFUNC();
776
aa070789
RZ		 777 /* If eeprom is not yet detected, do so now */
778 if (eeprom->word_size == 0)
779 e1000_init_eeprom_params(hw);
780
781 /* A check for invalid values: offset too large, too many words,
782 * and not enough words.
783 */
784 if ((offset >= eeprom->word_size) ||
785 (words > eeprom->word_size - offset) ||
786 (words == 0)) {
787 DEBUGOUT("\"words\" parameter out of bounds."
788 "Words = %d, size = %d\n", offset, eeprom->word_size);
789 return -E1000_ERR_EEPROM;
790 }
791
792 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
793 * directly. In this case, we need to acquire the EEPROM so that
794 * FW or other port software does not interrupt.
795 */
796 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
797 hw->eeprom.use_eerd == FALSE) {
798
799 /* Prepare the EEPROM for bit-bang reading */
800 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
801 return -E1000_ERR_EEPROM;
802 }
803
804 /* Eerd register EEPROM access requires no eeprom aquire/release */
805 if (eeprom->use_eerd == TRUE)
806 return e1000_read_eeprom_eerd(hw, offset, words, data);
807
808 /* ich8lan does not support currently. if needed, please
809 * add corresponding code and functions.
810 */
811#if 0
812 /* ICH EEPROM access is done via the ICH flash controller */
813 if (eeprom->type == e1000_eeprom_ich8)
814 return e1000_read_eeprom_ich8(hw, offset, words, data);
815#endif
816 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
817 * acquired the EEPROM at this point, so any returns should relase it */
818 if (eeprom->type == e1000_eeprom_spi) {
819 uint16_t word_in;
820 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
821
822 if (e1000_spi_eeprom_ready(hw)) {
823 e1000_release_eeprom(hw);
824 return -E1000_ERR_EEPROM;
825 }
826
827 e1000_standby_eeprom(hw);
828
829 /* Some SPI eeproms use the 8th address bit embedded in
830 * the opcode */
831 if ((eeprom->address_bits == 8) && (offset >= 128))
832 read_opcode |= EEPROM_A8_OPCODE_SPI;
833
834 /* Send the READ command (opcode + addr) */
835 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
836 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
837 eeprom->address_bits);
838
839 /* Read the data. The address of the eeprom internally
840 * increments with each byte (spi) being read, saving on the
841 * overhead of eeprom setup and tear-down. The address
842 * counter will roll over if reading beyond the size of
843 * the eeprom, thus allowing the entire memory to be read
844 * starting from any offset. */
845 for (i = 0; i < words; i++) {
846 word_in = e1000_shift_in_ee_bits(hw, 16);
847 data[i] = (word_in >> 8) | (word_in << 8);
848 }
849 } else if (eeprom->type == e1000_eeprom_microwire) {
850 for (i = 0; i < words; i++) {
851 /* Send the READ command (opcode + addr) */
852 e1000_shift_out_ee_bits(hw,
853 EEPROM_READ_OPCODE_MICROWIRE,
854 eeprom->opcode_bits);
855 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
856 eeprom->address_bits);
857
858 /* Read the data. For microwire, each word requires
859 * the overhead of eeprom setup and tear-down. */
860 data[i] = e1000_shift_in_ee_bits(hw, 16);
861 e1000_standby_eeprom(hw);
862 }
863 }
864
865 /* End this read operation */
866 e1000_release_eeprom(hw);
867
868 return E1000_SUCCESS;
869}
870
871/******************************************************************************
872 * Verifies that the EEPROM has a valid checksum
873 *
874 * hw - Struct containing variables accessed by shared code
875 *
876 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
877 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
878 * valid.
879 *****************************************************************************/
880static int
881e1000_validate_eeprom_checksum(struct eth_device *nic)
882{
883 struct e1000_hw *hw = nic->priv;
884 uint16_t checksum = 0;
885 uint16_t i, eeprom_data;
886
887 DEBUGFUNC();
888
889 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
890 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
891 DEBUGOUT("EEPROM Read Error\n");
892 return -E1000_ERR_EEPROM;
893 }
894 checksum += eeprom_data;
895 }
896
897 if (checksum == (uint16_t) EEPROM_SUM) {
898 return 0;
899 } else {
900 DEBUGOUT("EEPROM Checksum Invalid\n");
901 return -E1000_ERR_EEPROM;
902 }
903}
ecbd2078
RZ		 904
905/*****************************************************************************
906 * Set PHY to class A mode
907 * Assumes the following operations will follow to enable the new class mode.
908 * 1. Do a PHY soft reset
909 * 2. Restart auto-negotiation or force link.
910 *
911 * hw - Struct containing variables accessed by shared code
912 ****************************************************************************/
913static int32_t
914e1000_set_phy_mode(struct e1000_hw *hw)
915{
916 int32_t ret_val;
917 uint16_t eeprom_data;
918
919 DEBUGFUNC();
920
921 if ((hw->mac_type == e1000_82545_rev_3) &&
922 (hw->media_type == e1000_media_type_copper)) {
923 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
924 1, &eeprom_data);
925 if (ret_val)
926 return ret_val;
927
928 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
929 (eeprom_data & EEPROM_PHY_CLASS_A)) {
930 ret_val = e1000_write_phy_reg(hw,
931 M88E1000_PHY_PAGE_SELECT, 0x000B);
932 if (ret_val)
933 return ret_val;
934 ret_val = e1000_write_phy_reg(hw,
935 M88E1000_PHY_GEN_CONTROL, 0x8104);
936 if (ret_val)
937 return ret_val;
938
939 hw->phy_reset_disable = FALSE;
940 }
941 }
942
943 return E1000_SUCCESS;
944}
aa070789
RZ		 945#endif /* #ifndef CONFIG_AP1000 */
946
947/***************************************************************************
948 *
949 * Obtaining software semaphore bit (SMBI) before resetting PHY.
950 *
951 * hw: Struct containing variables accessed by shared code
952 *
953 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
954 * E1000_SUCCESS at any other case.
955 *
956 ***************************************************************************/
957static int32_t
958e1000_get_software_semaphore(struct e1000_hw *hw)
959{
960 int32_t timeout = hw->eeprom.word_size + 1;
961 uint32_t swsm;
962
963 DEBUGFUNC();
964
965 if (hw->mac_type != e1000_80003es2lan)
966 return E1000_SUCCESS;
967
968 while (timeout) {
969 swsm = E1000_READ_REG(hw, SWSM);
970 /* If SMBI bit cleared, it is now set and we hold
971 * the semaphore */
972 if (!(swsm & E1000_SWSM_SMBI))
973 break;
974 mdelay(1);
975 timeout--;
976 }
977
978 if (!timeout) {
979 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
980 return -E1000_ERR_RESET;
981 }
982
983 return E1000_SUCCESS;
984}
985
986/***************************************************************************
987 * This function clears HW semaphore bits.
988 *
989 * hw: Struct containing variables accessed by shared code
990 *
991 * returns: - None.
992 *
993 ***************************************************************************/
994static void
995e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
996{
997 uint32_t swsm;
998
999 DEBUGFUNC();
1000
1001 if (!hw->eeprom_semaphore_present)
1002 return;
1003
1004 swsm = E1000_READ_REG(hw, SWSM);
1005 if (hw->mac_type == e1000_80003es2lan) {
1006 /* Release both semaphores. */
1007 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1008 } else
1009 swsm &= ~(E1000_SWSM_SWESMBI);
1010 E1000_WRITE_REG(hw, SWSM, swsm);
1011}
1012
1013/***************************************************************************
1014 *
1015 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1016 * adapter or Eeprom access.
1017 *
1018 * hw: Struct containing variables accessed by shared code
1019 *
1020 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1021 * E1000_SUCCESS at any other case.
1022 *
1023 ***************************************************************************/
1024static int32_t
1025e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1026{
1027 int32_t timeout;
1028 uint32_t swsm;
1029
1030 DEBUGFUNC();
1031
1032 if (!hw->eeprom_semaphore_present)
1033 return E1000_SUCCESS;
1034
1035 if (hw->mac_type == e1000_80003es2lan) {
1036 /* Get the SW semaphore. */
1037 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1038 return -E1000_ERR_EEPROM;
1039 }
1040
1041 /* Get the FW semaphore. */
1042 timeout = hw->eeprom.word_size + 1;
1043 while (timeout) {
1044 swsm = E1000_READ_REG(hw, SWSM);
1045 swsm |= E1000_SWSM_SWESMBI;
1046 E1000_WRITE_REG(hw, SWSM, swsm);
1047 /* if we managed to set the bit we got the semaphore. */
1048 swsm = E1000_READ_REG(hw, SWSM);
1049 if (swsm & E1000_SWSM_SWESMBI)
1050 break;
1051
1052 udelay(50);
1053 timeout--;
1054 }
1055
1056 if (!timeout) {
1057 /* Release semaphores */
1058 e1000_put_hw_eeprom_semaphore(hw);
1059 DEBUGOUT("Driver can't access the Eeprom - "
1060 "SWESMBI bit is set.\n");
1061 return -E1000_ERR_EEPROM;
1062 }
1063
1064 return E1000_SUCCESS;
1065}
1066
1067static int32_t
1068e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1069{
1070 uint32_t swfw_sync = 0;
1071 uint32_t swmask = mask;
1072 uint32_t fwmask = mask << 16;
1073 int32_t timeout = 200;
1074
1075 DEBUGFUNC();
1076 while (timeout) {
1077 if (e1000_get_hw_eeprom_semaphore(hw))
1078 return -E1000_ERR_SWFW_SYNC;
1079
1080 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1081 if (!(swfw_sync & (fwmask | swmask)))
1082 break;
1083
1084 /* firmware currently using resource (fwmask) */
1085 /* or other software thread currently using resource (swmask) */
1086 e1000_put_hw_eeprom_semaphore(hw);
1087 mdelay(5);
1088 timeout--;
1089 }
1090
1091 if (!timeout) {
1092 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1093 return -E1000_ERR_SWFW_SYNC;
1094 }
1095
1096 swfw_sync |= swmask;
1097 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1098
1099 e1000_put_hw_eeprom_semaphore(hw);
1100 return E1000_SUCCESS;
1101}
1102
1103/******************************************************************************
1104 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1105 * second function of dual function devices
1106 *
1107 * nic - Struct containing variables accessed by shared code
1108 *****************************************************************************/
1109static int
1110e1000_read_mac_addr(struct eth_device *nic)
1111{
1112#ifndef CONFIG_AP1000
1113 struct e1000_hw *hw = nic->priv;
1114 uint16_t offset;
1115 uint16_t eeprom_data;
1116 int i;
1117
1118 DEBUGFUNC();
1119
1120 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1121 offset = i >> 1;
1122 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
682011ff
WD		 1123 DEBUGOUT("EEPROM Read Error\n");
1124 return -E1000_ERR_EEPROM;
1125 }
1126 nic->enetaddr[i] = eeprom_data & 0xff;
1127 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1128 }
1129 if ((hw->mac_type == e1000_82546) &&
1130 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
1131 /* Invert the last bit if this is the second device */
1132 nic->enetaddr[5] += 1;
1133 }
ac3315c2 1134#ifdef CONFIG_E1000_FALLBACK_MAC
f2302d44
SR		 1135 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1136 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1137
1138 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1139 }
ac3315c2 1140#endif
7521af1c
WD		 1141#else
1142 /*
1143 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1144 * environment variables. Currently this does not support the addition
1145 * of a PMC e1000 card, which is certainly a possibility, so this should
1146 * be updated to properly use the env variable only for the onboard e1000
1147 */
1148
1149 int ii;
1150 char *s, *e;
1151
1152 DEBUGFUNC();
1153
1154 s = getenv ("ethaddr");
f2302d44 1155 if (s == NULL) {
7521af1c 1156 return -E1000_ERR_EEPROM;
f2302d44 1157 } else {
7521af1c
WD		 1158 for(ii = 0; ii < 6; ii++) {
1159 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1160 if (s){
1161 s = (*e) ? e + 1 : e;
1162 }
1163 }
1164 }
1165#endif
682011ff
WD		 1166 return 0;
1167}
1168
1169/******************************************************************************
1170 * Initializes receive address filters.
1171 *
8bde7f77 1172 * hw - Struct containing variables accessed by shared code
682011ff
WD		 1173 *
1174 * Places the MAC address in receive address register 0 and clears the rest
1175 * of the receive addresss registers. Clears the multicast table. Assumes
1176 * the receiver is in reset when the routine is called.
1177 *****************************************************************************/
1178static void
1179e1000_init_rx_addrs(struct eth_device *nic)
1180{
1181 struct e1000_hw *hw = nic->priv;
1182 uint32_t i;
1183 uint32_t addr_low;
1184 uint32_t addr_high;
1185
1186 DEBUGFUNC();
1187
1188 /* Setup the receive address. */
1189 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1190 addr_low = (nic->enetaddr[0] |
1191 (nic->enetaddr[1] << 8) |
1192 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1193
1194 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1195
1196 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1197 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1198
1199 /* Zero out the other 15 receive addresses. */
1200 DEBUGOUT("Clearing RAR[1-15]\n");
1201 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1202 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1203 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1204 }
1205}
1206
1207/******************************************************************************
1208 * Clears the VLAN filer table
1209 *
1210 * hw - Struct containing variables accessed by shared code
1211 *****************************************************************************/
1212static void
1213e1000_clear_vfta(struct e1000_hw *hw)
1214{
1215 uint32_t offset;
1216
1217 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1218 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1219}
1220
1221/******************************************************************************
1222 * Set the mac type member in the hw struct.
8bde7f77 1223 *
682011ff
WD		 1224 * hw - Struct containing variables accessed by shared code
1225 *****************************************************************************/
aa070789 1226int32_t
682011ff
WD		 1227e1000_set_mac_type(struct e1000_hw *hw)
1228{
1229 DEBUGFUNC();
1230
1231 switch (hw->device_id) {
1232 case E1000_DEV_ID_82542:
1233 switch (hw->revision_id) {
1234 case E1000_82542_2_0_REV_ID:
1235 hw->mac_type = e1000_82542_rev2_0;
1236 break;
1237 case E1000_82542_2_1_REV_ID:
1238 hw->mac_type = e1000_82542_rev2_1;
1239 break;
1240 default:
1241 /* Invalid 82542 revision ID */
1242 return -E1000_ERR_MAC_TYPE;
1243 }
1244 break;
1245 case E1000_DEV_ID_82543GC_FIBER:
1246 case E1000_DEV_ID_82543GC_COPPER:
1247 hw->mac_type = e1000_82543;
1248 break;
1249 case E1000_DEV_ID_82544EI_COPPER:
1250 case E1000_DEV_ID_82544EI_FIBER:
1251 case E1000_DEV_ID_82544GC_COPPER:
1252 case E1000_DEV_ID_82544GC_LOM:
1253 hw->mac_type = e1000_82544;
1254 break;
1255 case E1000_DEV_ID_82540EM:
1256 case E1000_DEV_ID_82540EM_LOM:
aa070789
RZ		 1257 case E1000_DEV_ID_82540EP:
1258 case E1000_DEV_ID_82540EP_LOM:
1259 case E1000_DEV_ID_82540EP_LP:
682011ff
WD		 1260 hw->mac_type = e1000_82540;
1261 break;
1262 case E1000_DEV_ID_82545EM_COPPER:
1263 case E1000_DEV_ID_82545EM_FIBER:
1264 hw->mac_type = e1000_82545;
1265 break;
aa070789
RZ		 1266 case E1000_DEV_ID_82545GM_COPPER:
1267 case E1000_DEV_ID_82545GM_FIBER:
1268 case E1000_DEV_ID_82545GM_SERDES:
1269 hw->mac_type = e1000_82545_rev_3;
1270 break;
682011ff
WD		 1271 case E1000_DEV_ID_82546EB_COPPER:
1272 case E1000_DEV_ID_82546EB_FIBER:
aa070789 1273 case E1000_DEV_ID_82546EB_QUAD_COPPER:
682011ff
WD		 1274 hw->mac_type = e1000_82546;
1275 break;
aa070789
RZ		 1276 case E1000_DEV_ID_82546GB_COPPER:
1277 case E1000_DEV_ID_82546GB_FIBER:
1278 case E1000_DEV_ID_82546GB_SERDES:
1279 case E1000_DEV_ID_82546GB_PCIE:
1280 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1281 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1282 hw->mac_type = e1000_82546_rev_3;
1283 break;
1284 case E1000_DEV_ID_82541EI:
1285 case E1000_DEV_ID_82541EI_MOBILE:
1286 case E1000_DEV_ID_82541ER_LOM:
1287 hw->mac_type = e1000_82541;
1288 break;
ac3315c2 1289 case E1000_DEV_ID_82541ER:
aa070789 1290 case E1000_DEV_ID_82541GI:
aa3b8bf9 1291 case E1000_DEV_ID_82541GI_LF:
aa070789 1292 case E1000_DEV_ID_82541GI_MOBILE:
1aeed8d7
WD		 1293 hw->mac_type = e1000_82541_rev_2;
1294 break;
aa070789
RZ		 1295 case E1000_DEV_ID_82547EI:
1296 case E1000_DEV_ID_82547EI_MOBILE:
1297 hw->mac_type = e1000_82547;
1298 break;
1299 case E1000_DEV_ID_82547GI:
1300 hw->mac_type = e1000_82547_rev_2;
1301 break;
1302 case E1000_DEV_ID_82571EB_COPPER:
1303 case E1000_DEV_ID_82571EB_FIBER:
1304 case E1000_DEV_ID_82571EB_SERDES:
1305 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1306 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1307 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1308 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1309 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1310 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1311 hw->mac_type = e1000_82571;
1312 break;
1313 case E1000_DEV_ID_82572EI_COPPER:
1314 case E1000_DEV_ID_82572EI_FIBER:
1315 case E1000_DEV_ID_82572EI_SERDES:
1316 case E1000_DEV_ID_82572EI:
1317 hw->mac_type = e1000_82572;
1318 break;
1319 case E1000_DEV_ID_82573E:
1320 case E1000_DEV_ID_82573E_IAMT:
1321 case E1000_DEV_ID_82573L:
1322 hw->mac_type = e1000_82573;
1323 break;
2c2668f9
RZ		 1324 case E1000_DEV_ID_82574L:
1325 hw->mac_type = e1000_82574;
1326 break;
aa070789
RZ		 1327 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1328 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1329 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1330 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1331 hw->mac_type = e1000_80003es2lan;
1332 break;
1333 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1334 case E1000_DEV_ID_ICH8_IGP_AMT:
1335 case E1000_DEV_ID_ICH8_IGP_C:
1336 case E1000_DEV_ID_ICH8_IFE:
1337 case E1000_DEV_ID_ICH8_IFE_GT:
1338 case E1000_DEV_ID_ICH8_IFE_G:
1339 case E1000_DEV_ID_ICH8_IGP_M:
1340 hw->mac_type = e1000_ich8lan;
1341 break;
682011ff
WD		 1342 default:
1343 /* Should never have loaded on this device */
1344 return -E1000_ERR_MAC_TYPE;
1345 }
1346 return E1000_SUCCESS;
1347}
1348
1349/******************************************************************************
1350 * Reset the transmit and receive units; mask and clear all interrupts.
1351 *
1352 * hw - Struct containing variables accessed by shared code
1353 *****************************************************************************/
1354void
1355e1000_reset_hw(struct e1000_hw *hw)
1356{
1357 uint32_t ctrl;
1358 uint32_t ctrl_ext;
1359 uint32_t icr;
1360 uint32_t manc;
9ea005fb 1361 uint32_t pba = 0;
682011ff
WD		 1362
1363 DEBUGFUNC();
1364
9ea005fb
RZ		 1365 /* get the correct pba value for both PCI and PCIe*/
1366 if (hw->mac_type < e1000_82571)
1367 pba = E1000_DEFAULT_PCI_PBA;
1368 else
1369 pba = E1000_DEFAULT_PCIE_PBA;
1370
682011ff
WD		 1371 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1372 if (hw->mac_type == e1000_82542_rev2_0) {
1373 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1374 pci_write_config_word(hw->pdev, PCI_COMMAND,
aa070789 1375 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
682011ff
WD		 1376 }
1377
1378 /* Clear interrupt mask to stop board from generating interrupts */
1379 DEBUGOUT("Masking off all interrupts\n");
1380 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1381
1382 /* Disable the Transmit and Receive units. Then delay to allow
1383 * any pending transactions to complete before we hit the MAC with
1384 * the global reset.
1385 */
1386 E1000_WRITE_REG(hw, RCTL, 0);
1387 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1388 E1000_WRITE_FLUSH(hw);
1389
1390 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1391 hw->tbi_compatibility_on = FALSE;
1392
1393 /* Delay to allow any outstanding PCI transactions to complete before
1394 * resetting the device
1395 */
1396 mdelay(10);
1397
1398 /* Issue a global reset to the MAC. This will reset the chip's
1399 * transmit, receive, DMA, and link units. It will not effect
1400 * the current PCI configuration. The global reset bit is self-
1401 * clearing, and should clear within a microsecond.
1402 */
1403 DEBUGOUT("Issuing a global reset to MAC\n");
1404 ctrl = E1000_READ_REG(hw, CTRL);
1405
aa070789 1406 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
682011ff
WD		 1407
1408 /* Force a reload from the EEPROM if necessary */
1409 if (hw->mac_type < e1000_82540) {
1410 /* Wait for reset to complete */
1411 udelay(10);
1412 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1413 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1414 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1415 E1000_WRITE_FLUSH(hw);
1416 /* Wait for EEPROM reload */
1417 mdelay(2);
1418 } else {
1419 /* Wait for EEPROM reload (it happens automatically) */
1420 mdelay(4);
1421 /* Dissable HW ARPs on ASF enabled adapters */
1422 manc = E1000_READ_REG(hw, MANC);
1423 manc &= ~(E1000_MANC_ARP_EN);
1424 E1000_WRITE_REG(hw, MANC, manc);
1425 }
1426
1427 /* Clear interrupt mask to stop board from generating interrupts */
1428 DEBUGOUT("Masking off all interrupts\n");
1429 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1430
1431 /* Clear any pending interrupt events. */
1432 icr = E1000_READ_REG(hw, ICR);
1433
1434 /* If MWI was previously enabled, reenable it. */
1435 if (hw->mac_type == e1000_82542_rev2_0) {
1436 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1437 }
9ea005fb 1438 E1000_WRITE_REG(hw, PBA, pba);
aa070789
RZ		 1439}
1440
1441/******************************************************************************
1442 *
1443 * Initialize a number of hardware-dependent bits
1444 *
1445 * hw: Struct containing variables accessed by shared code
1446 *
1447 * This function contains hardware limitation workarounds for PCI-E adapters
1448 *
1449 *****************************************************************************/
1450static void
1451e1000_initialize_hardware_bits(struct e1000_hw *hw)
1452{
1453 if ((hw->mac_type >= e1000_82571) &&
1454 (!hw->initialize_hw_bits_disable)) {
1455 /* Settings common to all PCI-express silicon */
1456 uint32_t reg_ctrl, reg_ctrl_ext;
1457 uint32_t reg_tarc0, reg_tarc1;
1458 uint32_t reg_tctl;
1459 uint32_t reg_txdctl, reg_txdctl1;
1460
1461 /* link autonegotiation/sync workarounds */
1462 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1463 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1464
1465 /* Enable not-done TX descriptor counting */
1466 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1467 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1468 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1469
1470 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1471 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1472 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1473
1474 switch (hw->mac_type) {
1475 case e1000_82571:
1476 case e1000_82572:
1477 /* Clear PHY TX compatible mode bits */
1478 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1479 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1480
1481 /* link autonegotiation/sync workarounds */
1482 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1483
1484 /* TX ring control fixes */
1485 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1486
1487 /* Multiple read bit is reversed polarity */
1488 reg_tctl = E1000_READ_REG(hw, TCTL);
1489 if (reg_tctl & E1000_TCTL_MULR)
1490 reg_tarc1 &= ~(1 << 28);
1491 else
1492 reg_tarc1 |= (1 << 28);
1493
1494 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1495 break;
1496 case e1000_82573:
2c2668f9 1497 case e1000_82574:
aa070789
RZ		 1498 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1499 reg_ctrl_ext &= ~(1 << 23);
1500 reg_ctrl_ext |= (1 << 22);
1501
1502 /* TX byte count fix */
1503 reg_ctrl = E1000_READ_REG(hw, CTRL);
1504 reg_ctrl &= ~(1 << 29);
1505
1506 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1507 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1508 break;
1509 case e1000_80003es2lan:
1510 /* improve small packet performace for fiber/serdes */
1511 if ((hw->media_type == e1000_media_type_fiber)
1512 || (hw->media_type ==
1513 e1000_media_type_internal_serdes)) {
1514 reg_tarc0 &= ~(1 << 20);
1515 }
1516
1517 /* Multiple read bit is reversed polarity */
1518 reg_tctl = E1000_READ_REG(hw, TCTL);
1519 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1520 if (reg_tctl & E1000_TCTL_MULR)
1521 reg_tarc1 &= ~(1 << 28);
1522 else
1523 reg_tarc1 |= (1 << 28);
1524
1525 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1526 break;
1527 case e1000_ich8lan:
1528 /* Reduce concurrent DMA requests to 3 from 4 */
1529 if ((hw->revision_id < 3) ||
1530 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1531 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1532 reg_tarc0 |= ((1 << 29)|(1 << 28));
1533
1534 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1535 reg_ctrl_ext |= (1 << 22);
1536 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1537
1538 /* workaround TX hang with TSO=on */
1539 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1540
1541 /* Multiple read bit is reversed polarity */
1542 reg_tctl = E1000_READ_REG(hw, TCTL);
1543 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1544 if (reg_tctl & E1000_TCTL_MULR)
1545 reg_tarc1 &= ~(1 << 28);
1546 else
1547 reg_tarc1 |= (1 << 28);
1548
1549 /* workaround TX hang with TSO=on */
1550 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1551
1552 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1553 break;
1554 default:
1555 break;
1556 }
1557
1558 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1559 }
682011ff
WD		 1560}
1561
1562/******************************************************************************
1563 * Performs basic configuration of the adapter.
1564 *
1565 * hw - Struct containing variables accessed by shared code
8bde7f77
WD		 1566 *
1567 * Assumes that the controller has previously been reset and is in a
682011ff
WD		 1568 * post-reset uninitialized state. Initializes the receive address registers,
1569 * multicast table, and VLAN filter table. Calls routines to setup link
1570 * configuration and flow control settings. Clears all on-chip counters. Leaves
1571 * the transmit and receive units disabled and uninitialized.
1572 *****************************************************************************/
1573static int
1574e1000_init_hw(struct eth_device *nic)
1575{
1576 struct e1000_hw *hw = nic->priv;
aa070789 1577 uint32_t ctrl;
682011ff
WD		 1578 uint32_t i;
1579 int32_t ret_val;
1580 uint16_t pcix_cmd_word;
1581 uint16_t pcix_stat_hi_word;
1582 uint16_t cmd_mmrbc;
1583 uint16_t stat_mmrbc;
aa070789
RZ		 1584 uint32_t mta_size;
1585 uint32_t reg_data;
1586 uint32_t ctrl_ext;
682011ff 1587 DEBUGFUNC();
aa070789
RZ		 1588 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1589 if ((hw->mac_type == e1000_ich8lan) &&
1590 ((hw->revision_id < 3) ||
1591 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1592 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1593 reg_data = E1000_READ_REG(hw, STATUS);
1594 reg_data &= ~0x80000000;
1595 E1000_WRITE_REG(hw, STATUS, reg_data);
682011ff 1596 }
aa070789 1597 /* Do not need initialize Identification LED */
682011ff 1598
aa070789
RZ		 1599 /* Set the media type and TBI compatibility */
1600 e1000_set_media_type(hw);
1601
1602 /* Must be called after e1000_set_media_type
1603 * because media_type is used */
1604 e1000_initialize_hardware_bits(hw);
682011ff
WD		 1605
1606 /* Disabling VLAN filtering. */
1607 DEBUGOUT("Initializing the IEEE VLAN\n");
aa070789
RZ		 1608 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1609 if (hw->mac_type != e1000_ich8lan) {
1610 if (hw->mac_type < e1000_82545_rev_3)
1611 E1000_WRITE_REG(hw, VET, 0);
1612 e1000_clear_vfta(hw);
1613 }
682011ff
WD		 1614
1615 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1616 if (hw->mac_type == e1000_82542_rev2_0) {
1617 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1618 pci_write_config_word(hw->pdev, PCI_COMMAND,
1619 hw->
1620 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1621 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1622 E1000_WRITE_FLUSH(hw);
1623 mdelay(5);
1624 }
1625
1626 /* Setup the receive address. This involves initializing all of the Receive
1627 * Address Registers (RARs 0 - 15).
1628 */
1629 e1000_init_rx_addrs(nic);
1630
1631 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1632 if (hw->mac_type == e1000_82542_rev2_0) {
1633 E1000_WRITE_REG(hw, RCTL, 0);
1634 E1000_WRITE_FLUSH(hw);
1635 mdelay(1);
1636 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1637 }
1638
1639 /* Zero out the Multicast HASH table */
1640 DEBUGOUT("Zeroing the MTA\n");
aa070789
RZ		 1641 mta_size = E1000_MC_TBL_SIZE;
1642 if (hw->mac_type == e1000_ich8lan)
1643 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1644 for (i = 0; i < mta_size; i++) {
682011ff 1645 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
aa070789
RZ		 1646 /* use write flush to prevent Memory Write Block (MWB) from
1647 * occuring when accessing our register space */
1648 E1000_WRITE_FLUSH(hw);
1649 }
682011ff
WD		 1650#if 0
1651 /* Set the PCI priority bit correctly in the CTRL register. This
1652 * determines if the adapter gives priority to receives, or if it
aa070789
RZ		 1653 * gives equal priority to transmits and receives. Valid only on
1654 * 82542 and 82543 silicon.
682011ff 1655 */
aa070789 1656 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
682011ff
WD		 1657 ctrl = E1000_READ_REG(hw, CTRL);
1658 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1659 }
1660#endif
aa070789
RZ		 1661 switch (hw->mac_type) {
1662 case e1000_82545_rev_3:
1663 case e1000_82546_rev_3:
1664 break;
1665 default:
682011ff 1666 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
aa070789 1667 if (hw->bus_type == e1000_bus_type_pcix) {
682011ff
WD		 1668 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1669 &pcix_cmd_word);
1670 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1671 &pcix_stat_hi_word);
1672 cmd_mmrbc =
1673 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1674 PCIX_COMMAND_MMRBC_SHIFT;
1675 stat_mmrbc =
1676 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1677 PCIX_STATUS_HI_MMRBC_SHIFT;
1678 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1679 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1680 if (cmd_mmrbc > stat_mmrbc) {
1681 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1682 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1683 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1684 pcix_cmd_word);
1685 }
1686 }
aa070789
RZ		 1687 break;
1688 }
1689
1690 /* More time needed for PHY to initialize */
1691 if (hw->mac_type == e1000_ich8lan)
1692 mdelay(15);
682011ff
WD		 1693
1694 /* Call a subroutine to configure the link and setup flow control. */
1695 ret_val = e1000_setup_link(nic);
1696
1697 /* Set the transmit descriptor write-back policy */
1698 if (hw->mac_type > e1000_82544) {
1699 ctrl = E1000_READ_REG(hw, TXDCTL);
1700 ctrl =
1701 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1702 E1000_TXDCTL_FULL_TX_DESC_WB;
1703 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1704 }
aa070789
RZ		 1705
1706 switch (hw->mac_type) {
1707 default:
1708 break;
1709 case e1000_80003es2lan:
1710 /* Enable retransmit on late collisions */
1711 reg_data = E1000_READ_REG(hw, TCTL);
1712 reg_data |= E1000_TCTL_RTLC;
1713 E1000_WRITE_REG(hw, TCTL, reg_data);
1714
1715 /* Configure Gigabit Carry Extend Padding */
1716 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1717 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1718 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1719 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1720
1721 /* Configure Transmit Inter-Packet Gap */
1722 reg_data = E1000_READ_REG(hw, TIPG);
1723 reg_data &= ~E1000_TIPG_IPGT_MASK;
1724 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1725 E1000_WRITE_REG(hw, TIPG, reg_data);
1726
1727 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1728 reg_data &= ~0x00100000;
1729 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1730 /* Fall through */
1731 case e1000_82571:
1732 case e1000_82572:
1733 case e1000_ich8lan:
1734 ctrl = E1000_READ_REG(hw, TXDCTL1);
1735 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1736 | E1000_TXDCTL_FULL_TX_DESC_WB;
1737 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1738 break;
2c2668f9
RZ		 1739 case e1000_82573:
1740 case e1000_82574:
1741 reg_data = E1000_READ_REG(hw, GCR);
1742 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1743 E1000_WRITE_REG(hw, GCR, reg_data);
aa070789
RZ		 1744 }
1745
682011ff
WD		 1746#if 0
1747 /* Clear all of the statistics registers (clear on read). It is
1748 * important that we do this after we have tried to establish link
1749 * because the symbol error count will increment wildly if there
1750 * is no link.
1751 */
1752 e1000_clear_hw_cntrs(hw);
aa070789
RZ		 1753
1754 /* ICH8 No-snoop bits are opposite polarity.
1755 * Set to snoop by default after reset. */
1756 if (hw->mac_type == e1000_ich8lan)
1757 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
682011ff
WD		 1758#endif
1759
aa070789
RZ		 1760 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1761 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1762 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1763 /* Relaxed ordering must be disabled to avoid a parity
1764 * error crash in a PCI slot. */
1765 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1766 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1767 }
1768
682011ff
WD		 1769 return ret_val;
1770}
1771
1772/******************************************************************************
1773 * Configures flow control and link settings.
8bde7f77 1774 *
682011ff 1775 * hw - Struct containing variables accessed by shared code
8bde7f77 1776 *
682011ff
WD		 1777 * Determines which flow control settings to use. Calls the apropriate media-
1778 * specific link configuration function. Configures the flow control settings.
1779 * Assuming the adapter has a valid link partner, a valid link should be
8bde7f77 1780 * established. Assumes the hardware has previously been reset and the
682011ff
WD		 1781 * transmitter and receiver are not enabled.
1782 *****************************************************************************/
1783static int
1784e1000_setup_link(struct eth_device *nic)
1785{
1786 struct e1000_hw *hw = nic->priv;
1787 uint32_t ctrl_ext;
1788 int32_t ret_val;
1789 uint16_t eeprom_data;
1790
1791 DEBUGFUNC();
1792
aa070789
RZ		 1793 /* In the case of the phy reset being blocked, we already have a link.
1794 * We do not have to set it up again. */
1795 if (e1000_check_phy_reset_block(hw))
1796 return E1000_SUCCESS;
1797
7521af1c 1798#ifndef CONFIG_AP1000
682011ff
WD		 1799 /* Read and store word 0x0F of the EEPROM. This word contains bits
1800 * that determine the hardware's default PAUSE (flow control) mode,
1801 * a bit that determines whether the HW defaults to enabling or
1802 * disabling auto-negotiation, and the direction of the
1803 * SW defined pins. If there is no SW over-ride of the flow
1804 * control setting, then the variable hw->fc will
1805 * be initialized based on a value in the EEPROM.
1806 */
aa070789
RZ		 1807 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1808 &eeprom_data) < 0) {
682011ff
WD		 1809 DEBUGOUT("EEPROM Read Error\n");
1810 return -E1000_ERR_EEPROM;
1811 }
7521af1c
WD		 1812#else
1813 /* we have to hardcode the proper value for our hardware. */
1814 /* this value is for the 82540EM pci card used for prototyping, and it works. */
1815 eeprom_data = 0xb220;
1816#endif
682011ff
WD		 1817
1818 if (hw->fc == e1000_fc_default) {
aa070789
RZ		 1819 switch (hw->mac_type) {
1820 case e1000_ich8lan:
1821 case e1000_82573:
2c2668f9 1822 case e1000_82574:
682011ff 1823 hw->fc = e1000_fc_full;
aa070789
RZ		 1824 break;
1825 default:
1826#ifndef CONFIG_AP1000
1827 ret_val = e1000_read_eeprom(hw,
1828 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1829 if (ret_val) {
1830 DEBUGOUT("EEPROM Read Error\n");
1831 return -E1000_ERR_EEPROM;
1832 }
1833#else
1834 eeprom_data = 0xb220;
1835#endif
1836 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1837 hw->fc = e1000_fc_none;
1838 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1839 EEPROM_WORD0F_ASM_DIR)
1840 hw->fc = e1000_fc_tx_pause;
1841 else
1842 hw->fc = e1000_fc_full;
1843 break;
1844 }
682011ff
WD		 1845 }
1846
1847 /* We want to save off the original Flow Control configuration just
1848 * in case we get disconnected and then reconnected into a different
1849 * hub or switch with different Flow Control capabilities.
1850 */
1851 if (hw->mac_type == e1000_82542_rev2_0)
1852 hw->fc &= (~e1000_fc_tx_pause);
1853
1854 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1855 hw->fc &= (~e1000_fc_rx_pause);
1856
1857 hw->original_fc = hw->fc;
1858
1859 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1860
1861 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1862 * polarity value for the SW controlled pins, and setup the
1863 * Extended Device Control reg with that info.
1864 * This is needed because one of the SW controlled pins is used for
1865 * signal detection. So this should be done before e1000_setup_pcs_link()
1866 * or e1000_phy_setup() is called.
1867 */
1868 if (hw->mac_type == e1000_82543) {
1869 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1870 SWDPIO__EXT_SHIFT);
1871 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1872 }
1873
1874 /* Call the necessary subroutine to configure the link. */
1875 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1876 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1877 if (ret_val < 0) {
1878 return ret_val;
1879 }
1880
1881 /* Initialize the flow control address, type, and PAUSE timer
1882 * registers to their default values. This is done even if flow
1883 * control is disabled, because it does not hurt anything to
1884 * initialize these registers.
1885 */
aa070789
RZ		 1886 DEBUGOUT("Initializing the Flow Control address, type"
1887 "and timer regs\n");
1888
1889 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1890 if (hw->mac_type != e1000_ich8lan) {
1891 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1892 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1893 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1894 }
682011ff 1895
682011ff
WD		 1896 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1897
1898 /* Set the flow control receive threshold registers. Normally,
1899 * these registers will be set to a default threshold that may be
1900 * adjusted later by the driver's runtime code. However, if the
1901 * ability to transmit pause frames in not enabled, then these
8bde7f77 1902 * registers will be set to 0.
682011ff
WD		 1903 */
1904 if (!(hw->fc & e1000_fc_tx_pause)) {
1905 E1000_WRITE_REG(hw, FCRTL, 0);
1906 E1000_WRITE_REG(hw, FCRTH, 0);
1907 } else {
1908 /* We need to set up the Receive Threshold high and low water marks
1909 * as well as (optionally) enabling the transmission of XON frames.
1910 */
1911 if (hw->fc_send_xon) {
1912 E1000_WRITE_REG(hw, FCRTL,
1913 (hw->fc_low_water | E1000_FCRTL_XONE));
1914 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1915 } else {
1916 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1917 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1918 }
1919 }
1920 return ret_val;
1921}
1922
1923/******************************************************************************
1924 * Sets up link for a fiber based adapter
1925 *
1926 * hw - Struct containing variables accessed by shared code
1927 *
1928 * Manipulates Physical Coding Sublayer functions in order to configure
1929 * link. Assumes the hardware has been previously reset and the transmitter
1930 * and receiver are not enabled.
1931 *****************************************************************************/
1932static int
1933e1000_setup_fiber_link(struct eth_device *nic)
1934{
1935 struct e1000_hw *hw = nic->priv;
1936 uint32_t ctrl;
1937 uint32_t status;
1938 uint32_t txcw = 0;
1939 uint32_t i;
1940 uint32_t signal;
1941 int32_t ret_val;
1942
1943 DEBUGFUNC();
8bde7f77
WD		 1944 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1945 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 1946 * cleared when there is a signal
1947 */
1948 ctrl = E1000_READ_REG(hw, CTRL);
1949 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1950 signal = E1000_CTRL_SWDPIN1;
1951 else
1952 signal = 0;
1953
1954 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1955 ctrl);
1956 /* Take the link out of reset */
1957 ctrl &= ~(E1000_CTRL_LRST);
1958
1959 e1000_config_collision_dist(hw);
1960
1961 /* Check for a software override of the flow control settings, and setup
1962 * the device accordingly. If auto-negotiation is enabled, then software
1963 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1964 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
8bde7f77 1965 * auto-negotiation is disabled, then software will have to manually
682011ff
WD		 1966 * configure the two flow control enable bits in the CTRL register.
1967 *
1968 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 1969 * 0: Flow control is completely disabled
1970 * 1: Rx flow control is enabled (we can receive pause frames, but
1971 * not send pause frames).
1972 * 2: Tx flow control is enabled (we can send pause frames but we do
1973 * not support receiving pause frames).
1974 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff
WD		 1975 */
1976 switch (hw->fc) {
1977 case e1000_fc_none:
1978 /* Flow control is completely disabled by a software over-ride. */
1979 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1980 break;
1981 case e1000_fc_rx_pause:
8bde7f77
WD		 1982 /* RX Flow control is enabled and TX Flow control is disabled by a
1983 * software over-ride. Since there really isn't a way to advertise
682011ff
WD		 1984 * that we are capable of RX Pause ONLY, we will advertise that we
1985 * support both symmetric and asymmetric RX PAUSE. Later, we will
1986 * disable the adapter's ability to send PAUSE frames.
1987 */
1988 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1989 break;
1990 case e1000_fc_tx_pause:
8bde7f77 1991 /* TX Flow control is enabled, and RX Flow control is disabled, by a
682011ff
WD		 1992 * software over-ride.
1993 */
1994 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1995 break;
1996 case e1000_fc_full:
1997 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1998 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1999 break;
2000 default:
2001 DEBUGOUT("Flow control param set incorrectly\n");
2002 return -E1000_ERR_CONFIG;
2003 break;
2004 }
2005
2006 /* Since auto-negotiation is enabled, take the link out of reset (the link
2007 * will be in reset, because we previously reset the chip). This will
2008 * restart auto-negotiation. If auto-neogtiation is successful then the
2009 * link-up status bit will be set and the flow control enable bits (RFCE
2010 * and TFCE) will be set according to their negotiated value.
2011 */
2012 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2013
2014 E1000_WRITE_REG(hw, TXCW, txcw);
2015 E1000_WRITE_REG(hw, CTRL, ctrl);
2016 E1000_WRITE_FLUSH(hw);
2017
2018 hw->txcw = txcw;
2019 mdelay(1);
2020
2021 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
8bde7f77
WD		 2022 * indication in the Device Status Register. Time-out if a link isn't
2023 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
682011ff
WD		 2024 * less than 500 milliseconds even if the other end is doing it in SW).
2025 */
2026 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2027 DEBUGOUT("Looking for Link\n");
2028 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2029 mdelay(10);
2030 status = E1000_READ_REG(hw, STATUS);
2031 if (status & E1000_STATUS_LU)
2032 break;
2033 }
2034 if (i == (LINK_UP_TIMEOUT / 10)) {
8bde7f77 2035 /* AutoNeg failed to achieve a link, so we'll call
682011ff
WD		 2036 * e1000_check_for_link. This routine will force the link up if we
2037 * detect a signal. This will allow us to communicate with
2038 * non-autonegotiating link partners.
2039 */
2040 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2041 hw->autoneg_failed = 1;
2042 ret_val = e1000_check_for_link(nic);
2043 if (ret_val < 0) {
2044 DEBUGOUT("Error while checking for link\n");
2045 return ret_val;
2046 }
2047 hw->autoneg_failed = 0;
2048 } else {
2049 hw->autoneg_failed = 0;
2050 DEBUGOUT("Valid Link Found\n");
2051 }
aa070789
RZ		 2052 } else {
2053 DEBUGOUT("No Signal Detected\n");
2054 return -E1000_ERR_NOLINK;
2055 }
2056 return 0;
2057}
2058
aa070789
RZ		 2059/******************************************************************************
2060* Make sure we have a valid PHY and change PHY mode before link setup.
2061*
2062* hw - Struct containing variables accessed by shared code
2063******************************************************************************/
2064static int32_t
2065e1000_copper_link_preconfig(struct e1000_hw *hw)
2066{
2067 uint32_t ctrl;
2068 int32_t ret_val;
2069 uint16_t phy_data;
2070
2071 DEBUGFUNC();
2072
2073 ctrl = E1000_READ_REG(hw, CTRL);
2074 /* With 82543, we need to force speed and duplex on the MAC equal to what
2075 * the PHY speed and duplex configuration is. In addition, we need to
2076 * perform a hardware reset on the PHY to take it out of reset.
2077 */
2078 if (hw->mac_type > e1000_82543) {
2079 ctrl |= E1000_CTRL_SLU;
2080 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2081 E1000_WRITE_REG(hw, CTRL, ctrl);
2082 } else {
2083 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2084 | E1000_CTRL_SLU);
2085 E1000_WRITE_REG(hw, CTRL, ctrl);
2086 ret_val = e1000_phy_hw_reset(hw);
2087 if (ret_val)
2088 return ret_val;
2089 }
2090
2091 /* Make sure we have a valid PHY */
2092 ret_val = e1000_detect_gig_phy(hw);
2093 if (ret_val) {
2094 DEBUGOUT("Error, did not detect valid phy.\n");
2095 return ret_val;
2096 }
2097 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2098
2099#ifndef CONFIG_AP1000
2100 /* Set PHY to class A mode (if necessary) */
2101 ret_val = e1000_set_phy_mode(hw);
2102 if (ret_val)
2103 return ret_val;
2104#endif
2105 if ((hw->mac_type == e1000_82545_rev_3) ||
2106 (hw->mac_type == e1000_82546_rev_3)) {
2107 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2108 &phy_data);
2109 phy_data |= 0x00000008;
2110 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2111 phy_data);
2112 }
2113
2114 if (hw->mac_type <= e1000_82543 ||
2115 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2116 hw->mac_type == e1000_82541_rev_2
2117 || hw->mac_type == e1000_82547_rev_2)
2118 hw->phy_reset_disable = FALSE;
2119
2120 return E1000_SUCCESS;
2121}
2122
2123/*****************************************************************************
2124 *
2125 * This function sets the lplu state according to the active flag. When
2126 * activating lplu this function also disables smart speed and vise versa.
2127 * lplu will not be activated unless the device autonegotiation advertisment
2128 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2129 * hw: Struct containing variables accessed by shared code
2130 * active - true to enable lplu false to disable lplu.
2131 *
2132 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2133 * E1000_SUCCESS at any other case.
2134 *
2135 ****************************************************************************/
2136
2137static int32_t
2138e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2139{
2140 uint32_t phy_ctrl = 0;
2141 int32_t ret_val;
2142 uint16_t phy_data;
2143 DEBUGFUNC();
2144
2145 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2146 && hw->phy_type != e1000_phy_igp_3)
2147 return E1000_SUCCESS;
2148
2149 /* During driver activity LPLU should not be used or it will attain link
2150 * from the lowest speeds starting from 10Mbps. The capability is used
2151 * for Dx transitions and states */
2152 if (hw->mac_type == e1000_82541_rev_2
2153 || hw->mac_type == e1000_82547_rev_2) {
2154 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2155 &phy_data);
2156 if (ret_val)
2157 return ret_val;
2158 } else if (hw->mac_type == e1000_ich8lan) {
2159 /* MAC writes into PHY register based on the state transition
2160 * and start auto-negotiation. SW driver can overwrite the
2161 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2162 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2163 } else {
2164 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2165 &phy_data);
2166 if (ret_val)
2167 return ret_val;
2168 }
2169
2170 if (!active) {
2171 if (hw->mac_type == e1000_82541_rev_2 ||
2172 hw->mac_type == e1000_82547_rev_2) {
2173 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2174 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2175 phy_data);
2176 if (ret_val)
2177 return ret_val;
2178 } else {
2179 if (hw->mac_type == e1000_ich8lan) {
2180 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2181 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2182 } else {
2183 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2184 ret_val = e1000_write_phy_reg(hw,
2185 IGP02E1000_PHY_POWER_MGMT, phy_data);
2186 if (ret_val)
2187 return ret_val;
2188 }
2189 }
2190
2191 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2192 * Dx states where the power conservation is most important. During
2193 * driver activity we should enable SmartSpeed, so performance is
2194 * maintained. */
2195 if (hw->smart_speed == e1000_smart_speed_on) {
2196 ret_val = e1000_read_phy_reg(hw,
2197 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2198 if (ret_val)
2199 return ret_val;
2200
2201 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2202 ret_val = e1000_write_phy_reg(hw,
2203 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2204 if (ret_val)
2205 return ret_val;
2206 } else if (hw->smart_speed == e1000_smart_speed_off) {
2207 ret_val = e1000_read_phy_reg(hw,
2208 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2209 if (ret_val)
2210 return ret_val;
2211
2212 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2213 ret_val = e1000_write_phy_reg(hw,
2214 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2215 if (ret_val)
2216 return ret_val;
2217 }
2218
2219 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2220 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2221 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2222
2223 if (hw->mac_type == e1000_82541_rev_2 ||
2224 hw->mac_type == e1000_82547_rev_2) {
2225 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2226 ret_val = e1000_write_phy_reg(hw,
2227 IGP01E1000_GMII_FIFO, phy_data);
2228 if (ret_val)
2229 return ret_val;
2230 } else {
2231 if (hw->mac_type == e1000_ich8lan) {
2232 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2233 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2234 } else {
2235 phy_data |= IGP02E1000_PM_D3_LPLU;
2236 ret_val = e1000_write_phy_reg(hw,
2237 IGP02E1000_PHY_POWER_MGMT, phy_data);
2238 if (ret_val)
2239 return ret_val;
2240 }
2241 }
2242
2243 /* When LPLU is enabled we should disable SmartSpeed */
2244 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2245 &phy_data);
2246 if (ret_val)
2247 return ret_val;
2248
2249 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2250 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2251 phy_data);
2252 if (ret_val)
2253 return ret_val;
2254 }
2255 return E1000_SUCCESS;
2256}
2257
2258/*****************************************************************************
2259 *
2260 * This function sets the lplu d0 state according to the active flag. When
2261 * activating lplu this function also disables smart speed and vise versa.
2262 * lplu will not be activated unless the device autonegotiation advertisment
2263 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2264 * hw: Struct containing variables accessed by shared code
2265 * active - true to enable lplu false to disable lplu.
2266 *
2267 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2268 * E1000_SUCCESS at any other case.
2269 *
2270 ****************************************************************************/
2271
2272static int32_t
2273e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2274{
2275 uint32_t phy_ctrl = 0;
2276 int32_t ret_val;
2277 uint16_t phy_data;
2278 DEBUGFUNC();
2279
2280 if (hw->mac_type <= e1000_82547_rev_2)
2281 return E1000_SUCCESS;
2282
2283 if (hw->mac_type == e1000_ich8lan) {
2284 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2285 } else {
2286 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2287 &phy_data);
2288 if (ret_val)
2289 return ret_val;
2290 }
2291
2292 if (!active) {
2293 if (hw->mac_type == e1000_ich8lan) {
2294 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2295 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2296 } else {
2297 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2298 ret_val = e1000_write_phy_reg(hw,
2299 IGP02E1000_PHY_POWER_MGMT, phy_data);
2300 if (ret_val)
2301 return ret_val;
2302 }
2303
2304 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2305 * Dx states where the power conservation is most important. During
2306 * driver activity we should enable SmartSpeed, so performance is
2307 * maintained. */
2308 if (hw->smart_speed == e1000_smart_speed_on) {
2309 ret_val = e1000_read_phy_reg(hw,
2310 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2311 if (ret_val)
2312 return ret_val;
2313
2314 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2315 ret_val = e1000_write_phy_reg(hw,
2316 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2317 if (ret_val)
2318 return ret_val;
2319 } else if (hw->smart_speed == e1000_smart_speed_off) {
2320 ret_val = e1000_read_phy_reg(hw,
2321 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2322 if (ret_val)
2323 return ret_val;
2324
2325 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2326 ret_val = e1000_write_phy_reg(hw,
2327 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2328 if (ret_val)
2329 return ret_val;
2330 }
2331
2332
2333 } else {
2334
2335 if (hw->mac_type == e1000_ich8lan) {
2336 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2337 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2338 } else {
2339 phy_data |= IGP02E1000_PM_D0_LPLU;
2340 ret_val = e1000_write_phy_reg(hw,
2341 IGP02E1000_PHY_POWER_MGMT, phy_data);
2342 if (ret_val)
2343 return ret_val;
2344 }
2345
2346 /* When LPLU is enabled we should disable SmartSpeed */
2347 ret_val = e1000_read_phy_reg(hw,
2348 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2349 if (ret_val)
2350 return ret_val;
2351
2352 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2353 ret_val = e1000_write_phy_reg(hw,
2354 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2355 if (ret_val)
2356 return ret_val;
2357
2358 }
2359 return E1000_SUCCESS;
2360}
2361
2362/********************************************************************
2363* Copper link setup for e1000_phy_igp series.
2364*
2365* hw - Struct containing variables accessed by shared code
2366*********************************************************************/
2367static int32_t
2368e1000_copper_link_igp_setup(struct e1000_hw *hw)
2369{
2370 uint32_t led_ctrl;
2371 int32_t ret_val;
2372 uint16_t phy_data;
2373
f81ecb5d 2374 DEBUGFUNC();
aa070789
RZ		 2375
2376 if (hw->phy_reset_disable)
2377 return E1000_SUCCESS;
2378
2379 ret_val = e1000_phy_reset(hw);
2380 if (ret_val) {
2381 DEBUGOUT("Error Resetting the PHY\n");
2382 return ret_val;
2383 }
2384
2385 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2386 mdelay(15);
2387 if (hw->mac_type != e1000_ich8lan) {
2388 /* Configure activity LED after PHY reset */
2389 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2390 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2391 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2392 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2393 }
2394
2395 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2396 if (hw->phy_type == e1000_phy_igp) {
2397 /* disable lplu d3 during driver init */
2398 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2399 if (ret_val) {
2400 DEBUGOUT("Error Disabling LPLU D3\n");
2401 return ret_val;
2402 }
2403 }
2404
2405 /* disable lplu d0 during driver init */
2406 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2407 if (ret_val) {
2408 DEBUGOUT("Error Disabling LPLU D0\n");
2409 return ret_val;
2410 }
2411 /* Configure mdi-mdix settings */
2412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2413 if (ret_val)
2414 return ret_val;
2415
2416 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2417 hw->dsp_config_state = e1000_dsp_config_disabled;
2418 /* Force MDI for earlier revs of the IGP PHY */
2419 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2420 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2421 hw->mdix = 1;
2422
2423 } else {
2424 hw->dsp_config_state = e1000_dsp_config_enabled;
2425 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2426
2427 switch (hw->mdix) {
2428 case 1:
2429 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2430 break;
2431 case 2:
2432 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2433 break;
2434 case 0:
2435 default:
2436 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2437 break;
2438 }
2439 }
2440 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2441 if (ret_val)
2442 return ret_val;
2443
2444 /* set auto-master slave resolution settings */
2445 if (hw->autoneg) {
2446 e1000_ms_type phy_ms_setting = hw->master_slave;
2447
2448 if (hw->ffe_config_state == e1000_ffe_config_active)
2449 hw->ffe_config_state = e1000_ffe_config_enabled;
2450
2451 if (hw->dsp_config_state == e1000_dsp_config_activated)
2452 hw->dsp_config_state = e1000_dsp_config_enabled;
2453
2454 /* when autonegotiation advertisment is only 1000Mbps then we
2455 * should disable SmartSpeed and enable Auto MasterSlave
2456 * resolution as hardware default. */
2457 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2458 /* Disable SmartSpeed */
2459 ret_val = e1000_read_phy_reg(hw,
2460 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2461 if (ret_val)
2462 return ret_val;
2463 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2464 ret_val = e1000_write_phy_reg(hw,
2465 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2466 if (ret_val)
2467 return ret_val;
2468 /* Set auto Master/Slave resolution process */
2469 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2470 &phy_data);
2471 if (ret_val)
2472 return ret_val;
2473 phy_data &= ~CR_1000T_MS_ENABLE;
2474 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2475 phy_data);
2476 if (ret_val)
2477 return ret_val;
2478 }
2479
2480 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2481 if (ret_val)
2482 return ret_val;
2483
2484 /* load defaults for future use */
2485 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2486 ((phy_data & CR_1000T_MS_VALUE) ?
2487 e1000_ms_force_master :
2488 e1000_ms_force_slave) :
2489 e1000_ms_auto;
2490
2491 switch (phy_ms_setting) {
2492 case e1000_ms_force_master:
2493 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2494 break;
2495 case e1000_ms_force_slave:
2496 phy_data |= CR_1000T_MS_ENABLE;
2497 phy_data &= ~(CR_1000T_MS_VALUE);
2498 break;
2499 case e1000_ms_auto:
2500 phy_data &= ~CR_1000T_MS_ENABLE;
2501 default:
2502 break;
2503 }
2504 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2505 if (ret_val)
2506 return ret_val;
2507 }
2508
2509 return E1000_SUCCESS;
2510}
2511
2512/*****************************************************************************
2513 * This function checks the mode of the firmware.
2514 *
2515 * returns - TRUE when the mode is IAMT or FALSE.
2516 ****************************************************************************/
2517boolean_t
2518e1000_check_mng_mode(struct e1000_hw *hw)
2519{
2520 uint32_t fwsm;
2521 DEBUGFUNC();
2522
2523 fwsm = E1000_READ_REG(hw, FWSM);
2524
2525 if (hw->mac_type == e1000_ich8lan) {
2526 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2527 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2528 return TRUE;
2529 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2530 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2531 return TRUE;
2532
2533 return FALSE;
2534}
2535
2536static int32_t
2537e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2538{
2539 uint32_t reg_val;
2540 uint16_t swfw;
2541 DEBUGFUNC();
2542
2543 if ((hw->mac_type == e1000_80003es2lan) &&
2544 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2545 swfw = E1000_SWFW_PHY1_SM;
2546 } else {
2547 swfw = E1000_SWFW_PHY0_SM;
2548 }
2549 if (e1000_swfw_sync_acquire(hw, swfw))
2550 return -E1000_ERR_SWFW_SYNC;
2551
2552 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2553 & E1000_KUMCTRLSTA_OFFSET) | data;
2554 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2555 udelay(2);
2556
2557 return E1000_SUCCESS;
2558}
2559
2560static int32_t
2561e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2562{
2563 uint32_t reg_val;
2564 uint16_t swfw;
2565 DEBUGFUNC();
2566
2567 if ((hw->mac_type == e1000_80003es2lan) &&
2568 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2569 swfw = E1000_SWFW_PHY1_SM;
2570 } else {
2571 swfw = E1000_SWFW_PHY0_SM;
2572 }
2573 if (e1000_swfw_sync_acquire(hw, swfw))
2574 return -E1000_ERR_SWFW_SYNC;
2575
2576 /* Write register address */
2577 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2578 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2579 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2580 udelay(2);
2581
2582 /* Read the data returned */
2583 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2584 *data = (uint16_t)reg_val;
2585
2586 return E1000_SUCCESS;
2587}
2588
2589/********************************************************************
2590* Copper link setup for e1000_phy_gg82563 series.
2591*
2592* hw - Struct containing variables accessed by shared code
2593*********************************************************************/
2594static int32_t
2595e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2596{
2597 int32_t ret_val;
2598 uint16_t phy_data;
2599 uint32_t reg_data;
2600
2601 DEBUGFUNC();
2602
2603 if (!hw->phy_reset_disable) {
2604 /* Enable CRS on TX for half-duplex operation. */
2605 ret_val = e1000_read_phy_reg(hw,
2606 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2607 if (ret_val)
2608 return ret_val;
2609
2610 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2611 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2612 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2613
2614 ret_val = e1000_write_phy_reg(hw,
2615 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2616 if (ret_val)
2617 return ret_val;
2618
2619 /* Options:
2620 * MDI/MDI-X = 0 (default)
2621 * 0 - Auto for all speeds
2622 * 1 - MDI mode
2623 * 2 - MDI-X mode
2624 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2625 */
2626 ret_val = e1000_read_phy_reg(hw,
2627 GG82563_PHY_SPEC_CTRL, &phy_data);
2628 if (ret_val)
2629 return ret_val;
2630
2631 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2632
2633 switch (hw->mdix) {
2634 case 1:
2635 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2636 break;
2637 case 2:
2638 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2639 break;
2640 case 0:
2641 default:
2642 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2643 break;
2644 }
2645
2646 /* Options:
2647 * disable_polarity_correction = 0 (default)
2648 * Automatic Correction for Reversed Cable Polarity
2649 * 0 - Disabled
2650 * 1 - Enabled
2651 */
2652 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2653 ret_val = e1000_write_phy_reg(hw,
2654 GG82563_PHY_SPEC_CTRL, phy_data);
2655
2656 if (ret_val)
2657 return ret_val;
2658
2659 /* SW Reset the PHY so all changes take effect */
2660 ret_val = e1000_phy_reset(hw);
2661 if (ret_val) {
2662 DEBUGOUT("Error Resetting the PHY\n");
2663 return ret_val;
2664 }
2665 } /* phy_reset_disable */
2666
2667 if (hw->mac_type == e1000_80003es2lan) {
2668 /* Bypass RX and TX FIFO's */
2669 ret_val = e1000_write_kmrn_reg(hw,
2670 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2671 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2672 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2673 if (ret_val)
2674 return ret_val;
2675
2676 ret_val = e1000_read_phy_reg(hw,
2677 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2678 if (ret_val)
2679 return ret_val;
2680
2681 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2682 ret_val = e1000_write_phy_reg(hw,
2683 GG82563_PHY_SPEC_CTRL_2, phy_data);
2684
2685 if (ret_val)
2686 return ret_val;
2687
2688 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2689 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2690 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2691
2692 ret_val = e1000_read_phy_reg(hw,
2693 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2694 if (ret_val)
2695 return ret_val;
2696
2697 /* Do not init these registers when the HW is in IAMT mode, since the
2698 * firmware will have already initialized them. We only initialize
2699 * them if the HW is not in IAMT mode.
2700 */
2701 if (e1000_check_mng_mode(hw) == FALSE) {
2702 /* Enable Electrical Idle on the PHY */
2703 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2704 ret_val = e1000_write_phy_reg(hw,
2705 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2706 if (ret_val)
2707 return ret_val;
2708
2709 ret_val = e1000_read_phy_reg(hw,
2710 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2711 if (ret_val)
2712 return ret_val;
2713
2714 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2715 ret_val = e1000_write_phy_reg(hw,
2716 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2717
2718 if (ret_val)
2719 return ret_val;
2720 }
2721
2722 /* Workaround: Disable padding in Kumeran interface in the MAC
2723 * and in the PHY to avoid CRC errors.
2724 */
2725 ret_val = e1000_read_phy_reg(hw,
2726 GG82563_PHY_INBAND_CTRL, &phy_data);
2727 if (ret_val)
2728 return ret_val;
2729 phy_data |= GG82563_ICR_DIS_PADDING;
2730 ret_val = e1000_write_phy_reg(hw,
2731 GG82563_PHY_INBAND_CTRL, phy_data);
2732 if (ret_val)
2733 return ret_val;
682011ff 2734 }
aa070789 2735 return E1000_SUCCESS;
682011ff
WD		 2736}
2737
aa070789
RZ		 2738/********************************************************************
2739* Copper link setup for e1000_phy_m88 series.
682011ff
WD		 2740*
2741* hw - Struct containing variables accessed by shared code
aa070789
RZ		 2742*********************************************************************/
2743static int32_t
2744e1000_copper_link_mgp_setup(struct e1000_hw *hw)
682011ff 2745{
682011ff 2746 int32_t ret_val;
682011ff
WD		 2747 uint16_t phy_data;
2748
2749 DEBUGFUNC();
2750
aa070789
RZ		 2751 if (hw->phy_reset_disable)
2752 return E1000_SUCCESS;
682011ff 2753
aa070789
RZ		 2754 /* Enable CRS on TX. This must be set for half-duplex operation. */
2755 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2756 if (ret_val)
682011ff 2757 return ret_val;
682011ff 2758
682011ff
WD		 2759 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2760
682011ff
WD		 2761 /* Options:
2762 * MDI/MDI-X = 0 (default)
2763 * 0 - Auto for all speeds
2764 * 1 - MDI mode
2765 * 2 - MDI-X mode
2766 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2767 */
2768 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
aa070789 2769
682011ff
WD		 2770 switch (hw->mdix) {
2771 case 1:
2772 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2773 break;
2774 case 2:
2775 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2776 break;
2777 case 3:
2778 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2779 break;
2780 case 0:
2781 default:
2782 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2783 break;
2784 }
682011ff 2785
682011ff
WD		 2786 /* Options:
2787 * disable_polarity_correction = 0 (default)
aa070789 2788 * Automatic Correction for Reversed Cable Polarity
682011ff
WD		 2789 * 0 - Disabled
2790 * 1 - Enabled
2791 */
2792 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
aa070789
RZ		 2793 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2794 if (ret_val)
2795 return ret_val;
682011ff 2796
aa070789
RZ		 2797 if (hw->phy_revision < M88E1011_I_REV_4) {
2798 /* Force TX_CLK in the Extended PHY Specific Control Register
2799 * to 25MHz clock.
2800 */
2801 ret_val = e1000_read_phy_reg(hw,
2802 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2803 if (ret_val)
2804 return ret_val;
2805
2806 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2807
2808 if ((hw->phy_revision == E1000_REVISION_2) &&
2809 (hw->phy_id == M88E1111_I_PHY_ID)) {
2810 /* Vidalia Phy, set the downshift counter to 5x */
2811 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2812 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2813 ret_val = e1000_write_phy_reg(hw,
2814 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2815 if (ret_val)
2816 return ret_val;
2817 } else {
2818 /* Configure Master and Slave downshift values */
2819 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2820 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2821 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2822 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2823 ret_val = e1000_write_phy_reg(hw,
2824 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2825 if (ret_val)
2826 return ret_val;
2827 }
682011ff
WD		 2828 }
2829
2830 /* SW Reset the PHY so all changes take effect */
2831 ret_val = e1000_phy_reset(hw);
aa070789 2832 if (ret_val) {
682011ff
WD		 2833 DEBUGOUT("Error Resetting the PHY\n");
2834 return ret_val;
2835 }
2836
aa070789
RZ		 2837 return E1000_SUCCESS;
2838}
2839
2840/********************************************************************
2841* Setup auto-negotiation and flow control advertisements,
2842* and then perform auto-negotiation.
2843*
2844* hw - Struct containing variables accessed by shared code
2845*********************************************************************/
2846static int32_t
2847e1000_copper_link_autoneg(struct e1000_hw *hw)
2848{
2849 int32_t ret_val;
2850 uint16_t phy_data;
2851
2852 DEBUGFUNC();
682011ff 2853
682011ff
WD		 2854 /* Perform some bounds checking on the hw->autoneg_advertised
2855 * parameter. If this variable is zero, then set it to the default.
2856 */
2857 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2858
2859 /* If autoneg_advertised is zero, we assume it was not defaulted
2860 * by the calling code so we set to advertise full capability.
2861 */
2862 if (hw->autoneg_advertised == 0)
2863 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2864
aa070789
RZ		 2865 /* IFE phy only supports 10/100 */
2866 if (hw->phy_type == e1000_phy_ife)
2867 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2868
682011ff
WD		 2869 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2870 ret_val = e1000_phy_setup_autoneg(hw);
aa070789 2871 if (ret_val) {
682011ff
WD		 2872 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2873 return ret_val;
2874 }
2875 DEBUGOUT("Restarting Auto-Neg\n");
2876
2877 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2878 * the Auto Neg Restart bit in the PHY control register.
2879 */
aa070789
RZ		 2880 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2881 if (ret_val)
2882 return ret_val;
2883
682011ff 2884 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
aa070789
RZ		 2885 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2886 if (ret_val)
2887 return ret_val;
2888
682011ff
WD		 2889 /* Does the user want to wait for Auto-Neg to complete here, or
2890 * check at a later time (for example, callback routine).
2891 */
aa070789
RZ		 2892 /* If we do not wait for autonegtation to complete I
2893 * do not see a valid link status.
2894 * wait_autoneg_complete = 1 .
2895 */
682011ff
WD		 2896 if (hw->wait_autoneg_complete) {
2897 ret_val = e1000_wait_autoneg(hw);
aa070789
RZ		 2898 if (ret_val) {
2899 DEBUGOUT("Error while waiting for autoneg"
2900 "to complete\n");
682011ff
WD		 2901 return ret_val;
2902 }
2903 }
aa070789
RZ		 2904
2905 hw->get_link_status = TRUE;
2906
2907 return E1000_SUCCESS;
2908}
2909
2910/******************************************************************************
2911* Config the MAC and the PHY after link is up.
2912* 1) Set up the MAC to the current PHY speed/duplex
2913* if we are on 82543. If we
2914* are on newer silicon, we only need to configure
2915* collision distance in the Transmit Control Register.
2916* 2) Set up flow control on the MAC to that established with
2917* the link partner.
2918* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2919*
2920* hw - Struct containing variables accessed by shared code
2921******************************************************************************/
2922static int32_t
2923e1000_copper_link_postconfig(struct e1000_hw *hw)
2924{
2925 int32_t ret_val;
2926 DEBUGFUNC();
2927
2928 if (hw->mac_type >= e1000_82544) {
2929 e1000_config_collision_dist(hw);
2930 } else {
2931 ret_val = e1000_config_mac_to_phy(hw);
2932 if (ret_val) {
2933 DEBUGOUT("Error configuring MAC to PHY settings\n");
2934 return ret_val;
2935 }
2936 }
2937 ret_val = e1000_config_fc_after_link_up(hw);
2938 if (ret_val) {
2939 DEBUGOUT("Error Configuring Flow Control\n");
682011ff
WD		 2940 return ret_val;
2941 }
aa070789
RZ		 2942 return E1000_SUCCESS;
2943}
2944
2945/******************************************************************************
2946* Detects which PHY is present and setup the speed and duplex
2947*
2948* hw - Struct containing variables accessed by shared code
2949******************************************************************************/
2950static int
2951e1000_setup_copper_link(struct eth_device *nic)
2952{
2953 struct e1000_hw *hw = nic->priv;
2954 int32_t ret_val;
2955 uint16_t i;
2956 uint16_t phy_data;
2957 uint16_t reg_data;
2958
2959 DEBUGFUNC();
2960
2961 switch (hw->mac_type) {
2962 case e1000_80003es2lan:
2963 case e1000_ich8lan:
2964 /* Set the mac to wait the maximum time between each
2965 * iteration and increase the max iterations when
2966 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2967 ret_val = e1000_write_kmrn_reg(hw,
2968 GG82563_REG(0x34, 4), 0xFFFF);
2969 if (ret_val)
2970 return ret_val;
2971 ret_val = e1000_read_kmrn_reg(hw,
2972 GG82563_REG(0x34, 9), &reg_data);
2973 if (ret_val)
2974 return ret_val;
2975 reg_data |= 0x3F;
2976 ret_val = e1000_write_kmrn_reg(hw,
2977 GG82563_REG(0x34, 9), reg_data);
2978 if (ret_val)
2979 return ret_val;
2980 default:
2981 break;
2982 }
2983
2984 /* Check if it is a valid PHY and set PHY mode if necessary. */
2985 ret_val = e1000_copper_link_preconfig(hw);
2986 if (ret_val)
2987 return ret_val;
2988 switch (hw->mac_type) {
2989 case e1000_80003es2lan:
2990 /* Kumeran registers are written-only */
2991 reg_data =
2992 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2993 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2994 ret_val = e1000_write_kmrn_reg(hw,
2995 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
2996 if (ret_val)
2997 return ret_val;
2998 break;
2999 default:
3000 break;
3001 }
3002
3003 if (hw->phy_type == e1000_phy_igp ||
3004 hw->phy_type == e1000_phy_igp_3 ||
3005 hw->phy_type == e1000_phy_igp_2) {
3006 ret_val = e1000_copper_link_igp_setup(hw);
3007 if (ret_val)
3008 return ret_val;
3009 } else if (hw->phy_type == e1000_phy_m88) {
3010 ret_val = e1000_copper_link_mgp_setup(hw);
3011 if (ret_val)
3012 return ret_val;
3013 } else if (hw->phy_type == e1000_phy_gg82563) {
3014 ret_val = e1000_copper_link_ggp_setup(hw);
3015 if (ret_val)
3016 return ret_val;
3017 }
3018
3019 /* always auto */
3020 /* Setup autoneg and flow control advertisement
3021 * and perform autonegotiation */
3022 ret_val = e1000_copper_link_autoneg(hw);
3023 if (ret_val)
3024 return ret_val;
682011ff
WD		 3025
3026 /* Check link status. Wait up to 100 microseconds for link to become
3027 * valid.
3028 */
3029 for (i = 0; i < 10; i++) {
aa070789
RZ		 3030 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3031 if (ret_val)
3032 return ret_val;
3033 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3034 if (ret_val)
3035 return ret_val;
3036
682011ff 3037 if (phy_data & MII_SR_LINK_STATUS) {
aa070789
RZ		 3038 /* Config the MAC and PHY after link is up */
3039 ret_val = e1000_copper_link_postconfig(hw);
3040 if (ret_val)
682011ff 3041 return ret_val;
aa070789 3042
682011ff 3043 DEBUGOUT("Valid link established!!!\n");
aa070789 3044 return E1000_SUCCESS;
682011ff
WD		 3045 }
3046 udelay(10);
3047 }
3048
3049 DEBUGOUT("Unable to establish link!!!\n");
aa070789 3050 return E1000_SUCCESS;
682011ff
WD		 3051}
3052
3053/******************************************************************************
3054* Configures PHY autoneg and flow control advertisement settings
3055*
3056* hw - Struct containing variables accessed by shared code
3057******************************************************************************/
aa070789 3058int32_t
682011ff
WD		 3059e1000_phy_setup_autoneg(struct e1000_hw *hw)
3060{
aa070789 3061 int32_t ret_val;
682011ff
WD		 3062 uint16_t mii_autoneg_adv_reg;
3063 uint16_t mii_1000t_ctrl_reg;
3064
3065 DEBUGFUNC();
3066
3067 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
aa070789
RZ		 3068 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3069 if (ret_val)
3070 return ret_val;
682011ff 3071
aa070789
RZ		 3072 if (hw->phy_type != e1000_phy_ife) {
3073 /* Read the MII 1000Base-T Control Register (Address 9). */
3074 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3075 &mii_1000t_ctrl_reg);
3076 if (ret_val)
3077 return ret_val;
3078 } else
3079 mii_1000t_ctrl_reg = 0;
682011ff
WD		 3080
3081 /* Need to parse both autoneg_advertised and fc and set up
3082 * the appropriate PHY registers. First we will parse for
3083 * autoneg_advertised software override. Since we can advertise
3084 * a plethora of combinations, we need to check each bit
3085 * individually.
3086 */
3087
3088 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3089 * Advertisement Register (Address 4) and the 1000 mb speed bits in
aa070789 3090 * the 1000Base-T Control Register (Address 9).
682011ff
WD		 3091 */
3092 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3093 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3094
3095 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3096
3097 /* Do we want to advertise 10 Mb Half Duplex? */
3098 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3099 DEBUGOUT("Advertise 10mb Half duplex\n");
3100 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3101 }
3102
3103 /* Do we want to advertise 10 Mb Full Duplex? */
3104 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3105 DEBUGOUT("Advertise 10mb Full duplex\n");
3106 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3107 }
3108
3109 /* Do we want to advertise 100 Mb Half Duplex? */
3110 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3111 DEBUGOUT("Advertise 100mb Half duplex\n");
3112 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3113 }
3114
3115 /* Do we want to advertise 100 Mb Full Duplex? */
3116 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3117 DEBUGOUT("Advertise 100mb Full duplex\n");
3118 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3119 }
3120
3121 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3122 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3123 DEBUGOUT
3124 ("Advertise 1000mb Half duplex requested, request denied!\n");
3125 }
3126
3127 /* Do we want to advertise 1000 Mb Full Duplex? */
3128 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3129 DEBUGOUT("Advertise 1000mb Full duplex\n");
3130 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3131 }
3132
3133 /* Check for a software override of the flow control settings, and
3134 * setup the PHY advertisement registers accordingly. If
3135 * auto-negotiation is enabled, then software will have to set the
3136 * "PAUSE" bits to the correct value in the Auto-Negotiation
3137 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3138 *
3139 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3140 * 0: Flow control is completely disabled
3141 * 1: Rx flow control is enabled (we can receive pause frames
3142 * but not send pause frames).
3143 * 2: Tx flow control is enabled (we can send pause frames
3144 * but we do not support receiving pause frames).
3145 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff 3146 * other: No software override. The flow control configuration
1aeed8d7 3147 * in the EEPROM is used.
682011ff
WD		 3148 */
3149 switch (hw->fc) {
3150 case e1000_fc_none: /* 0 */
3151 /* Flow control (RX & TX) is completely disabled by a
3152 * software over-ride.
3153 */
3154 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3155 break;
3156 case e1000_fc_rx_pause: /* 1 */
3157 /* RX Flow control is enabled, and TX Flow control is
3158 * disabled, by a software over-ride.
3159 */
3160 /* Since there really isn't a way to advertise that we are
3161 * capable of RX Pause ONLY, we will advertise that we
3162 * support both symmetric and asymmetric RX PAUSE. Later
3163 * (in e1000_config_fc_after_link_up) we will disable the
3164 *hw's ability to send PAUSE frames.
3165 */
3166 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3167 break;
3168 case e1000_fc_tx_pause: /* 2 */
3169 /* TX Flow control is enabled, and RX Flow control is
3170 * disabled, by a software over-ride.
3171 */
3172 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3173 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3174 break;
3175 case e1000_fc_full: /* 3 */
3176 /* Flow control (both RX and TX) is enabled by a software
3177 * over-ride.
3178 */
3179 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3180 break;
3181 default:
3182 DEBUGOUT("Flow control param set incorrectly\n");
3183 return -E1000_ERR_CONFIG;
3184 }
3185
aa070789
RZ		 3186 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3187 if (ret_val)
3188 return ret_val;
682011ff
WD		 3189
3190 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3191
aa070789
RZ		 3192 if (hw->phy_type != e1000_phy_ife) {
3193 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3194 mii_1000t_ctrl_reg);
3195 if (ret_val)
3196 return ret_val;
682011ff 3197 }
aa070789
RZ		 3198
3199 return E1000_SUCCESS;
682011ff
WD		 3200}
3201
3202/******************************************************************************
3203* Sets the collision distance in the Transmit Control register
3204*
3205* hw - Struct containing variables accessed by shared code
3206*
3207* Link should have been established previously. Reads the speed and duplex
3208* information from the Device Status register.
3209******************************************************************************/
3210static void
3211e1000_config_collision_dist(struct e1000_hw *hw)
3212{
aa070789
RZ		 3213 uint32_t tctl, coll_dist;
3214
3215 DEBUGFUNC();
3216
3217 if (hw->mac_type < e1000_82543)
3218 coll_dist = E1000_COLLISION_DISTANCE_82542;
3219 else
3220 coll_dist = E1000_COLLISION_DISTANCE;
682011ff
WD		 3221
3222 tctl = E1000_READ_REG(hw, TCTL);
3223
3224 tctl &= ~E1000_TCTL_COLD;
aa070789 3225 tctl |= coll_dist << E1000_COLD_SHIFT;
682011ff
WD		 3226
3227 E1000_WRITE_REG(hw, TCTL, tctl);
3228 E1000_WRITE_FLUSH(hw);
3229}
3230
3231/******************************************************************************
3232* Sets MAC speed and duplex settings to reflect the those in the PHY
3233*
3234* hw - Struct containing variables accessed by shared code
3235* mii_reg - data to write to the MII control register
3236*
3237* The contents of the PHY register containing the needed information need to
3238* be passed in.
3239******************************************************************************/
3240static int
3241e1000_config_mac_to_phy(struct e1000_hw *hw)
3242{
3243 uint32_t ctrl;
3244 uint16_t phy_data;
3245
3246 DEBUGFUNC();
3247
3248 /* Read the Device Control Register and set the bits to Force Speed
3249 * and Duplex.
3250 */
3251 ctrl = E1000_READ_REG(hw, CTRL);
3252 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3253 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3254
3255 /* Set up duplex in the Device Control and Transmit Control
3256 * registers depending on negotiated values.
3257 */
3258 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3259 DEBUGOUT("PHY Read Error\n");
3260 return -E1000_ERR_PHY;
3261 }
3262 if (phy_data & M88E1000_PSSR_DPLX)
3263 ctrl |= E1000_CTRL_FD;
3264 else
3265 ctrl &= ~E1000_CTRL_FD;
3266
3267 e1000_config_collision_dist(hw);
3268
3269 /* Set up speed in the Device Control register depending on
3270 * negotiated values.
3271 */
3272 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3273 ctrl |= E1000_CTRL_SPD_1000;
3274 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3275 ctrl |= E1000_CTRL_SPD_100;
3276 /* Write the configured values back to the Device Control Reg. */
3277 E1000_WRITE_REG(hw, CTRL, ctrl);
3278 return 0;
3279}
3280
3281/******************************************************************************
3282 * Forces the MAC's flow control settings.
8bde7f77 3283 *
682011ff
WD		 3284 * hw - Struct containing variables accessed by shared code
3285 *
3286 * Sets the TFCE and RFCE bits in the device control register to reflect
3287 * the adapter settings. TFCE and RFCE need to be explicitly set by
3288 * software when a Copper PHY is used because autonegotiation is managed
3289 * by the PHY rather than the MAC. Software must also configure these
3290 * bits when link is forced on a fiber connection.
3291 *****************************************************************************/
3292static int
3293e1000_force_mac_fc(struct e1000_hw *hw)
3294{
3295 uint32_t ctrl;
3296
3297 DEBUGFUNC();
3298
3299 /* Get the current configuration of the Device Control Register */
3300 ctrl = E1000_READ_REG(hw, CTRL);
3301
3302 /* Because we didn't get link via the internal auto-negotiation
3303 * mechanism (we either forced link or we got link via PHY
3304 * auto-neg), we have to manually enable/disable transmit an
3305 * receive flow control.
3306 *
3307 * The "Case" statement below enables/disable flow control
3308 * according to the "hw->fc" parameter.
3309 *
3310 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3311 * 0: Flow control is completely disabled
3312 * 1: Rx flow control is enabled (we can receive pause
3313 * frames but not send pause frames).
3314 * 2: Tx flow control is enabled (we can send pause frames
3315 * frames but we do not receive pause frames).
3316 * 3: Both Rx and TX flow control (symmetric) is enabled.
682011ff
WD		 3317 * other: No other values should be possible at this point.
3318 */
3319
3320 switch (hw->fc) {
3321 case e1000_fc_none:
3322 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3323 break;
3324 case e1000_fc_rx_pause:
3325 ctrl &= (~E1000_CTRL_TFCE);
3326 ctrl |= E1000_CTRL_RFCE;
3327 break;
3328 case e1000_fc_tx_pause:
3329 ctrl &= (~E1000_CTRL_RFCE);
3330 ctrl |= E1000_CTRL_TFCE;
3331 break;
3332 case e1000_fc_full:
3333 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3334 break;
3335 default:
3336 DEBUGOUT("Flow control param set incorrectly\n");
3337 return -E1000_ERR_CONFIG;
3338 }
3339
3340 /* Disable TX Flow Control for 82542 (rev 2.0) */
3341 if (hw->mac_type == e1000_82542_rev2_0)
3342 ctrl &= (~E1000_CTRL_TFCE);
3343
3344 E1000_WRITE_REG(hw, CTRL, ctrl);
3345 return 0;
3346}
3347
3348/******************************************************************************
3349 * Configures flow control settings after link is established
8bde7f77 3350 *
682011ff
WD		 3351 * hw - Struct containing variables accessed by shared code
3352 *
3353 * Should be called immediately after a valid link has been established.
3354 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3355 * and autonegotiation is enabled, the MAC flow control settings will be set
3356 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3357 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3358 *****************************************************************************/
aa070789 3359static int32_t
682011ff
WD		 3360e1000_config_fc_after_link_up(struct e1000_hw *hw)
3361{
3362 int32_t ret_val;
3363 uint16_t mii_status_reg;
3364 uint16_t mii_nway_adv_reg;
3365 uint16_t mii_nway_lp_ability_reg;
3366 uint16_t speed;
3367 uint16_t duplex;
3368
3369 DEBUGFUNC();
3370
3371 /* Check for the case where we have fiber media and auto-neg failed
3372 * so we had to force link. In this case, we need to force the
3373 * configuration of the MAC to match the "fc" parameter.
3374 */
aa070789
RZ		 3375 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3376 || ((hw->media_type == e1000_media_type_internal_serdes)
3377 && (hw->autoneg_failed))
3378 || ((hw->media_type == e1000_media_type_copper)
3379 && (!hw->autoneg))) {
682011ff
WD		 3380 ret_val = e1000_force_mac_fc(hw);
3381 if (ret_val < 0) {
3382 DEBUGOUT("Error forcing flow control settings\n");
3383 return ret_val;
3384 }
3385 }
3386
3387 /* Check for the case where we have copper media and auto-neg is
3388 * enabled. In this case, we need to check and see if Auto-Neg
3389 * has completed, and if so, how the PHY and link partner has
3390 * flow control configured.
3391 */
3392 if (hw->media_type == e1000_media_type_copper) {
3393 /* Read the MII Status Register and check to see if AutoNeg
3394 * has completed. We read this twice because this reg has
3395 * some "sticky" (latched) bits.
3396 */
3397 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3398 DEBUGOUT("PHY Read Error \n");
3399 return -E1000_ERR_PHY;
3400 }
3401 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3402 DEBUGOUT("PHY Read Error \n");
3403 return -E1000_ERR_PHY;
3404 }
3405
3406 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3407 /* The AutoNeg process has completed, so we now need to
3408 * read both the Auto Negotiation Advertisement Register
3409 * (Address 4) and the Auto_Negotiation Base Page Ability
3410 * Register (Address 5) to determine how flow control was
3411 * negotiated.
3412 */
3413 if (e1000_read_phy_reg
3414 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3415 DEBUGOUT("PHY Read Error\n");
3416 return -E1000_ERR_PHY;
3417 }
3418 if (e1000_read_phy_reg
3419 (hw, PHY_LP_ABILITY,
3420 &mii_nway_lp_ability_reg) < 0) {
3421 DEBUGOUT("PHY Read Error\n");
3422 return -E1000_ERR_PHY;
3423 }
3424
3425 /* Two bits in the Auto Negotiation Advertisement Register
3426 * (Address 4) and two bits in the Auto Negotiation Base
3427 * Page Ability Register (Address 5) determine flow control
3428 * for both the PHY and the link partner. The following
3429 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3430 * 1999, describes these PAUSE resolution bits and how flow
3431 * control is determined based upon these settings.
3432 * NOTE: DC = Don't Care
3433 *
3434 * LOCAL DEVICE | LINK PARTNER
3435 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3436 *-------|---------|-------|---------|--------------------
1aeed8d7
WD		 3437 * 0 | 0 | DC | DC | e1000_fc_none
3438 * 0 | 1 | 0 | DC | e1000_fc_none
3439 * 0 | 1 | 1 | 0 | e1000_fc_none
3440 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3441 * 1 | 0 | 0 | DC | e1000_fc_none
3442 * 1 | DC | 1 | DC | e1000_fc_full
3443 * 1 | 1 | 0 | 0 | e1000_fc_none
3444 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3445 *
3446 */
3447 /* Are both PAUSE bits set to 1? If so, this implies
3448 * Symmetric Flow Control is enabled at both ends. The
3449 * ASM_DIR bits are irrelevant per the spec.
3450 *
3451 * For Symmetric Flow Control:
3452 *
3453 * LOCAL DEVICE | LINK PARTNER
3454 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3455 *-------|---------|-------|---------|--------------------
1aeed8d7 3456 * 1 | DC | 1 | DC | e1000_fc_full
682011ff
WD		 3457 *
3458 */
3459 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3460 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3461 /* Now we need to check if the user selected RX ONLY
3462 * of pause frames. In this case, we had to advertise
3463 * FULL flow control because we could not advertise RX
3464 * ONLY. Hence, we must now check to see if we need to
3465 * turn OFF the TRANSMISSION of PAUSE frames.
3466 */
3467 if (hw->original_fc == e1000_fc_full) {
3468 hw->fc = e1000_fc_full;
3469 DEBUGOUT("Flow Control = FULL.\r\n");
3470 } else {
3471 hw->fc = e1000_fc_rx_pause;
3472 DEBUGOUT
3473 ("Flow Control = RX PAUSE frames only.\r\n");
3474 }
3475 }
3476 /* For receiving PAUSE frames ONLY.
3477 *
3478 * LOCAL DEVICE | LINK PARTNER
3479 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3480 *-------|---------|-------|---------|--------------------
1aeed8d7 3481 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
682011ff
WD		 3482 *
3483 */
3484 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3485 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3486 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3487 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3488 {
3489 hw->fc = e1000_fc_tx_pause;
3490 DEBUGOUT
3491 ("Flow Control = TX PAUSE frames only.\r\n");
3492 }
3493 /* For transmitting PAUSE frames ONLY.
3494 *
3495 * LOCAL DEVICE | LINK PARTNER
3496 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3497 *-------|---------|-------|---------|--------------------
1aeed8d7 3498 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3499 *
3500 */
3501 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3502 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3503 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3504 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3505 {
3506 hw->fc = e1000_fc_rx_pause;
3507 DEBUGOUT
3508 ("Flow Control = RX PAUSE frames only.\r\n");
3509 }
3510 /* Per the IEEE spec, at this point flow control should be
3511 * disabled. However, we want to consider that we could
3512 * be connected to a legacy switch that doesn't advertise
3513 * desired flow control, but can be forced on the link
3514 * partner. So if we advertised no flow control, that is
3515 * what we will resolve to. If we advertised some kind of
3516 * receive capability (Rx Pause Only or Full Flow Control)
3517 * and the link partner advertised none, we will configure
3518 * ourselves to enable Rx Flow Control only. We can do
3519 * this safely for two reasons: If the link partner really
3520 * didn't want flow control enabled, and we enable Rx, no
3521 * harm done since we won't be receiving any PAUSE frames
3522 * anyway. If the intent on the link partner was to have
3523 * flow control enabled, then by us enabling RX only, we
3524 * can at least receive pause frames and process them.
3525 * This is a good idea because in most cases, since we are
3526 * predominantly a server NIC, more times than not we will
3527 * be asked to delay transmission of packets than asking
3528 * our link partner to pause transmission of frames.
3529 */
3530 else if (hw->original_fc == e1000_fc_none ||
3531 hw->original_fc == e1000_fc_tx_pause) {
3532 hw->fc = e1000_fc_none;
3533 DEBUGOUT("Flow Control = NONE.\r\n");
3534 } else {
3535 hw->fc = e1000_fc_rx_pause;
3536 DEBUGOUT
3537 ("Flow Control = RX PAUSE frames only.\r\n");
3538 }
3539
1aeed8d7 3540 /* Now we need to do one last check... If we auto-
682011ff
WD		 3541 * negotiated to HALF DUPLEX, flow control should not be
3542 * enabled per IEEE 802.3 spec.
3543 */
3544 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3545
3546 if (duplex == HALF_DUPLEX)
3547 hw->fc = e1000_fc_none;
3548
3549 /* Now we call a subroutine to actually force the MAC
3550 * controller to use the correct flow control settings.
3551 */
3552 ret_val = e1000_force_mac_fc(hw);
3553 if (ret_val < 0) {
3554 DEBUGOUT
3555 ("Error forcing flow control settings\n");
3556 return ret_val;
3557 }
3558 } else {
3559 DEBUGOUT
3560 ("Copper PHY and Auto Neg has not completed.\r\n");
3561 }
3562 }
aa070789 3563 return E1000_SUCCESS;
682011ff
WD		 3564}
3565
3566/******************************************************************************
3567 * Checks to see if the link status of the hardware has changed.
3568 *
3569 * hw - Struct containing variables accessed by shared code
3570 *
3571 * Called by any function that needs to check the link status of the adapter.
3572 *****************************************************************************/
3573static int
3574e1000_check_for_link(struct eth_device *nic)
3575{
3576 struct e1000_hw *hw = nic->priv;
3577 uint32_t rxcw;
3578 uint32_t ctrl;
3579 uint32_t status;
3580 uint32_t rctl;
3581 uint32_t signal;
3582 int32_t ret_val;
3583 uint16_t phy_data;
3584 uint16_t lp_capability;
3585
3586 DEBUGFUNC();
3587
8bde7f77
WD		 3588 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3589 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 3590 * cleared when there is a signal
3591 */
3592 ctrl = E1000_READ_REG(hw, CTRL);
3593 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3594 signal = E1000_CTRL_SWDPIN1;
3595 else
3596 signal = 0;
3597
3598 status = E1000_READ_REG(hw, STATUS);
3599 rxcw = E1000_READ_REG(hw, RXCW);
3600 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3601
3602 /* If we have a copper PHY then we only want to go out to the PHY
3603 * registers to see if Auto-Neg has completed and/or if our link
1aeed8d7 3604 * status has changed. The get_link_status flag will be set if we
682011ff
WD		 3605 * receive a Link Status Change interrupt or we have Rx Sequence
3606 * Errors.
3607 */
3608 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3609 /* First we want to see if the MII Status Register reports
3610 * link. If so, then we want to get the current speed/duplex
3611 * of the PHY.
3612 * Read the register twice since the link bit is sticky.
3613 */
3614 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3615 DEBUGOUT("PHY Read Error\n");
3616 return -E1000_ERR_PHY;
3617 }
3618 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3619 DEBUGOUT("PHY Read Error\n");
3620 return -E1000_ERR_PHY;
3621 }
3622
3623 if (phy_data & MII_SR_LINK_STATUS) {
3624 hw->get_link_status = FALSE;
3625 } else {
3626 /* No link detected */
3627 return -E1000_ERR_NOLINK;
3628 }
3629
3630 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3631 * have Si on board that is 82544 or newer, Auto
3632 * Speed Detection takes care of MAC speed/duplex
3633 * configuration. So we only need to configure Collision
3634 * Distance in the MAC. Otherwise, we need to force
3635 * speed/duplex on the MAC to the current PHY speed/duplex
3636 * settings.
3637 */
3638 if (hw->mac_type >= e1000_82544)
3639 e1000_config_collision_dist(hw);
3640 else {
3641 ret_val = e1000_config_mac_to_phy(hw);
3642 if (ret_val < 0) {
3643 DEBUGOUT
3644 ("Error configuring MAC to PHY settings\n");
3645 return ret_val;
3646 }
3647 }
3648
8bde7f77 3649 /* Configure Flow Control now that Auto-Neg has completed. First, we
682011ff
WD		 3650 * need to restore the desired flow control settings because we may
3651 * have had to re-autoneg with a different link partner.
3652 */
3653 ret_val = e1000_config_fc_after_link_up(hw);
3654 if (ret_val < 0) {
3655 DEBUGOUT("Error configuring flow control\n");
3656 return ret_val;
3657 }
3658
3659 /* At this point we know that we are on copper and we have
3660 * auto-negotiated link. These are conditions for checking the link
1aeed8d7 3661 * parter capability register. We use the link partner capability to
682011ff
WD		 3662 * determine if TBI Compatibility needs to be turned on or off. If
3663 * the link partner advertises any speed in addition to Gigabit, then
3664 * we assume that they are GMII-based, and TBI compatibility is not
3665 * needed. If no other speeds are advertised, we assume the link
3666 * partner is TBI-based, and we turn on TBI Compatibility.
3667 */
3668 if (hw->tbi_compatibility_en) {
3669 if (e1000_read_phy_reg
3670 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3671 DEBUGOUT("PHY Read Error\n");
3672 return -E1000_ERR_PHY;
3673 }
3674 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3675 NWAY_LPAR_10T_FD_CAPS |
3676 NWAY_LPAR_100TX_HD_CAPS |
3677 NWAY_LPAR_100TX_FD_CAPS |
3678 NWAY_LPAR_100T4_CAPS)) {
8bde7f77 3679 /* If our link partner advertises anything in addition to
682011ff
WD		 3680 * gigabit, we do not need to enable TBI compatibility.
3681 */
3682 if (hw->tbi_compatibility_on) {
3683 /* If we previously were in the mode, turn it off. */
3684 rctl = E1000_READ_REG(hw, RCTL);
3685 rctl &= ~E1000_RCTL_SBP;
3686 E1000_WRITE_REG(hw, RCTL, rctl);
3687 hw->tbi_compatibility_on = FALSE;
3688 }
3689 } else {
3690 /* If TBI compatibility is was previously off, turn it on. For
3691 * compatibility with a TBI link partner, we will store bad
3692 * packets. Some frames have an additional byte on the end and
3693 * will look like CRC errors to to the hardware.
3694 */
3695 if (!hw->tbi_compatibility_on) {
3696 hw->tbi_compatibility_on = TRUE;
3697 rctl = E1000_READ_REG(hw, RCTL);
3698 rctl |= E1000_RCTL_SBP;
3699 E1000_WRITE_REG(hw, RCTL, rctl);
3700 }
3701 }
3702 }
3703 }
3704 /* If we don't have link (auto-negotiation failed or link partner cannot
3705 * auto-negotiate), the cable is plugged in (we have signal), and our
3706 * link partner is not trying to auto-negotiate with us (we are receiving
3707 * idles or data), we need to force link up. We also need to give
3708 * auto-negotiation time to complete, in case the cable was just plugged
3709 * in. The autoneg_failed flag does this.
3710 */
3711 else if ((hw->media_type == e1000_media_type_fiber) &&
3712 (!(status & E1000_STATUS_LU)) &&
3713 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3714 (!(rxcw & E1000_RXCW_C))) {
3715 if (hw->autoneg_failed == 0) {
3716 hw->autoneg_failed = 1;
3717 return 0;
3718 }
3719 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3720
3721 /* Disable auto-negotiation in the TXCW register */
3722 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3723
3724 /* Force link-up and also force full-duplex. */
3725 ctrl = E1000_READ_REG(hw, CTRL);
3726 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3727 E1000_WRITE_REG(hw, CTRL, ctrl);
3728
3729 /* Configure Flow Control after forcing link up. */
3730 ret_val = e1000_config_fc_after_link_up(hw);
3731 if (ret_val < 0) {
3732 DEBUGOUT("Error configuring flow control\n");
3733 return ret_val;
3734 }
3735 }
3736 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3737 * auto-negotiation in the TXCW register and disable forced link in the
3738 * Device Control register in an attempt to auto-negotiate with our link
3739 * partner.
3740 */
3741 else if ((hw->media_type == e1000_media_type_fiber) &&
3742 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3743 DEBUGOUT
3744 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3745 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3746 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3747 }
3748 return 0;
3749}
3750
aa070789
RZ		 3751/******************************************************************************
3752* Configure the MAC-to-PHY interface for 10/100Mbps
3753*
3754* hw - Struct containing variables accessed by shared code
3755******************************************************************************/
3756static int32_t
3757e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3758{
3759 int32_t ret_val = E1000_SUCCESS;
3760 uint32_t tipg;
3761 uint16_t reg_data;
3762
3763 DEBUGFUNC();
3764
3765 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3766 ret_val = e1000_write_kmrn_reg(hw,
3767 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3768 if (ret_val)
3769 return ret_val;
3770
3771 /* Configure Transmit Inter-Packet Gap */
3772 tipg = E1000_READ_REG(hw, TIPG);
3773 tipg &= ~E1000_TIPG_IPGT_MASK;
3774 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3775 E1000_WRITE_REG(hw, TIPG, tipg);
3776
3777 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3778
3779 if (ret_val)
3780 return ret_val;
3781
3782 if (duplex == HALF_DUPLEX)
3783 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3784 else
3785 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3786
3787 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3788
3789 return ret_val;
3790}
3791
3792static int32_t
3793e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3794{
3795 int32_t ret_val = E1000_SUCCESS;
3796 uint16_t reg_data;
3797 uint32_t tipg;
3798
3799 DEBUGFUNC();
3800
3801 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3802 ret_val = e1000_write_kmrn_reg(hw,
3803 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3804 if (ret_val)
3805 return ret_val;
3806
3807 /* Configure Transmit Inter-Packet Gap */
3808 tipg = E1000_READ_REG(hw, TIPG);
3809 tipg &= ~E1000_TIPG_IPGT_MASK;
3810 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3811 E1000_WRITE_REG(hw, TIPG, tipg);
3812
3813 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3814
3815 if (ret_val)
3816 return ret_val;
3817
3818 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3819 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3820
3821 return ret_val;
3822}
3823
682011ff
WD		 3824/******************************************************************************
3825 * Detects the current speed and duplex settings of the hardware.
3826 *
3827 * hw - Struct containing variables accessed by shared code
3828 * speed - Speed of the connection
3829 * duplex - Duplex setting of the connection
3830 *****************************************************************************/
aa070789
RZ		 3831static int
3832e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3833 uint16_t *duplex)
682011ff
WD		 3834{
3835 uint32_t status;
aa070789
RZ		 3836 int32_t ret_val;
3837 uint16_t phy_data;
682011ff
WD		 3838
3839 DEBUGFUNC();
3840
3841 if (hw->mac_type >= e1000_82543) {
3842 status = E1000_READ_REG(hw, STATUS);
3843 if (status & E1000_STATUS_SPEED_1000) {
3844 *speed = SPEED_1000;
3845 DEBUGOUT("1000 Mbs, ");
3846 } else if (status & E1000_STATUS_SPEED_100) {
3847 *speed = SPEED_100;
3848 DEBUGOUT("100 Mbs, ");
3849 } else {
3850 *speed = SPEED_10;
3851 DEBUGOUT("10 Mbs, ");
3852 }
3853
3854 if (status & E1000_STATUS_FD) {
3855 *duplex = FULL_DUPLEX;
3856 DEBUGOUT("Full Duplex\r\n");
3857 } else {
3858 *duplex = HALF_DUPLEX;
3859 DEBUGOUT(" Half Duplex\r\n");
3860 }
3861 } else {
3862 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3863 *speed = SPEED_1000;
3864 *duplex = FULL_DUPLEX;
3865 }
aa070789
RZ		 3866
3867 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3868 * even if it is operating at half duplex. Here we set the duplex
3869 * settings to match the duplex in the link partner's capabilities.
3870 */
3871 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3872 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3873 if (ret_val)
3874 return ret_val;
3875
3876 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3877 *duplex = HALF_DUPLEX;
3878 else {
3879 ret_val = e1000_read_phy_reg(hw,
3880 PHY_LP_ABILITY, &phy_data);
3881 if (ret_val)
3882 return ret_val;
3883 if ((*speed == SPEED_100 &&
3884 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3885 || (*speed == SPEED_10
3886 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3887 *duplex = HALF_DUPLEX;
3888 }
3889 }
3890
3891 if ((hw->mac_type == e1000_80003es2lan) &&
3892 (hw->media_type == e1000_media_type_copper)) {
3893 if (*speed == SPEED_1000)
3894 ret_val = e1000_configure_kmrn_for_1000(hw);
3895 else
3896 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3897 if (ret_val)
3898 return ret_val;
3899 }
3900 return E1000_SUCCESS;
682011ff
WD		 3901}
3902
3903/******************************************************************************
3904* Blocks until autoneg completes or times out (~4.5 seconds)
3905*
3906* hw - Struct containing variables accessed by shared code
3907******************************************************************************/
3908static int
3909e1000_wait_autoneg(struct e1000_hw *hw)
3910{
3911 uint16_t i;
3912 uint16_t phy_data;
3913
3914 DEBUGFUNC();
3915 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3916
3917 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3918 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3919 /* Read the MII Status Register and wait for Auto-Neg
3920 * Complete bit to be set.
3921 */
3922 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3923 DEBUGOUT("PHY Read Error\n");
3924 return -E1000_ERR_PHY;
3925 }
3926 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3927 DEBUGOUT("PHY Read Error\n");
3928 return -E1000_ERR_PHY;
3929 }
3930 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3931 DEBUGOUT("Auto-Neg complete.\n");
3932 return 0;
3933 }
3934 mdelay(100);
3935 }
3936 DEBUGOUT("Auto-Neg timedout.\n");
3937 return -E1000_ERR_TIMEOUT;
3938}
3939
3940/******************************************************************************
3941* Raises the Management Data Clock
3942*
3943* hw - Struct containing variables accessed by shared code
3944* ctrl - Device control register's current value
3945******************************************************************************/
3946static void
3947e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3948{
3949 /* Raise the clock input to the Management Data Clock (by setting the MDC
3950 * bit), and then delay 2 microseconds.
3951 */
3952 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3953 E1000_WRITE_FLUSH(hw);
3954 udelay(2);
3955}
3956
3957/******************************************************************************
3958* Lowers the Management Data Clock
3959*
3960* hw - Struct containing variables accessed by shared code
3961* ctrl - Device control register's current value
3962******************************************************************************/
3963static void
3964e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3965{
3966 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3967 * bit), and then delay 2 microseconds.
3968 */
3969 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3970 E1000_WRITE_FLUSH(hw);
3971 udelay(2);
3972}
3973
3974/******************************************************************************
3975* Shifts data bits out to the PHY
3976*
3977* hw - Struct containing variables accessed by shared code
3978* data - Data to send out to the PHY
3979* count - Number of bits to shift out
3980*
3981* Bits are shifted out in MSB to LSB order.
3982******************************************************************************/
3983static void
3984e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3985{
3986 uint32_t ctrl;
3987 uint32_t mask;
3988
3989 /* We need to shift "count" number of bits out to the PHY. So, the value
8bde7f77 3990 * in the "data" parameter will be shifted out to the PHY one bit at a
682011ff
WD		 3991 * time. In order to do this, "data" must be broken down into bits.
3992 */
3993 mask = 0x01;
3994 mask <<= (count - 1);
3995
3996 ctrl = E1000_READ_REG(hw, CTRL);
3997
3998 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3999 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4000
4001 while (mask) {
4002 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4003 * then raising and lowering the Management Data Clock. A "0" is
4004 * shifted out to the PHY by setting the MDIO bit to "0" and then
4005 * raising and lowering the clock.
4006 */
4007 if (data & mask)
4008 ctrl |= E1000_CTRL_MDIO;
4009 else
4010 ctrl &= ~E1000_CTRL_MDIO;
4011
4012 E1000_WRITE_REG(hw, CTRL, ctrl);
4013 E1000_WRITE_FLUSH(hw);
4014
4015 udelay(2);
4016
4017 e1000_raise_mdi_clk(hw, &ctrl);
4018 e1000_lower_mdi_clk(hw, &ctrl);
4019
4020 mask = mask >> 1;
4021 }
4022}
4023
4024/******************************************************************************
4025* Shifts data bits in from the PHY
4026*
4027* hw - Struct containing variables accessed by shared code
4028*
8bde7f77 4029* Bits are shifted in in MSB to LSB order.
682011ff
WD		 4030******************************************************************************/
4031static uint16_t
4032e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4033{
4034 uint32_t ctrl;
4035 uint16_t data = 0;
4036 uint8_t i;
4037
4038 /* In order to read a register from the PHY, we need to shift in a total
4039 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4040 * to avoid contention on the MDIO pin when a read operation is performed.
4041 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4042 * by raising the input to the Management Data Clock (setting the MDC bit),
4043 * and then reading the value of the MDIO bit.
4044 */
4045 ctrl = E1000_READ_REG(hw, CTRL);
4046
4047 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4048 ctrl &= ~E1000_CTRL_MDIO_DIR;
4049 ctrl &= ~E1000_CTRL_MDIO;
4050
4051 E1000_WRITE_REG(hw, CTRL, ctrl);
4052 E1000_WRITE_FLUSH(hw);
4053
4054 /* Raise and Lower the clock before reading in the data. This accounts for
4055 * the turnaround bits. The first clock occurred when we clocked out the
4056 * last bit of the Register Address.
4057 */
4058 e1000_raise_mdi_clk(hw, &ctrl);
4059 e1000_lower_mdi_clk(hw, &ctrl);
4060
4061 for (data = 0, i = 0; i < 16; i++) {
4062 data = data << 1;
4063 e1000_raise_mdi_clk(hw, &ctrl);
4064 ctrl = E1000_READ_REG(hw, CTRL);
4065 /* Check to see if we shifted in a "1". */
4066 if (ctrl & E1000_CTRL_MDIO)
4067 data |= 1;
4068 e1000_lower_mdi_clk(hw, &ctrl);
4069 }
4070
4071 e1000_raise_mdi_clk(hw, &ctrl);
4072 e1000_lower_mdi_clk(hw, &ctrl);
4073
4074 return data;
4075}
4076
4077/*****************************************************************************
4078* Reads the value from a PHY register
4079*
4080* hw - Struct containing variables accessed by shared code
4081* reg_addr - address of the PHY register to read
4082******************************************************************************/
4083static int
4084e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4085{
4086 uint32_t i;
4087 uint32_t mdic = 0;
4088 const uint32_t phy_addr = 1;
4089
4090 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4091 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4092 return -E1000_ERR_PARAM;
4093 }
4094
4095 if (hw->mac_type > e1000_82543) {
4096 /* Set up Op-code, Phy Address, and register address in the MDI
4097 * Control register. The MAC will take care of interfacing with the
4098 * PHY to retrieve the desired data.
4099 */
4100 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4101 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4102 (E1000_MDIC_OP_READ));
4103
4104 E1000_WRITE_REG(hw, MDIC, mdic);
4105
4106 /* Poll the ready bit to see if the MDI read completed */
4107 for (i = 0; i < 64; i++) {
4108 udelay(10);
4109 mdic = E1000_READ_REG(hw, MDIC);
4110 if (mdic & E1000_MDIC_READY)
4111 break;
4112 }
4113 if (!(mdic & E1000_MDIC_READY)) {
4114 DEBUGOUT("MDI Read did not complete\n");
4115 return -E1000_ERR_PHY;
4116 }
4117 if (mdic & E1000_MDIC_ERROR) {
4118 DEBUGOUT("MDI Error\n");
4119 return -E1000_ERR_PHY;
4120 }
4121 *phy_data = (uint16_t) mdic;
4122 } else {
4123 /* We must first send a preamble through the MDIO pin to signal the
4124 * beginning of an MII instruction. This is done by sending 32
4125 * consecutive "1" bits.
4126 */
4127 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4128
4129 /* Now combine the next few fields that are required for a read
4130 * operation. We use this method instead of calling the
4131 * e1000_shift_out_mdi_bits routine five different times. The format of
4132 * a MII read instruction consists of a shift out of 14 bits and is
4133 * defined as follows:
4134 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4135 * followed by a shift in of 18 bits. This first two bits shifted in
4136 * are TurnAround bits used to avoid contention on the MDIO pin when a
4137 * READ operation is performed. These two bits are thrown away
4138 * followed by a shift in of 16 bits which contains the desired data.
4139 */
4140 mdic = ((reg_addr) | (phy_addr << 5) |
4141 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4142
4143 e1000_shift_out_mdi_bits(hw, mdic, 14);
4144
4145 /* Now that we've shifted out the read command to the MII, we need to
4146 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4147 * register address.
4148 */
4149 *phy_data = e1000_shift_in_mdi_bits(hw);
4150 }
4151 return 0;
4152}
4153
4154/******************************************************************************
4155* Writes a value to a PHY register
4156*
4157* hw - Struct containing variables accessed by shared code
4158* reg_addr - address of the PHY register to write
4159* data - data to write to the PHY
4160******************************************************************************/
4161static int
4162e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4163{
4164 uint32_t i;
4165 uint32_t mdic = 0;
4166 const uint32_t phy_addr = 1;
4167
4168 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4169 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4170 return -E1000_ERR_PARAM;
4171 }
4172
4173 if (hw->mac_type > e1000_82543) {
4174 /* Set up Op-code, Phy Address, register address, and data intended
4175 * for the PHY register in the MDI Control register. The MAC will take
4176 * care of interfacing with the PHY to send the desired data.
4177 */
4178 mdic = (((uint32_t) phy_data) |
4179 (reg_addr << E1000_MDIC_REG_SHIFT) |
4180 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4181 (E1000_MDIC_OP_WRITE));
4182
4183 E1000_WRITE_REG(hw, MDIC, mdic);
4184
4185 /* Poll the ready bit to see if the MDI read completed */
4186 for (i = 0; i < 64; i++) {
4187 udelay(10);
4188 mdic = E1000_READ_REG(hw, MDIC);
4189 if (mdic & E1000_MDIC_READY)
4190 break;
4191 }
4192 if (!(mdic & E1000_MDIC_READY)) {
4193 DEBUGOUT("MDI Write did not complete\n");
4194 return -E1000_ERR_PHY;
4195 }
4196 } else {
4197 /* We'll need to use the SW defined pins to shift the write command
4198 * out to the PHY. We first send a preamble to the PHY to signal the
8bde7f77 4199 * beginning of the MII instruction. This is done by sending 32
682011ff
WD		 4200 * consecutive "1" bits.
4201 */
4202 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4203
8bde7f77 4204 /* Now combine the remaining required fields that will indicate a
682011ff
WD		 4205 * write operation. We use this method instead of calling the
4206 * e1000_shift_out_mdi_bits routine for each field in the command. The
4207 * format of a MII write instruction is as follows:
4208 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4209 */
4210 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4211 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4212 mdic <<= 16;
4213 mdic |= (uint32_t) phy_data;
4214
4215 e1000_shift_out_mdi_bits(hw, mdic, 32);
4216 }
4217 return 0;
4218}
4219
aa070789
RZ		 4220/******************************************************************************
4221 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4222 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4223 * the caller to figure out how to deal with it.
4224 *
4225 * hw - Struct containing variables accessed by shared code
4226 *
4227 * returns: - E1000_BLK_PHY_RESET
4228 * E1000_SUCCESS
4229 *
4230 *****************************************************************************/
4231int32_t
4232e1000_check_phy_reset_block(struct e1000_hw *hw)
4233{
4234 uint32_t manc = 0;
4235 uint32_t fwsm = 0;
4236
4237 if (hw->mac_type == e1000_ich8lan) {
4238 fwsm = E1000_READ_REG(hw, FWSM);
4239 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4240 : E1000_BLK_PHY_RESET;
4241 }
4242
4243 if (hw->mac_type > e1000_82547_rev_2)
4244 manc = E1000_READ_REG(hw, MANC);
4245 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4246 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4247}
4248
4249/***************************************************************************
4250 * Checks if the PHY configuration is done
4251 *
4252 * hw: Struct containing variables accessed by shared code
4253 *
4254 * returns: - E1000_ERR_RESET if fail to reset MAC
4255 * E1000_SUCCESS at any other case.
4256 *
4257 ***************************************************************************/
4258static int32_t
4259e1000_get_phy_cfg_done(struct e1000_hw *hw)
4260{
4261 int32_t timeout = PHY_CFG_TIMEOUT;
4262 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4263
4264 DEBUGFUNC();
4265
4266 switch (hw->mac_type) {
4267 default:
4268 mdelay(10);
4269 break;
4270 case e1000_80003es2lan:
4271 /* Separate *_CFG_DONE_* bit for each port */
4272 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4273 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4274 /* Fall Through */
4275 case e1000_82571:
4276 case e1000_82572:
4277 while (timeout) {
4278 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4279 break;
4280 else
4281 mdelay(1);
4282 timeout--;
4283 }
4284 if (!timeout) {
4285 DEBUGOUT("MNG configuration cycle has not "
4286 "completed.\n");
4287 return -E1000_ERR_RESET;
4288 }
4289 break;
4290 }
4291
4292 return E1000_SUCCESS;
4293}
4294
682011ff
WD		 4295/******************************************************************************
4296* Returns the PHY to the power-on reset state
4297*
4298* hw - Struct containing variables accessed by shared code
4299******************************************************************************/
aa070789 4300int32_t
682011ff
WD		 4301e1000_phy_hw_reset(struct e1000_hw *hw)
4302{
aa070789
RZ		 4303 uint32_t ctrl, ctrl_ext;
4304 uint32_t led_ctrl;
4305 int32_t ret_val;
4306 uint16_t swfw;
682011ff
WD		 4307
4308 DEBUGFUNC();
4309
aa070789
RZ		 4310 /* In the case of the phy reset being blocked, it's not an error, we
4311 * simply return success without performing the reset. */
4312 ret_val = e1000_check_phy_reset_block(hw);
4313 if (ret_val)
4314 return E1000_SUCCESS;
4315
682011ff
WD		 4316 DEBUGOUT("Resetting Phy...\n");
4317
4318 if (hw->mac_type > e1000_82543) {
aa070789
RZ		 4319 if ((hw->mac_type == e1000_80003es2lan) &&
4320 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
4321 swfw = E1000_SWFW_PHY1_SM;
4322 } else {
4323 swfw = E1000_SWFW_PHY0_SM;
4324 }
4325 if (e1000_swfw_sync_acquire(hw, swfw)) {
4326 DEBUGOUT("Unable to acquire swfw sync\n");
4327 return -E1000_ERR_SWFW_SYNC;
4328 }
682011ff
WD		 4329 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4330 * bit. Then, take it out of reset.
4331 */
4332 ctrl = E1000_READ_REG(hw, CTRL);
4333 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4334 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4335
4336 if (hw->mac_type < e1000_82571)
4337 udelay(10);
4338 else
4339 udelay(100);
4340
682011ff
WD		 4341 E1000_WRITE_REG(hw, CTRL, ctrl);
4342 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4343
4344 if (hw->mac_type >= e1000_82571)
4345 mdelay(10);
4346
682011ff
WD		 4347 } else {
4348 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4349 * bit to put the PHY into reset. Then, take it out of reset.
4350 */
4351 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4352 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4353 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4354 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4355 E1000_WRITE_FLUSH(hw);
4356 mdelay(10);
4357 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4358 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4359 E1000_WRITE_FLUSH(hw);
4360 }
4361 udelay(150);
aa070789
RZ		 4362
4363 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4364 /* Configure activity LED after PHY reset */
4365 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4366 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4367 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4368 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4369 }
4370
4371 /* Wait for FW to finish PHY configuration. */
4372 ret_val = e1000_get_phy_cfg_done(hw);
4373 if (ret_val != E1000_SUCCESS)
4374 return ret_val;
4375
4376 return ret_val;
4377}
4378
4379/******************************************************************************
4380 * IGP phy init script - initializes the GbE PHY
4381 *
4382 * hw - Struct containing variables accessed by shared code
4383 *****************************************************************************/
4384static void
4385e1000_phy_init_script(struct e1000_hw *hw)
4386{
4387 uint32_t ret_val;
4388 uint16_t phy_saved_data;
4389 DEBUGFUNC();
4390
4391 if (hw->phy_init_script) {
4392 mdelay(20);
4393
4394 /* Save off the current value of register 0x2F5B to be
4395 * restored at the end of this routine. */
4396 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4397
4398 /* Disabled the PHY transmitter */
4399 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4400
4401 mdelay(20);
4402
4403 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4404
4405 mdelay(5);
4406
4407 switch (hw->mac_type) {
4408 case e1000_82541:
4409 case e1000_82547:
4410 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4411
4412 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4413
4414 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4415
4416 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4417
4418 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4419
4420 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4421
4422 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4423
4424 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4425
4426 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4427 break;
4428
4429 case e1000_82541_rev_2:
4430 case e1000_82547_rev_2:
4431 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4432 break;
4433 default:
4434 break;
4435 }
4436
4437 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4438
4439 mdelay(20);
4440
4441 /* Now enable the transmitter */
4442 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4443
4444 if (hw->mac_type == e1000_82547) {
4445 uint16_t fused, fine, coarse;
4446
4447 /* Move to analog registers page */
4448 e1000_read_phy_reg(hw,
4449 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4450
4451 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4452 e1000_read_phy_reg(hw,
4453 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4454
4455 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4456 coarse = fused
4457 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4458
4459 if (coarse >
4460 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4461 coarse -=
4462 IGP01E1000_ANALOG_FUSE_COARSE_10;
4463 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4464 } else if (coarse
4465 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4466 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4467
4468 fused = (fused
4469 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4470 (fine
4471 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4472 (coarse
4473 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4474
4475 e1000_write_phy_reg(hw,
4476 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4477 e1000_write_phy_reg(hw,
4478 IGP01E1000_ANALOG_FUSE_BYPASS,
4479 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4480 }
4481 }
4482 }
682011ff
WD		 4483}
4484
4485/******************************************************************************
4486* Resets the PHY
4487*
4488* hw - Struct containing variables accessed by shared code
4489*
aa070789 4490* Sets bit 15 of the MII Control register
682011ff 4491******************************************************************************/
aa070789 4492int32_t
682011ff
WD		 4493e1000_phy_reset(struct e1000_hw *hw)
4494{
aa070789 4495 int32_t ret_val;
682011ff
WD		 4496 uint16_t phy_data;
4497
4498 DEBUGFUNC();
4499
aa070789
RZ		 4500 /* In the case of the phy reset being blocked, it's not an error, we
4501 * simply return success without performing the reset. */
4502 ret_val = e1000_check_phy_reset_block(hw);
4503 if (ret_val)
4504 return E1000_SUCCESS;
4505
4506 switch (hw->phy_type) {
4507 case e1000_phy_igp:
4508 case e1000_phy_igp_2:
4509 case e1000_phy_igp_3:
4510 case e1000_phy_ife:
4511 ret_val = e1000_phy_hw_reset(hw);
4512 if (ret_val)
4513 return ret_val;
4514 break;
4515 default:
4516 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4517 if (ret_val)
4518 return ret_val;
4519
4520 phy_data |= MII_CR_RESET;
4521 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4522 if (ret_val)
4523 return ret_val;
4524
4525 udelay(1);
4526 break;
682011ff 4527 }
aa070789
RZ		 4528
4529 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4530 e1000_phy_init_script(hw);
4531
4532 return E1000_SUCCESS;
682011ff
WD		 4533}
4534
1aeed8d7 4535static int e1000_set_phy_type (struct e1000_hw *hw)
ac3315c2 4536{
1aeed8d7
WD		 4537 DEBUGFUNC ();
4538
4539 if (hw->mac_type == e1000_undefined)
4540 return -E1000_ERR_PHY_TYPE;
4541
4542 switch (hw->phy_id) {
4543 case M88E1000_E_PHY_ID:
4544 case M88E1000_I_PHY_ID:
4545 case M88E1011_I_PHY_ID:
aa070789 4546 case M88E1111_I_PHY_ID:
1aeed8d7
WD		 4547 hw->phy_type = e1000_phy_m88;
4548 break;
4549 case IGP01E1000_I_PHY_ID:
4550 if (hw->mac_type == e1000_82541 ||
aa070789
RZ		 4551 hw->mac_type == e1000_82541_rev_2 ||
4552 hw->mac_type == e1000_82547 ||
4553 hw->mac_type == e1000_82547_rev_2) {
1aeed8d7 4554 hw->phy_type = e1000_phy_igp;
aa070789
RZ		 4555 hw->phy_type = e1000_phy_igp;
4556 break;
4557 }
4558 case IGP03E1000_E_PHY_ID:
4559 hw->phy_type = e1000_phy_igp_3;
4560 break;
4561 case IFE_E_PHY_ID:
4562 case IFE_PLUS_E_PHY_ID:
4563 case IFE_C_E_PHY_ID:
4564 hw->phy_type = e1000_phy_ife;
4565 break;
4566 case GG82563_E_PHY_ID:
4567 if (hw->mac_type == e1000_80003es2lan) {
4568 hw->phy_type = e1000_phy_gg82563;
1aeed8d7
WD		 4569 break;
4570 }
2c2668f9
RZ		 4571 case BME1000_E_PHY_ID:
4572 hw->phy_type = e1000_phy_bm;
4573 break;
1aeed8d7
WD		 4574 /* Fall Through */
4575 default:
4576 /* Should never have loaded on this device */
4577 hw->phy_type = e1000_phy_undefined;
4578 return -E1000_ERR_PHY_TYPE;
4579 }
4580
4581 return E1000_SUCCESS;
ac3315c2
AS		 4582}
4583
682011ff
WD		 4584/******************************************************************************
4585* Probes the expected PHY address for known PHY IDs
4586*
4587* hw - Struct containing variables accessed by shared code
4588******************************************************************************/
aa070789 4589static int32_t
682011ff
WD		 4590e1000_detect_gig_phy(struct e1000_hw *hw)
4591{
aa070789 4592 int32_t phy_init_status, ret_val;
682011ff 4593 uint16_t phy_id_high, phy_id_low;
aa070789 4594 boolean_t match = FALSE;
682011ff
WD		 4595
4596 DEBUGFUNC();
4597
aa070789
RZ		 4598 /* The 82571 firmware may still be configuring the PHY. In this
4599 * case, we cannot access the PHY until the configuration is done. So
4600 * we explicitly set the PHY values. */
4601 if (hw->mac_type == e1000_82571 ||
4602 hw->mac_type == e1000_82572) {
4603 hw->phy_id = IGP01E1000_I_PHY_ID;
4604 hw->phy_type = e1000_phy_igp_2;
4605 return E1000_SUCCESS;
682011ff 4606 }
aa070789
RZ		 4607
4608 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4609 * work- around that forces PHY page 0 to be set or the reads fail.
4610 * The rest of the code in this routine uses e1000_read_phy_reg to
4611 * read the PHY ID. So for ESB-2 we need to have this set so our
4612 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4613 * the routines below will figure this out as well. */
4614 if (hw->mac_type == e1000_80003es2lan)
4615 hw->phy_type = e1000_phy_gg82563;
4616
4617 /* Read the PHY ID Registers to identify which PHY is onboard. */
4618 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4619 if (ret_val)
4620 return ret_val;
4621
682011ff 4622 hw->phy_id = (uint32_t) (phy_id_high << 16);
aa070789
RZ		 4623 udelay(20);
4624 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4625 if (ret_val)
4626 return ret_val;
4627
682011ff 4628 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
aa070789 4629 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
682011ff
WD		 4630
4631 switch (hw->mac_type) {
4632 case e1000_82543:
4633 if (hw->phy_id == M88E1000_E_PHY_ID)
4634 match = TRUE;
4635 break;
4636 case e1000_82544:
4637 if (hw->phy_id == M88E1000_I_PHY_ID)
4638 match = TRUE;
4639 break;
4640 case e1000_82540:
4641 case e1000_82545:
aa070789 4642 case e1000_82545_rev_3:
682011ff 4643 case e1000_82546:
aa070789 4644 case e1000_82546_rev_3:
682011ff
WD		 4645 if (hw->phy_id == M88E1011_I_PHY_ID)
4646 match = TRUE;
4647 break;
aa070789 4648 case e1000_82541:
ac3315c2 4649 case e1000_82541_rev_2:
aa070789
RZ		 4650 case e1000_82547:
4651 case e1000_82547_rev_2:
ac3315c2
AS		 4652 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4653 match = TRUE;
4654
4655 break;
aa070789
RZ		 4656 case e1000_82573:
4657 if (hw->phy_id == M88E1111_I_PHY_ID)
4658 match = TRUE;
4659 break;
2c2668f9
RZ		 4660 case e1000_82574:
4661 if (hw->phy_id == BME1000_E_PHY_ID)
4662 match = TRUE;
4663 break;
aa070789
RZ		 4664 case e1000_80003es2lan:
4665 if (hw->phy_id == GG82563_E_PHY_ID)
4666 match = TRUE;
4667 break;
4668 case e1000_ich8lan:
4669 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4670 match = TRUE;
4671 if (hw->phy_id == IFE_E_PHY_ID)
4672 match = TRUE;
4673 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4674 match = TRUE;
4675 if (hw->phy_id == IFE_C_E_PHY_ID)
4676 match = TRUE;
4677 break;
682011ff
WD		 4678 default:
4679 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4680 return -E1000_ERR_CONFIG;
4681 }
ac3315c2
AS		 4682
4683 phy_init_status = e1000_set_phy_type(hw);
4684
4685 if ((match) && (phy_init_status == E1000_SUCCESS)) {
682011ff
WD		 4686 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4687 return 0;
4688 }
4689 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4690 return -E1000_ERR_PHY;
4691}
4692
aa070789
RZ		 4693/*****************************************************************************
4694 * Set media type and TBI compatibility.
4695 *
4696 * hw - Struct containing variables accessed by shared code
4697 * **************************************************************************/
4698void
4699e1000_set_media_type(struct e1000_hw *hw)
4700{
4701 uint32_t status;
4702
4703 DEBUGFUNC();
4704
4705 if (hw->mac_type != e1000_82543) {
4706 /* tbi_compatibility is only valid on 82543 */
4707 hw->tbi_compatibility_en = FALSE;
4708 }
4709
4710 switch (hw->device_id) {
4711 case E1000_DEV_ID_82545GM_SERDES:
4712 case E1000_DEV_ID_82546GB_SERDES:
4713 case E1000_DEV_ID_82571EB_SERDES:
4714 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4715 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4716 case E1000_DEV_ID_82572EI_SERDES:
4717 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4718 hw->media_type = e1000_media_type_internal_serdes;
4719 break;
4720 default:
4721 switch (hw->mac_type) {
4722 case e1000_82542_rev2_0:
4723 case e1000_82542_rev2_1:
4724 hw->media_type = e1000_media_type_fiber;
4725 break;
4726 case e1000_ich8lan:
4727 case e1000_82573:
2c2668f9 4728 case e1000_82574:
aa070789
RZ		 4729 /* The STATUS_TBIMODE bit is reserved or reused
4730 * for the this device.
4731 */
4732 hw->media_type = e1000_media_type_copper;
4733 break;
4734 default:
4735 status = E1000_READ_REG(hw, STATUS);
4736 if (status & E1000_STATUS_TBIMODE) {
4737 hw->media_type = e1000_media_type_fiber;
4738 /* tbi_compatibility not valid on fiber */
4739 hw->tbi_compatibility_en = FALSE;
4740 } else {
4741 hw->media_type = e1000_media_type_copper;
4742 }
4743 break;
4744 }
4745 }
4746}
4747
682011ff
WD		 4748/**
4749 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4750 *
4751 * e1000_sw_init initializes the Adapter private data structure.
4752 * Fields are initialized based on PCI device information and
4753 * OS network device settings (MTU size).
4754 **/
4755
4756static int
4757e1000_sw_init(struct eth_device *nic, int cardnum)
4758{
4759 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4760 int result;
4761
4762 /* PCI config space info */
4763 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4764 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4765 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4766 &hw->subsystem_vendor_id);
4767 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4768
4769 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4770 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4771
4772 /* identify the MAC */
4773 result = e1000_set_mac_type(hw);
4774 if (result) {
4775 E1000_ERR("Unknown MAC Type\n");
4776 return result;
4777 }
4778
aa070789
RZ		 4779 switch (hw->mac_type) {
4780 default:
4781 break;
4782 case e1000_82541:
4783 case e1000_82547:
4784 case e1000_82541_rev_2:
4785 case e1000_82547_rev_2:
4786 hw->phy_init_script = 1;
4787 break;
4788 }
4789
682011ff
WD		 4790 /* lan a vs. lan b settings */
4791 if (hw->mac_type == e1000_82546)
4792 /*this also works w/ multiple 82546 cards */
4793 /*but not if they're intermingled /w other e1000s */
4794 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
4795 else
4796 hw->lan_loc = e1000_lan_a;
4797
4798 /* flow control settings */
4799 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4800 hw->fc_low_water = E1000_FC_LOW_THRESH;
4801 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4802 hw->fc_send_xon = 1;
4803
4804 /* Media type - copper or fiber */
aa070789 4805 e1000_set_media_type(hw);
682011ff
WD		 4806
4807 if (hw->mac_type >= e1000_82543) {
4808 uint32_t status = E1000_READ_REG(hw, STATUS);
4809
4810 if (status & E1000_STATUS_TBIMODE) {
4811 DEBUGOUT("fiber interface\n");
4812 hw->media_type = e1000_media_type_fiber;
4813 } else {
4814 DEBUGOUT("copper interface\n");
4815 hw->media_type = e1000_media_type_copper;
4816 }
4817 } else {
4818 hw->media_type = e1000_media_type_fiber;
4819 }
4820
aa070789
RZ		 4821 hw->tbi_compatibility_en = TRUE;
4822 hw->wait_autoneg_complete = TRUE;
682011ff
WD		 4823 if (hw->mac_type < e1000_82543)
4824 hw->report_tx_early = 0;
4825 else
4826 hw->report_tx_early = 1;
4827
682011ff
WD		 4828 return E1000_SUCCESS;
4829}
4830
4831void
4832fill_rx(struct e1000_hw *hw)
4833{
4834 struct e1000_rx_desc *rd;
4835
4836 rx_last = rx_tail;
4837 rd = rx_base + rx_tail;
4838 rx_tail = (rx_tail + 1) % 8;
4839 memset(rd, 0, 16);
4840 rd->buffer_addr = cpu_to_le64((u32) & packet);
4841 E1000_WRITE_REG(hw, RDT, rx_tail);
4842}
4843
4844/**
4845 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4846 * @adapter: board private structure
4847 *
4848 * Configure the Tx unit of the MAC after a reset.
4849 **/
4850
4851static void
4852e1000_configure_tx(struct e1000_hw *hw)
4853{
4854 unsigned long ptr;
4855 unsigned long tctl;
aa070789
RZ		 4856 unsigned long tipg, tarc;
4857 uint32_t ipgr1, ipgr2;
682011ff
WD		 4858
4859 ptr = (u32) tx_pool;
4860 if (ptr & 0xf)
4861 ptr = (ptr + 0x10) & (~0xf);
4862
4863 tx_base = (typeof(tx_base)) ptr;
4864
4865 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4866 E1000_WRITE_REG(hw, TDBAH, 0);
4867
4868 E1000_WRITE_REG(hw, TDLEN, 128);
4869
4870 /* Setup the HW Tx Head and Tail descriptor pointers */
4871 E1000_WRITE_REG(hw, TDH, 0);
4872 E1000_WRITE_REG(hw, TDT, 0);
4873 tx_tail = 0;
4874
aa070789
RZ		 4875 /* Set the default values for the Tx Inter Packet Gap timer */
4876 if (hw->mac_type <= e1000_82547_rev_2 &&
4877 (hw->media_type == e1000_media_type_fiber ||
4878 hw->media_type == e1000_media_type_internal_serdes))
4879 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4880 else
4881 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4882
682011ff
WD		 4883 /* Set the default values for the Tx Inter Packet Gap timer */
4884 switch (hw->mac_type) {
4885 case e1000_82542_rev2_0:
4886 case e1000_82542_rev2_1:
4887 tipg = DEFAULT_82542_TIPG_IPGT;
aa070789
RZ		 4888 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4889 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4890 break;
4891 case e1000_80003es2lan:
4892 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4893 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
682011ff
WD		 4894 break;
4895 default:
aa070789
RZ		 4896 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4897 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4898 break;
682011ff 4899 }
aa070789
RZ		 4900 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4901 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
682011ff 4902 E1000_WRITE_REG(hw, TIPG, tipg);
682011ff
WD		 4903 /* Program the Transmit Control Register */
4904 tctl = E1000_READ_REG(hw, TCTL);
4905 tctl &= ~E1000_TCTL_CT;
4906 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4907 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
aa070789
RZ		 4908
4909 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4910 tarc = E1000_READ_REG(hw, TARC0);
4911 /* set the speed mode bit, we'll clear it if we're not at
4912 * gigabit link later */
4913 /* git bit can be set to 1*/
4914 } else if (hw->mac_type == e1000_80003es2lan) {
4915 tarc = E1000_READ_REG(hw, TARC0);
4916 tarc |= 1;
4917 E1000_WRITE_REG(hw, TARC0, tarc);
4918 tarc = E1000_READ_REG(hw, TARC1);
4919 tarc |= 1;
4920 E1000_WRITE_REG(hw, TARC1, tarc);
4921 }
4922
682011ff
WD		 4923
4924 e1000_config_collision_dist(hw);
aa070789
RZ		 4925 /* Setup Transmit Descriptor Settings for eop descriptor */
4926 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
682011ff 4927
aa070789
RZ		 4928 /* Need to set up RS bit */
4929 if (hw->mac_type < e1000_82543)
4930 hw->txd_cmd |= E1000_TXD_CMD_RPS;
682011ff 4931 else
aa070789
RZ		 4932 hw->txd_cmd |= E1000_TXD_CMD_RS;
4933 E1000_WRITE_REG(hw, TCTL, tctl);
682011ff
WD		 4934}
4935
4936/**
4937 * e1000_setup_rctl - configure the receive control register
4938 * @adapter: Board private structure
4939 **/
4940static void
4941e1000_setup_rctl(struct e1000_hw *hw)
4942{
4943 uint32_t rctl;
4944
4945 rctl = E1000_READ_REG(hw, RCTL);
4946
4947 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4948
aa070789
RZ		 4949 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4950 | E1000_RCTL_RDMTS_HALF; /* |
4951 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
682011ff
WD		 4952
4953 if (hw->tbi_compatibility_on == 1)
4954 rctl |= E1000_RCTL_SBP;
4955 else
4956 rctl &= ~E1000_RCTL_SBP;
4957
4958 rctl &= ~(E1000_RCTL_SZ_4096);
682011ff
WD		 4959 rctl |= E1000_RCTL_SZ_2048;
4960 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
682011ff
WD		 4961 E1000_WRITE_REG(hw, RCTL, rctl);
4962}
4963
4964/**
4965 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4966 * @adapter: board private structure
4967 *
4968 * Configure the Rx unit of the MAC after a reset.
4969 **/
4970static void
4971e1000_configure_rx(struct e1000_hw *hw)
4972{
4973 unsigned long ptr;
aa070789 4974 unsigned long rctl, ctrl_ext;
682011ff
WD		 4975 rx_tail = 0;
4976 /* make sure receives are disabled while setting up the descriptors */
4977 rctl = E1000_READ_REG(hw, RCTL);
4978 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
682011ff 4979 if (hw->mac_type >= e1000_82540) {
682011ff
WD		 4980 /* Set the interrupt throttling rate. Value is calculated
4981 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
1aeed8d7
WD		 4982#define MAX_INTS_PER_SEC 8000
4983#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
682011ff
WD		 4984 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4985 }
4986
aa070789
RZ		 4987 if (hw->mac_type >= e1000_82571) {
4988 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4989 /* Reset delay timers after every interrupt */
4990 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4991 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4992 E1000_WRITE_FLUSH(hw);
4993 }
682011ff
WD		 4994 /* Setup the Base and Length of the Rx Descriptor Ring */
4995 ptr = (u32) rx_pool;
4996 if (ptr & 0xf)
4997 ptr = (ptr + 0x10) & (~0xf);
4998 rx_base = (typeof(rx_base)) ptr;
4999 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
5000 E1000_WRITE_REG(hw, RDBAH, 0);
5001
5002 E1000_WRITE_REG(hw, RDLEN, 128);
5003
5004 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5005 E1000_WRITE_REG(hw, RDH, 0);
5006 E1000_WRITE_REG(hw, RDT, 0);
682011ff
WD		 5007 /* Enable Receives */
5008
5009 E1000_WRITE_REG(hw, RCTL, rctl);
5010 fill_rx(hw);
5011}
5012
5013/**************************************************************************
5014POLL - Wait for a frame
5015***************************************************************************/
5016static int
5017e1000_poll(struct eth_device *nic)
5018{
5019 struct e1000_hw *hw = nic->priv;
5020 struct e1000_rx_desc *rd;
5021 /* return true if there's an ethernet packet ready to read */
5022 rd = rx_base + rx_last;
5023 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5024 return 0;
5025 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
77ddac94 5026 NetReceive((uchar *)packet, le32_to_cpu(rd->length));
682011ff
WD		 5027 fill_rx(hw);
5028 return 1;
5029}
5030
5031/**************************************************************************
5032TRANSMIT - Transmit a frame
5033***************************************************************************/
5034static int
5035e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5036{
8aa858cb 5037 void * nv_packet = (void *)packet;
682011ff
WD		 5038 struct e1000_hw *hw = nic->priv;
5039 struct e1000_tx_desc *txp;
5040 int i = 0;
5041
5042 txp = tx_base + tx_tail;
5043 tx_tail = (tx_tail + 1) % 8;
5044
8aa858cb 5045 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
aa070789 5046 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
682011ff
WD		 5047 txp->upper.data = 0;
5048 E1000_WRITE_REG(hw, TDT, tx_tail);
5049
aa070789 5050 E1000_WRITE_FLUSH(hw);
682011ff
WD		 5051 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5052 if (i++ > TOUT_LOOP) {
5053 DEBUGOUT("e1000: tx timeout\n");
5054 return 0;
5055 }
5056 udelay(10); /* give the nic a chance to write to the register */
5057 }
5058 return 1;
5059}
5060
5061/*reset function*/
5062static inline int
5063e1000_reset(struct eth_device *nic)
5064{
5065 struct e1000_hw *hw = nic->priv;
5066
5067 e1000_reset_hw(hw);
5068 if (hw->mac_type >= e1000_82544) {
5069 E1000_WRITE_REG(hw, WUC, 0);
5070 }
5071 return e1000_init_hw(nic);
5072}
5073
5074/**************************************************************************
5075DISABLE - Turn off ethernet interface
5076***************************************************************************/
5077static void
5078e1000_disable(struct eth_device *nic)
5079{
5080 struct e1000_hw *hw = nic->priv;
5081
5082 /* Turn off the ethernet interface */
5083 E1000_WRITE_REG(hw, RCTL, 0);
5084 E1000_WRITE_REG(hw, TCTL, 0);
5085
5086 /* Clear the transmit ring */
5087 E1000_WRITE_REG(hw, TDH, 0);
5088 E1000_WRITE_REG(hw, TDT, 0);
5089
5090 /* Clear the receive ring */
5091 E1000_WRITE_REG(hw, RDH, 0);
5092 E1000_WRITE_REG(hw, RDT, 0);
5093
5094 /* put the card in its initial state */
5095#if 0
5096 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5097#endif
5098 mdelay(10);
5099
5100}
5101
5102/**************************************************************************
5103INIT - set up ethernet interface(s)
5104***************************************************************************/
5105static int
5106e1000_init(struct eth_device *nic, bd_t * bis)
5107{
5108 struct e1000_hw *hw = nic->priv;
5109 int ret_val = 0;
5110
5111 ret_val = e1000_reset(nic);
5112 if (ret_val < 0) {
5113 if ((ret_val == -E1000_ERR_NOLINK) ||
5114 (ret_val == -E1000_ERR_TIMEOUT)) {
5115 E1000_ERR("Valid Link not detected\n");
5116 } else {
5117 E1000_ERR("Hardware Initialization Failed\n");
5118 }
5119 return 0;
5120 }
5121 e1000_configure_tx(hw);
5122 e1000_setup_rctl(hw);
5123 e1000_configure_rx(hw);
5124 return 1;
5125}
5126
aa070789
RZ		 5127/******************************************************************************
5128 * Gets the current PCI bus type of hardware
5129 *
5130 * hw - Struct containing variables accessed by shared code
5131 *****************************************************************************/
5132void e1000_get_bus_type(struct e1000_hw *hw)
5133{
5134 uint32_t status;
5135
5136 switch (hw->mac_type) {
5137 case e1000_82542_rev2_0:
5138 case e1000_82542_rev2_1:
5139 hw->bus_type = e1000_bus_type_pci;
5140 break;
5141 case e1000_82571:
5142 case e1000_82572:
5143 case e1000_82573:
2c2668f9 5144 case e1000_82574:
aa070789
RZ		 5145 case e1000_80003es2lan:
5146 hw->bus_type = e1000_bus_type_pci_express;
5147 break;
5148 case e1000_ich8lan:
5149 hw->bus_type = e1000_bus_type_pci_express;
5150 break;
5151 default:
5152 status = E1000_READ_REG(hw, STATUS);
5153 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5154 e1000_bus_type_pcix : e1000_bus_type_pci;
5155 break;
5156 }
5157}
5158
682011ff
WD		 5159/**************************************************************************
5160PROBE - Look for an adapter, this routine's visible to the outside
5161You should omit the last argument struct pci_device * for a non-PCI NIC
5162***************************************************************************/
5163int
5164e1000_initialize(bd_t * bis)
5165{
5166 pci_dev_t devno;
5167 int card_number = 0;
5168 struct eth_device *nic = NULL;
5169 struct e1000_hw *hw = NULL;
5170 u32 iobase;
5171 int idx = 0;
5172 u32 PciCommandWord;
5173
f81ecb5d
TT		 5174 DEBUGFUNC();
5175
682011ff
WD		 5176 while (1) { /* Find PCI device(s) */
5177 if ((devno = pci_find_devices(supported, idx++)) < 0) {
5178 break;
5179 }
5180
5181 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
5182 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
5183 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
5184
5185 pci_write_config_dword(devno, PCI_COMMAND,
5186 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
5187 /* Check if I/O accesses and Bus Mastering are enabled. */
5188 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
5189 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
5190 printf("Error: Can not enable MEM access.\n");
5191 continue;
5192 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
5193 printf("Error: Can not enable Bus Mastering.\n");
5194 continue;
5195 }
5196
5197 nic = (struct eth_device *) malloc(sizeof (*nic));
4b29bdb0
KG		 5198 if (!nic) {
5199 printf("Error: e1000 - Can not alloc memory\n");
5200 return 0;
5201 }
5202
682011ff 5203 hw = (struct e1000_hw *) malloc(sizeof (*hw));
4b29bdb0
KG		 5204 if (!hw) {
5205 free(nic);
5206 printf("Error: e1000 - Can not alloc memory\n");
5207 return 0;
5208 }
5209
f7ac99fd 5210 memset(nic, 0, sizeof(*nic));
4b29bdb0
KG		 5211 memset(hw, 0, sizeof(*hw));
5212
682011ff
WD		 5213 hw->pdev = devno;
5214 nic->priv = hw;
682011ff
WD		 5215
5216 sprintf(nic->name, "e1000#%d", card_number);
5217
5218 /* Are these variables needed? */
682011ff
WD		 5219 hw->fc = e1000_fc_default;
5220 hw->original_fc = e1000_fc_default;
682011ff 5221 hw->autoneg_failed = 0;
aa070789 5222 hw->autoneg = 1;
682011ff 5223 hw->get_link_status = TRUE;
f81ecb5d
TT		 5224 hw->hw_addr =
5225 pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
682011ff
WD		 5226 hw->mac_type = e1000_undefined;
5227
5228 /* MAC and Phy settings */
5229 if (e1000_sw_init(nic, card_number) < 0) {
5230 free(hw);
5231 free(nic);
5232 return 0;
5233 }
aa070789
RZ		 5234 if (e1000_check_phy_reset_block(hw))
5235 printf("phy reset block error \n");
5236 e1000_reset_hw(hw);
ac3315c2 5237#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
aa070789
RZ		 5238 if (e1000_init_eeprom_params(hw)) {
5239 printf("The EEPROM Checksum Is Not Valid\n");
5240 free(hw);
5241 free(nic);
5242 return 0;
5243 }
682011ff
WD		 5244 if (e1000_validate_eeprom_checksum(nic) < 0) {
5245 printf("The EEPROM Checksum Is Not Valid\n");
5246 free(hw);
5247 free(nic);
5248 return 0;
5249 }
7521af1c 5250#endif
682011ff
WD		 5251 e1000_read_mac_addr(nic);
5252
aa070789
RZ		 5253 /* get the bus type information */
5254 e1000_get_bus_type(hw);
682011ff
WD		 5255
5256 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
5257 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5258 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5259
5260 nic->init = e1000_init;
5261 nic->recv = e1000_poll;
5262 nic->send = e1000_transmit;
5263 nic->halt = e1000_disable;
5264
5265 eth_register(nic);
5266
5267 card_number++;
5268 }
ad3381cf 5269 return card_number;
682011ff 5270}
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