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Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header
[people/ms/u-boot.git] / drivers / net / e1000.c
CommitLineData
682011ff 1/**************************************************************************
ac3315c2 2Intel Pro 1000 for ppcboot/das-u-boot
682011ff
WD		 3Drivers are port from Intel's Linux driver e1000-4.3.15
4and from Etherboot pro 1000 driver by mrakes at vivato dot net
5tested on both gig copper and gig fiber boards
6***************************************************************************/
7/*******************************************************************************
8
8bde7f77 9
682011ff 10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
8bde7f77 11
1a459660 12 * SPDX-License-Identifier: GPL-2.0+
8bde7f77 13
682011ff
WD		 14 Contact Information:
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
17
18*******************************************************************************/
19/*
20 * Copyright (C) Archway Digital Solutions.
21 *
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
23 * 2/9/2002
24 *
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
2c2668f9
RZ		 28 *
29 * Copyright 2011 Freescale Semiconductor, Inc.
682011ff
WD		 30 */
31
c752cd2a 32#include <common.h>
c6d80a15 33#include <dm.h>
5c5e707a 34#include <errno.h>
cf92e05c 35#include <memalign.h>
5c5e707a 36#include <pci.h>
682011ff
WD		 37#include "e1000.h"
38
682011ff
WD		 39#define TOUT_LOOP 100000
40
f81ecb5d 41#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
682011ff 42#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
682011ff 43
9ea005fb
RZ		 44#define E1000_DEFAULT_PCI_PBA 0x00000030
45#define E1000_DEFAULT_PCIE_PBA 0x000a0026
682011ff
WD		 46
47/* NIC specific static variables go here */
48
873e8e01
MV		 49/* Intel i210 needs the DMA descriptor rings aligned to 128b */
50#define E1000_BUFFER_ALIGN 128
682011ff 51
c6d80a15
SG		 52/*
53 * TODO(sjg@chromium.org): Even with driver model we share these buffers.
54 * Concurrent receiving on multiple active Ethernet devices will not work.
55 * Normally U-Boot does not support this anyway. To fix it in this driver,
56 * move these buffers and the tx/rx pointers to struct e1000_hw.
57 */
873e8e01
MV		 58DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
59DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
60DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
682011ff
WD		 61
62static int tx_tail;
63static int rx_tail, rx_last;
c6d80a15
SG		 64#ifdef CONFIG_DM_ETH
65static int num_cards; /* Number of E1000 devices seen so far */
66#endif
682011ff 67
d60626f8 68static struct pci_device_id e1000_supported[] = {
5c5e707a
SG		 69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
70 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
75 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
aa070789 86 /* E1000 PCIe card */
5c5e707a
SG		 87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
95186063 117
1bc43437 118 {}
682011ff
WD		 119};
120
121/* Function forward declarations */
5c5e707a
SG		 122static int e1000_setup_link(struct e1000_hw *hw);
123static int e1000_setup_fiber_link(struct e1000_hw *hw);
124static int e1000_setup_copper_link(struct e1000_hw *hw);
682011ff
WD		 125static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
126static void e1000_config_collision_dist(struct e1000_hw *hw);
127static int e1000_config_mac_to_phy(struct e1000_hw *hw);
128static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
5c5e707a 129static int e1000_check_for_link(struct e1000_hw *hw);
682011ff 130static int e1000_wait_autoneg(struct e1000_hw *hw);
aa070789 131static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
682011ff
WD		 132 uint16_t * duplex);
133static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
134 uint16_t * phy_data);
135static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
136 uint16_t phy_data);
aa070789 137static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
682011ff
WD		 138static int e1000_phy_reset(struct e1000_hw *hw);
139static int e1000_detect_gig_phy(struct e1000_hw *hw);
aa070789
RZ		 140static void e1000_set_media_type(struct e1000_hw *hw);
141
142static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
7e2d991d 143static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
aa070789 144static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
682011ff 145
8712adfd
RI		 146#ifndef CONFIG_E1000_NO_NVM
147static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
ecbd2078
RZ		 148static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
149 uint16_t words,
150 uint16_t *data);
682011ff
WD		 151/******************************************************************************
152 * Raises the EEPROM's clock input.
153 *
154 * hw - Struct containing variables accessed by shared code
155 * eecd - EECD's current value
156 *****************************************************************************/
2326a94d 157void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
682011ff
WD		 158{
159 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
160 * wait 50 microseconds.
161 */
162 *eecd = *eecd | E1000_EECD_SK;
163 E1000_WRITE_REG(hw, EECD, *eecd);
164 E1000_WRITE_FLUSH(hw);
165 udelay(50);
166}
167
168/******************************************************************************
169 * Lowers the EEPROM's clock input.
170 *
8bde7f77 171 * hw - Struct containing variables accessed by shared code
682011ff
WD		 172 * eecd - EECD's current value
173 *****************************************************************************/
2326a94d 174void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
682011ff 175{
8bde7f77
WD		 176 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
177 * wait 50 microseconds.
682011ff
WD		 178 */
179 *eecd = *eecd & ~E1000_EECD_SK;
180 E1000_WRITE_REG(hw, EECD, *eecd);
181 E1000_WRITE_FLUSH(hw);
182 udelay(50);
183}
184
185/******************************************************************************
186 * Shift data bits out to the EEPROM.
187 *
188 * hw - Struct containing variables accessed by shared code
189 * data - data to send to the EEPROM
190 * count - number of bits to shift out
191 *****************************************************************************/
192static void
193e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
194{
195 uint32_t eecd;
196 uint32_t mask;
197
198 /* We need to shift "count" bits out to the EEPROM. So, value in the
199 * "data" parameter will be shifted out to the EEPROM one bit at a time.
8bde7f77 200 * In order to do this, "data" must be broken down into bits.
682011ff
WD		 201 */
202 mask = 0x01 << (count - 1);
203 eecd = E1000_READ_REG(hw, EECD);
204 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
205 do {
206 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
207 * and then raising and then lowering the clock (the SK bit controls
208 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
209 * by setting "DI" to "0" and then raising and then lowering the clock.
210 */
211 eecd &= ~E1000_EECD_DI;
212
213 if (data & mask)
214 eecd |= E1000_EECD_DI;
215
216 E1000_WRITE_REG(hw, EECD, eecd);
217 E1000_WRITE_FLUSH(hw);
218
219 udelay(50);
220
221 e1000_raise_ee_clk(hw, &eecd);
222 e1000_lower_ee_clk(hw, &eecd);
223
224 mask = mask >> 1;
225
226 } while (mask);
227
228 /* We leave the "DI" bit set to "0" when we leave this routine. */
229 eecd &= ~E1000_EECD_DI;
230 E1000_WRITE_REG(hw, EECD, eecd);
231}
232
233/******************************************************************************
234 * Shift data bits in from the EEPROM
235 *
236 * hw - Struct containing variables accessed by shared code
237 *****************************************************************************/
238static uint16_t
aa070789 239e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
682011ff
WD		 240{
241 uint32_t eecd;
242 uint32_t i;
243 uint16_t data;
244
aa070789
RZ		 245 /* In order to read a register from the EEPROM, we need to shift 'count'
246 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
247 * input to the EEPROM (setting the SK bit), and then reading the
248 * value of the "DO" bit. During this "shifting in" process the
249 * "DI" bit should always be clear.
682011ff
WD		 250 */
251
252 eecd = E1000_READ_REG(hw, EECD);
253
254 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
255 data = 0;
256
aa070789 257 for (i = 0; i < count; i++) {
682011ff
WD		 258 data = data << 1;
259 e1000_raise_ee_clk(hw, &eecd);
260
261 eecd = E1000_READ_REG(hw, EECD);
262
263 eecd &= ~(E1000_EECD_DI);
264 if (eecd & E1000_EECD_DO)
265 data |= 1;
266
267 e1000_lower_ee_clk(hw, &eecd);
268 }
269
270 return data;
271}
272
273/******************************************************************************
aa070789 274 * Returns EEPROM to a "standby" state
682011ff
WD		 275 *
276 * hw - Struct containing variables accessed by shared code
682011ff 277 *****************************************************************************/
2326a94d 278void e1000_standby_eeprom(struct e1000_hw *hw)
682011ff 279{
aa070789 280 struct e1000_eeprom_info *eeprom = &hw->eeprom;
682011ff
WD		 281 uint32_t eecd;
282
283 eecd = E1000_READ_REG(hw, EECD);
284
aa070789
RZ		 285 if (eeprom->type == e1000_eeprom_microwire) {
286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
287 E1000_WRITE_REG(hw, EECD, eecd);
288 E1000_WRITE_FLUSH(hw);
289 udelay(eeprom->delay_usec);
682011ff 290
aa070789
RZ		 291 /* Clock high */
292 eecd |= E1000_EECD_SK;
293 E1000_WRITE_REG(hw, EECD, eecd);
294 E1000_WRITE_FLUSH(hw);
295 udelay(eeprom->delay_usec);
296
297 /* Select EEPROM */
298 eecd |= E1000_EECD_CS;
299 E1000_WRITE_REG(hw, EECD, eecd);
300 E1000_WRITE_FLUSH(hw);
301 udelay(eeprom->delay_usec);
302
303 /* Clock low */
304 eecd &= ~E1000_EECD_SK;
305 E1000_WRITE_REG(hw, EECD, eecd);
306 E1000_WRITE_FLUSH(hw);
307 udelay(eeprom->delay_usec);
308 } else if (eeprom->type == e1000_eeprom_spi) {
309 /* Toggle CS to flush commands */
310 eecd |= E1000_EECD_CS;
311 E1000_WRITE_REG(hw, EECD, eecd);
312 E1000_WRITE_FLUSH(hw);
313 udelay(eeprom->delay_usec);
314 eecd &= ~E1000_EECD_CS;
315 E1000_WRITE_REG(hw, EECD, eecd);
316 E1000_WRITE_FLUSH(hw);
317 udelay(eeprom->delay_usec);
318 }
319}
320
321/***************************************************************************
322* Description: Determines if the onboard NVM is FLASH or EEPROM.
323*
324* hw - Struct containing variables accessed by shared code
325****************************************************************************/
472d5460 326static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
aa070789
RZ		 327{
328 uint32_t eecd = 0;
329
330 DEBUGFUNC();
331
332 if (hw->mac_type == e1000_ich8lan)
472d5460 333 return false;
aa070789 334
2c2668f9 335 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
aa070789
RZ		 336 eecd = E1000_READ_REG(hw, EECD);
337
338 /* Isolate bits 15 & 16 */
339 eecd = ((eecd >> 15) & 0x03);
340
341 /* If both bits are set, device is Flash type */
342 if (eecd == 0x03)
472d5460 343 return false;
aa070789 344 }
472d5460 345 return true;
682011ff
WD		 346}
347
348/******************************************************************************
aa070789 349 * Prepares EEPROM for access
8bde7f77 350 *
682011ff 351 * hw - Struct containing variables accessed by shared code
aa070789
RZ		 352 *
353 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
354 * function should be called before issuing a command to the EEPROM.
682011ff 355 *****************************************************************************/
2326a94d 356int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
682011ff 357{
aa070789
RZ		 358 struct e1000_eeprom_info *eeprom = &hw->eeprom;
359 uint32_t eecd, i = 0;
682011ff 360
f81ecb5d 361 DEBUGFUNC();
aa070789
RZ		 362
363 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
364 return -E1000_ERR_SWFW_SYNC;
682011ff
WD		 365 eecd = E1000_READ_REG(hw, EECD);
366
95186063 367 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
aa070789
RZ		 368 /* Request EEPROM Access */
369 if (hw->mac_type > e1000_82544) {
370 eecd |= E1000_EECD_REQ;
371 E1000_WRITE_REG(hw, EECD, eecd);
372 eecd = E1000_READ_REG(hw, EECD);
373 while ((!(eecd & E1000_EECD_GNT)) &&
374 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
375 i++;
376 udelay(5);
377 eecd = E1000_READ_REG(hw, EECD);
378 }
379 if (!(eecd & E1000_EECD_GNT)) {
380 eecd &= ~E1000_EECD_REQ;
381 E1000_WRITE_REG(hw, EECD, eecd);
382 DEBUGOUT("Could not acquire EEPROM grant\n");
383 return -E1000_ERR_EEPROM;
384 }
385 }
386 }
682011ff 387
aa070789 388 /* Setup EEPROM for Read/Write */
682011ff 389
aa070789
RZ		 390 if (eeprom->type == e1000_eeprom_microwire) {
391 /* Clear SK and DI */
392 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
393 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 394
aa070789
RZ		 395 /* Set CS */
396 eecd |= E1000_EECD_CS;
397 E1000_WRITE_REG(hw, EECD, eecd);
398 } else if (eeprom->type == e1000_eeprom_spi) {
399 /* Clear SK and CS */
400 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
401 E1000_WRITE_REG(hw, EECD, eecd);
402 udelay(1);
403 }
404
405 return E1000_SUCCESS;
682011ff
WD		 406}
407
408/******************************************************************************
aa070789
RZ		 409 * Sets up eeprom variables in the hw struct. Must be called after mac_type
410 * is configured. Additionally, if this is ICH8, the flash controller GbE
411 * registers must be mapped, or this will crash.
682011ff
WD		 412 *
413 * hw - Struct containing variables accessed by shared code
682011ff 414 *****************************************************************************/
aa070789 415static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
682011ff 416{
aa070789 417 struct e1000_eeprom_info *eeprom = &hw->eeprom;
95186063 418 uint32_t eecd;
aa070789
RZ		 419 int32_t ret_val = E1000_SUCCESS;
420 uint16_t eeprom_size;
682011ff 421
95186063
MV		 422 if (hw->mac_type == e1000_igb)
423 eecd = E1000_READ_REG(hw, I210_EECD);
424 else
425 eecd = E1000_READ_REG(hw, EECD);
426
f81ecb5d 427 DEBUGFUNC();
aa070789
RZ		 428
429 switch (hw->mac_type) {
430 case e1000_82542_rev2_0:
431 case e1000_82542_rev2_1:
432 case e1000_82543:
433 case e1000_82544:
434 eeprom->type = e1000_eeprom_microwire;
435 eeprom->word_size = 64;
436 eeprom->opcode_bits = 3;
437 eeprom->address_bits = 6;
438 eeprom->delay_usec = 50;
472d5460
YS		 439 eeprom->use_eerd = false;
440 eeprom->use_eewr = false;
aa070789
RZ		 441 break;
442 case e1000_82540:
443 case e1000_82545:
444 case e1000_82545_rev_3:
445 case e1000_82546:
446 case e1000_82546_rev_3:
447 eeprom->type = e1000_eeprom_microwire;
448 eeprom->opcode_bits = 3;
449 eeprom->delay_usec = 50;
450 if (eecd & E1000_EECD_SIZE) {
451 eeprom->word_size = 256;
452 eeprom->address_bits = 8;
453 } else {
454 eeprom->word_size = 64;
455 eeprom->address_bits = 6;
456 }
472d5460
YS		 457 eeprom->use_eerd = false;
458 eeprom->use_eewr = false;
aa070789
RZ		 459 break;
460 case e1000_82541:
461 case e1000_82541_rev_2:
462 case e1000_82547:
463 case e1000_82547_rev_2:
464 if (eecd & E1000_EECD_TYPE) {
465 eeprom->type = e1000_eeprom_spi;
466 eeprom->opcode_bits = 8;
467 eeprom->delay_usec = 1;
468 if (eecd & E1000_EECD_ADDR_BITS) {
469 eeprom->page_size = 32;
470 eeprom->address_bits = 16;
471 } else {
472 eeprom->page_size = 8;
473 eeprom->address_bits = 8;
474 }
475 } else {
476 eeprom->type = e1000_eeprom_microwire;
477 eeprom->opcode_bits = 3;
478 eeprom->delay_usec = 50;
479 if (eecd & E1000_EECD_ADDR_BITS) {
480 eeprom->word_size = 256;
481 eeprom->address_bits = 8;
482 } else {
483 eeprom->word_size = 64;
484 eeprom->address_bits = 6;
485 }
486 }
472d5460
YS		 487 eeprom->use_eerd = false;
488 eeprom->use_eewr = false;
aa070789
RZ		 489 break;
490 case e1000_82571:
491 case e1000_82572:
492 eeprom->type = e1000_eeprom_spi;
493 eeprom->opcode_bits = 8;
494 eeprom->delay_usec = 1;
495 if (eecd & E1000_EECD_ADDR_BITS) {
496 eeprom->page_size = 32;
497 eeprom->address_bits = 16;
498 } else {
499 eeprom->page_size = 8;
500 eeprom->address_bits = 8;
501 }
472d5460
YS		 502 eeprom->use_eerd = false;
503 eeprom->use_eewr = false;
aa070789
RZ		 504 break;
505 case e1000_82573:
2c2668f9 506 case e1000_82574:
aa070789
RZ		 507 eeprom->type = e1000_eeprom_spi;
508 eeprom->opcode_bits = 8;
509 eeprom->delay_usec = 1;
510 if (eecd & E1000_EECD_ADDR_BITS) {
511 eeprom->page_size = 32;
512 eeprom->address_bits = 16;
513 } else {
514 eeprom->page_size = 8;
515 eeprom->address_bits = 8;
682011ff 516 }
472d5460 517 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
95186063
MV		 518 eeprom->use_eerd = true;
519 eeprom->use_eewr = true;
520
aa070789
RZ		 521 eeprom->type = e1000_eeprom_flash;
522 eeprom->word_size = 2048;
523
524 /* Ensure that the Autonomous FLASH update bit is cleared due to
525 * Flash update issue on parts which use a FLASH for NVM. */
526 eecd &= ~E1000_EECD_AUPDEN;
682011ff 527 E1000_WRITE_REG(hw, EECD, eecd);
682011ff 528 }
aa070789
RZ		 529 break;
530 case e1000_80003es2lan:
531 eeprom->type = e1000_eeprom_spi;
532 eeprom->opcode_bits = 8;
533 eeprom->delay_usec = 1;
534 if (eecd & E1000_EECD_ADDR_BITS) {
535 eeprom->page_size = 32;
536 eeprom->address_bits = 16;
537 } else {
538 eeprom->page_size = 8;
539 eeprom->address_bits = 8;
540 }
472d5460
YS		 541 eeprom->use_eerd = true;
542 eeprom->use_eewr = false;
aa070789 543 break;
95186063
MV		 544 case e1000_igb:
545 /* i210 has 4k of iNVM mapped as EEPROM */
546 eeprom->type = e1000_eeprom_invm;
547 eeprom->opcode_bits = 8;
548 eeprom->delay_usec = 1;
549 eeprom->page_size = 32;
550 eeprom->address_bits = 16;
551 eeprom->use_eerd = true;
552 eeprom->use_eewr = false;
553 break;
682011ff 554
aa070789
RZ		 555 /* ich8lan does not support currently. if needed, please
556 * add corresponding code and functions.
557 */
558#if 0
559 case e1000_ich8lan:
560 {
561 int32_t i = 0;
562
563 eeprom->type = e1000_eeprom_ich8;
472d5460
YS		 564 eeprom->use_eerd = false;
565 eeprom->use_eewr = false;
aa070789
RZ		 566 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
567 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
568 ICH_FLASH_GFPREG);
569 /* Zero the shadow RAM structure. But don't load it from NVM
570 * so as to save time for driver init */
571 if (hw->eeprom_shadow_ram != NULL) {
572 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
472d5460 573 hw->eeprom_shadow_ram[i].modified = false;
aa070789
RZ		 574 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
575 }
576 }
682011ff 577
aa070789
RZ		 578 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
579 ICH_FLASH_SECTOR_SIZE;
682011ff 580
aa070789
RZ		 581 hw->flash_bank_size = ((flash_size >> 16)
582 & ICH_GFPREG_BASE_MASK) + 1;
583 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
682011ff 584
aa070789 585 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
682011ff 586
aa070789
RZ		 587 hw->flash_bank_size /= 2 * sizeof(uint16_t);
588 break;
589 }
590#endif
591 default:
592 break;
682011ff
WD		 593 }
594
95186063
MV		 595 if (eeprom->type == e1000_eeprom_spi ||
596 eeprom->type == e1000_eeprom_invm) {
aa070789
RZ		 597 /* eeprom_size will be an enum [0..8] that maps
598 * to eeprom sizes 128B to
599 * 32KB (incremented by powers of 2).
600 */
601 if (hw->mac_type <= e1000_82547_rev_2) {
602 /* Set to default value for initial eeprom read. */
603 eeprom->word_size = 64;
604 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
605 &eeprom_size);
606 if (ret_val)
607 return ret_val;
608 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
609 >> EEPROM_SIZE_SHIFT;
610 /* 256B eeprom size was not supported in earlier
611 * hardware, so we bump eeprom_size up one to
612 * ensure that "1" (which maps to 256B) is never
613 * the result used in the shifting logic below. */
614 if (eeprom_size)
615 eeprom_size++;
616 } else {
617 eeprom_size = (uint16_t)((eecd &
618 E1000_EECD_SIZE_EX_MASK) >>
619 E1000_EECD_SIZE_EX_SHIFT);
620 }
621
622 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
623 }
624 return ret_val;
682011ff
WD		 625}
626
aa070789
RZ		 627/******************************************************************************
628 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
629 *
630 * hw - Struct containing variables accessed by shared code
631 *****************************************************************************/
632static int32_t
633e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
682011ff 634{
aa070789
RZ		 635 uint32_t attempts = 100000;
636 uint32_t i, reg = 0;
637 int32_t done = E1000_ERR_EEPROM;
682011ff 638
aa070789 639 for (i = 0; i < attempts; i++) {
95186063
MV		 640 if (eerd == E1000_EEPROM_POLL_READ) {
641 if (hw->mac_type == e1000_igb)
642 reg = E1000_READ_REG(hw, I210_EERD);
643 else
644 reg = E1000_READ_REG(hw, EERD);
645 } else {
646 if (hw->mac_type == e1000_igb)
647 reg = E1000_READ_REG(hw, I210_EEWR);
648 else
649 reg = E1000_READ_REG(hw, EEWR);
650 }
aa070789
RZ		 651
652 if (reg & E1000_EEPROM_RW_REG_DONE) {
653 done = E1000_SUCCESS;
654 break;
655 }
656 udelay(5);
657 }
658
659 return done;
682011ff
WD		 660}
661
aa070789
RZ		 662/******************************************************************************
663 * Reads a 16 bit word from the EEPROM using the EERD register.
664 *
665 * hw - Struct containing variables accessed by shared code
666 * offset - offset of word in the EEPROM to read
667 * data - word read from the EEPROM
668 * words - number of words to read
669 *****************************************************************************/
670static int32_t
671e1000_read_eeprom_eerd(struct e1000_hw *hw,
672 uint16_t offset,
673 uint16_t words,
674 uint16_t *data)
682011ff 675{
aa070789
RZ		 676 uint32_t i, eerd = 0;
677 int32_t error = 0;
678
679 for (i = 0; i < words; i++) {
680 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
681 E1000_EEPROM_RW_REG_START;
682
95186063
MV		 683 if (hw->mac_type == e1000_igb)
684 E1000_WRITE_REG(hw, I210_EERD, eerd);
685 else
686 E1000_WRITE_REG(hw, EERD, eerd);
687
aa070789
RZ		 688 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
689
690 if (error)
691 break;
95186063
MV		 692
693 if (hw->mac_type == e1000_igb) {
694 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
695 E1000_EEPROM_RW_REG_DATA);
696 } else {
697 data[i] = (E1000_READ_REG(hw, EERD) >>
aa070789 698 E1000_EEPROM_RW_REG_DATA);
95186063 699 }
682011ff 700
682011ff 701 }
aa070789
RZ		 702
703 return error;
682011ff
WD		 704}
705
2326a94d 706void e1000_release_eeprom(struct e1000_hw *hw)
682011ff
WD		 707{
708 uint32_t eecd;
682011ff 709
aa070789
RZ		 710 DEBUGFUNC();
711
712 eecd = E1000_READ_REG(hw, EECD);
713
714 if (hw->eeprom.type == e1000_eeprom_spi) {
715 eecd |= E1000_EECD_CS; /* Pull CS high */
716 eecd &= ~E1000_EECD_SK; /* Lower SCK */
717
682011ff 718 E1000_WRITE_REG(hw, EECD, eecd);
aa070789
RZ		 719
720 udelay(hw->eeprom.delay_usec);
721 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
722 /* cleanup eeprom */
723
724 /* CS on Microwire is active-high */
725 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
726
727 E1000_WRITE_REG(hw, EECD, eecd);
728
729 /* Rising edge of clock */
730 eecd |= E1000_EECD_SK;
731 E1000_WRITE_REG(hw, EECD, eecd);
732 E1000_WRITE_FLUSH(hw);
733 udelay(hw->eeprom.delay_usec);
734
735 /* Falling edge of clock */
736 eecd &= ~E1000_EECD_SK;
737 E1000_WRITE_REG(hw, EECD, eecd);
738 E1000_WRITE_FLUSH(hw);
739 udelay(hw->eeprom.delay_usec);
682011ff 740 }
682011ff
WD		 741
742 /* Stop requesting EEPROM access */
743 if (hw->mac_type > e1000_82544) {
682011ff
WD		 744 eecd &= ~E1000_EECD_REQ;
745 E1000_WRITE_REG(hw, EECD, eecd);
746 }
7e2d991d
TH		 747
748 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
682011ff 749}
7e2d991d 750
682011ff 751/******************************************************************************
aa070789 752 * Reads a 16 bit word from the EEPROM.
8bde7f77 753 *
682011ff 754 * hw - Struct containing variables accessed by shared code
682011ff 755 *****************************************************************************/
aa070789
RZ		 756static int32_t
757e1000_spi_eeprom_ready(struct e1000_hw *hw)
682011ff 758{
aa070789
RZ		 759 uint16_t retry_count = 0;
760 uint8_t spi_stat_reg;
682011ff
WD		 761
762 DEBUGFUNC();
763
aa070789
RZ		 764 /* Read "Status Register" repeatedly until the LSB is cleared. The
765 * EEPROM will signal that the command has been completed by clearing
766 * bit 0 of the internal status register. If it's not cleared within
767 * 5 milliseconds, then error out.
768 */
769 retry_count = 0;
770 do {
771 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
772 hw->eeprom.opcode_bits);
773 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
774 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
775 break;
8bde7f77 776
aa070789
RZ		 777 udelay(5);
778 retry_count += 5;
779
780 e1000_standby_eeprom(hw);
781 } while (retry_count < EEPROM_MAX_RETRY_SPI);
782
783 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
784 * only 0-5mSec on 5V devices)
785 */
786 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
787 DEBUGOUT("SPI EEPROM Status error\n");
682011ff
WD		 788 return -E1000_ERR_EEPROM;
789 }
aa070789
RZ		 790
791 return E1000_SUCCESS;
682011ff
WD		 792}
793
794/******************************************************************************
aa070789 795 * Reads a 16 bit word from the EEPROM.
682011ff 796 *
aa070789
RZ		 797 * hw - Struct containing variables accessed by shared code
798 * offset - offset of word in the EEPROM to read
799 * data - word read from the EEPROM
682011ff 800 *****************************************************************************/
aa070789
RZ		 801static int32_t
802e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
803 uint16_t words, uint16_t *data)
682011ff 804{
aa070789
RZ		 805 struct e1000_eeprom_info *eeprom = &hw->eeprom;
806 uint32_t i = 0;
682011ff
WD		 807
808 DEBUGFUNC();
809
aa070789
RZ		 810 /* If eeprom is not yet detected, do so now */
811 if (eeprom->word_size == 0)
812 e1000_init_eeprom_params(hw);
813
814 /* A check for invalid values: offset too large, too many words,
815 * and not enough words.
816 */
817 if ((offset >= eeprom->word_size) ||
818 (words > eeprom->word_size - offset) ||
819 (words == 0)) {
820 DEBUGOUT("\"words\" parameter out of bounds."
821 "Words = %d, size = %d\n", offset, eeprom->word_size);
822 return -E1000_ERR_EEPROM;
823 }
824
825 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
826 * directly. In this case, we need to acquire the EEPROM so that
827 * FW or other port software does not interrupt.
828 */
472d5460
YS		 829 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
830 hw->eeprom.use_eerd == false) {
aa070789
RZ		 831
832 /* Prepare the EEPROM for bit-bang reading */
833 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
834 return -E1000_ERR_EEPROM;
835 }
836
837 /* Eerd register EEPROM access requires no eeprom aquire/release */
472d5460 838 if (eeprom->use_eerd == true)
aa070789
RZ		 839 return e1000_read_eeprom_eerd(hw, offset, words, data);
840
841 /* ich8lan does not support currently. if needed, please
842 * add corresponding code and functions.
843 */
844#if 0
845 /* ICH EEPROM access is done via the ICH flash controller */
846 if (eeprom->type == e1000_eeprom_ich8)
847 return e1000_read_eeprom_ich8(hw, offset, words, data);
848#endif
849 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
850 * acquired the EEPROM at this point, so any returns should relase it */
851 if (eeprom->type == e1000_eeprom_spi) {
852 uint16_t word_in;
853 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
854
855 if (e1000_spi_eeprom_ready(hw)) {
856 e1000_release_eeprom(hw);
857 return -E1000_ERR_EEPROM;
858 }
859
860 e1000_standby_eeprom(hw);
861
862 /* Some SPI eeproms use the 8th address bit embedded in
863 * the opcode */
864 if ((eeprom->address_bits == 8) && (offset >= 128))
865 read_opcode |= EEPROM_A8_OPCODE_SPI;
866
867 /* Send the READ command (opcode + addr) */
868 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
869 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
870 eeprom->address_bits);
871
872 /* Read the data. The address of the eeprom internally
873 * increments with each byte (spi) being read, saving on the
874 * overhead of eeprom setup and tear-down. The address
875 * counter will roll over if reading beyond the size of
876 * the eeprom, thus allowing the entire memory to be read
877 * starting from any offset. */
878 for (i = 0; i < words; i++) {
879 word_in = e1000_shift_in_ee_bits(hw, 16);
880 data[i] = (word_in >> 8) | (word_in << 8);
881 }
882 } else if (eeprom->type == e1000_eeprom_microwire) {
883 for (i = 0; i < words; i++) {
884 /* Send the READ command (opcode + addr) */
885 e1000_shift_out_ee_bits(hw,
886 EEPROM_READ_OPCODE_MICROWIRE,
887 eeprom->opcode_bits);
888 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
889 eeprom->address_bits);
890
891 /* Read the data. For microwire, each word requires
892 * the overhead of eeprom setup and tear-down. */
893 data[i] = e1000_shift_in_ee_bits(hw, 16);
894 e1000_standby_eeprom(hw);
895 }
896 }
897
898 /* End this read operation */
899 e1000_release_eeprom(hw);
900
901 return E1000_SUCCESS;
902}
903
904/******************************************************************************
905 * Verifies that the EEPROM has a valid checksum
906 *
907 * hw - Struct containing variables accessed by shared code
908 *
909 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
910 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
911 * valid.
912 *****************************************************************************/
114d7fc0 913static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
aa070789 914{
114d7fc0 915 uint16_t i, checksum, checksum_reg, *buf;
aa070789
RZ		 916
917 DEBUGFUNC();
918
114d7fc0
KM		 919 /* Allocate a temporary buffer */
920 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
921 if (!buf) {
5c5e707a 922 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
114d7fc0 923 return -E1000_ERR_EEPROM;
aa070789
RZ		 924 }
925
114d7fc0
KM		 926 /* Read the EEPROM */
927 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
5c5e707a 928 E1000_ERR(hw, "Unable to read EEPROM!\n");
aa070789
RZ		 929 return -E1000_ERR_EEPROM;
930 }
114d7fc0
KM		 931
932 /* Compute the checksum */
7a341066 933 checksum = 0;
114d7fc0
KM		 934 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
935 checksum += buf[i];
936 checksum = ((uint16_t)EEPROM_SUM) - checksum;
937 checksum_reg = buf[i];
938
939 /* Verify it! */
940 if (checksum == checksum_reg)
941 return 0;
942
943 /* Hrm, verification failed, print an error */
5c5e707a
SG		 944 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
945 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
946 checksum_reg, checksum);
114d7fc0
KM		 947
948 return -E1000_ERR_EEPROM;
aa070789 949}
8712adfd 950#endif /* CONFIG_E1000_NO_NVM */
ecbd2078
RZ		 951
952/*****************************************************************************
953 * Set PHY to class A mode
954 * Assumes the following operations will follow to enable the new class mode.
955 * 1. Do a PHY soft reset
956 * 2. Restart auto-negotiation or force link.
957 *
958 * hw - Struct containing variables accessed by shared code
959 ****************************************************************************/
960static int32_t
961e1000_set_phy_mode(struct e1000_hw *hw)
962{
8712adfd 963#ifndef CONFIG_E1000_NO_NVM
ecbd2078
RZ		 964 int32_t ret_val;
965 uint16_t eeprom_data;
966
967 DEBUGFUNC();
968
969 if ((hw->mac_type == e1000_82545_rev_3) &&
970 (hw->media_type == e1000_media_type_copper)) {
971 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
972 1, &eeprom_data);
973 if (ret_val)
974 return ret_val;
975
976 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
977 (eeprom_data & EEPROM_PHY_CLASS_A)) {
978 ret_val = e1000_write_phy_reg(hw,
979 M88E1000_PHY_PAGE_SELECT, 0x000B);
980 if (ret_val)
981 return ret_val;
982 ret_val = e1000_write_phy_reg(hw,
983 M88E1000_PHY_GEN_CONTROL, 0x8104);
984 if (ret_val)
985 return ret_val;
986
472d5460 987 hw->phy_reset_disable = false;
ecbd2078
RZ		 988 }
989 }
8712adfd 990#endif
ecbd2078
RZ		 991 return E1000_SUCCESS;
992}
aa070789 993
8712adfd 994#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 995/***************************************************************************
996 *
997 * Obtaining software semaphore bit (SMBI) before resetting PHY.
998 *
999 * hw: Struct containing variables accessed by shared code
1000 *
1001 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1002 * E1000_SUCCESS at any other case.
1003 *
1004 ***************************************************************************/
1005static int32_t
1006e1000_get_software_semaphore(struct e1000_hw *hw)
1007{
1008 int32_t timeout = hw->eeprom.word_size + 1;
1009 uint32_t swsm;
1010
1011 DEBUGFUNC();
1012
1013 if (hw->mac_type != e1000_80003es2lan)
1014 return E1000_SUCCESS;
1015
1016 while (timeout) {
1017 swsm = E1000_READ_REG(hw, SWSM);
1018 /* If SMBI bit cleared, it is now set and we hold
1019 * the semaphore */
1020 if (!(swsm & E1000_SWSM_SMBI))
1021 break;
1022 mdelay(1);
1023 timeout--;
1024 }
1025
1026 if (!timeout) {
1027 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1028 return -E1000_ERR_RESET;
1029 }
1030
1031 return E1000_SUCCESS;
1032}
8712adfd 1033#endif
aa070789
RZ		 1034
1035/***************************************************************************
1036 * This function clears HW semaphore bits.
1037 *
1038 * hw: Struct containing variables accessed by shared code
1039 *
1040 * returns: - None.
1041 *
1042 ***************************************************************************/
1043static void
1044e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1045{
8712adfd 1046#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1047 uint32_t swsm;
1048
1049 DEBUGFUNC();
1050
1051 if (!hw->eeprom_semaphore_present)
1052 return;
1053
1054 swsm = E1000_READ_REG(hw, SWSM);
1055 if (hw->mac_type == e1000_80003es2lan) {
1056 /* Release both semaphores. */
1057 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1058 } else
1059 swsm &= ~(E1000_SWSM_SWESMBI);
1060 E1000_WRITE_REG(hw, SWSM, swsm);
8712adfd 1061#endif
aa070789
RZ		 1062}
1063
1064/***************************************************************************
1065 *
1066 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1067 * adapter or Eeprom access.
1068 *
1069 * hw: Struct containing variables accessed by shared code
1070 *
1071 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1072 * E1000_SUCCESS at any other case.
1073 *
1074 ***************************************************************************/
1075static int32_t
1076e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1077{
8712adfd 1078#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1079 int32_t timeout;
1080 uint32_t swsm;
1081
1082 DEBUGFUNC();
1083
1084 if (!hw->eeprom_semaphore_present)
1085 return E1000_SUCCESS;
1086
1087 if (hw->mac_type == e1000_80003es2lan) {
1088 /* Get the SW semaphore. */
1089 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1090 return -E1000_ERR_EEPROM;
1091 }
1092
1093 /* Get the FW semaphore. */
1094 timeout = hw->eeprom.word_size + 1;
1095 while (timeout) {
1096 swsm = E1000_READ_REG(hw, SWSM);
1097 swsm |= E1000_SWSM_SWESMBI;
1098 E1000_WRITE_REG(hw, SWSM, swsm);
1099 /* if we managed to set the bit we got the semaphore. */
1100 swsm = E1000_READ_REG(hw, SWSM);
1101 if (swsm & E1000_SWSM_SWESMBI)
1102 break;
1103
1104 udelay(50);
1105 timeout--;
1106 }
1107
1108 if (!timeout) {
1109 /* Release semaphores */
1110 e1000_put_hw_eeprom_semaphore(hw);
1111 DEBUGOUT("Driver can't access the Eeprom - "
1112 "SWESMBI bit is set.\n");
1113 return -E1000_ERR_EEPROM;
1114 }
8712adfd 1115#endif
aa070789
RZ		 1116 return E1000_SUCCESS;
1117}
1118
7e2d991d 1119/* Take ownership of the PHY */
aa070789
RZ		 1120static int32_t
1121e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1122{
1123 uint32_t swfw_sync = 0;
1124 uint32_t swmask = mask;
1125 uint32_t fwmask = mask << 16;
1126 int32_t timeout = 200;
1127
1128 DEBUGFUNC();
1129 while (timeout) {
1130 if (e1000_get_hw_eeprom_semaphore(hw))
1131 return -E1000_ERR_SWFW_SYNC;
1132
3c63dd53 1133 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
76f8cdb2 1134 if (!(swfw_sync & (fwmask | swmask)))
aa070789
RZ		 1135 break;
1136
1137 /* firmware currently using resource (fwmask) */
1138 /* or other software thread currently using resource (swmask) */
1139 e1000_put_hw_eeprom_semaphore(hw);
1140 mdelay(5);
1141 timeout--;
1142 }
1143
1144 if (!timeout) {
1145 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1146 return -E1000_ERR_SWFW_SYNC;
1147 }
1148
1149 swfw_sync |= swmask;
1150 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1151
1152 e1000_put_hw_eeprom_semaphore(hw);
1153 return E1000_SUCCESS;
1154}
1155
7e2d991d
TH		 1156static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1157{
1158 uint32_t swfw_sync = 0;
1159
1160 DEBUGFUNC();
1161 while (e1000_get_hw_eeprom_semaphore(hw))
1162 ; /* Empty */
1163
1164 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1165 swfw_sync &= ~mask;
1166 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1167
1168 e1000_put_hw_eeprom_semaphore(hw);
1169}
1170
472d5460 1171static bool e1000_is_second_port(struct e1000_hw *hw)
987b43a1
KM		 1172{
1173 switch (hw->mac_type) {
1174 case e1000_80003es2lan:
1175 case e1000_82546:
1176 case e1000_82571:
1177 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
472d5460 1178 return true;
987b43a1
KM		 1179 /* Fallthrough */
1180 default:
472d5460 1181 return false;
987b43a1
KM		 1182 }
1183}
1184
8712adfd 1185#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1186/******************************************************************************
1187 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1188 * second function of dual function devices
1189 *
1190 * nic - Struct containing variables accessed by shared code
1191 *****************************************************************************/
1192static int
5c5e707a 1193e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
aa070789 1194{
aa070789
RZ		 1195 uint16_t offset;
1196 uint16_t eeprom_data;
95186063 1197 uint32_t reg_data = 0;
aa070789
RZ		 1198 int i;
1199
1200 DEBUGFUNC();
1201
1202 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1203 offset = i >> 1;
95186063
MV		 1204 if (hw->mac_type == e1000_igb) {
1205 /* i210 preloads MAC address into RAL/RAH registers */
1206 if (offset == 0)
1207 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1208 else if (offset == 1)
1209 reg_data >>= 16;
1210 else if (offset == 2)
1211 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1212 eeprom_data = reg_data & 0xffff;
1213 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
682011ff
WD		 1214 DEBUGOUT("EEPROM Read Error\n");
1215 return -E1000_ERR_EEPROM;
1216 }
5c5e707a
SG		 1217 enetaddr[i] = eeprom_data & 0xff;
1218 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
682011ff 1219 }
987b43a1
KM		 1220
1221 /* Invert the last bit if this is the second device */
1222 if (e1000_is_second_port(hw))
5c5e707a 1223 enetaddr[5] ^= 1;
987b43a1 1224
682011ff
WD		 1225 return 0;
1226}
8712adfd 1227#endif
682011ff
WD		 1228
1229/******************************************************************************
1230 * Initializes receive address filters.
1231 *
8bde7f77 1232 * hw - Struct containing variables accessed by shared code
682011ff
WD		 1233 *
1234 * Places the MAC address in receive address register 0 and clears the rest
1235 * of the receive addresss registers. Clears the multicast table. Assumes
1236 * the receiver is in reset when the routine is called.
1237 *****************************************************************************/
1238static void
5c5e707a 1239e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
682011ff 1240{
682011ff
WD		 1241 uint32_t i;
1242 uint32_t addr_low;
1243 uint32_t addr_high;
1244
1245 DEBUGFUNC();
1246
1247 /* Setup the receive address. */
1248 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5c5e707a
SG		 1249 addr_low = (enetaddr[0] |
1250 (enetaddr[1] << 8) |
1251 (enetaddr[2] << 16) | (enetaddr[3] << 24));
682011ff 1252
5c5e707a 1253 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
682011ff
WD		 1254
1255 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1256 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1257
1258 /* Zero out the other 15 receive addresses. */
1259 DEBUGOUT("Clearing RAR[1-15]\n");
1260 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1261 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1262 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1263 }
1264}
1265
1266/******************************************************************************
1267 * Clears the VLAN filer table
1268 *
1269 * hw - Struct containing variables accessed by shared code
1270 *****************************************************************************/
1271static void
1272e1000_clear_vfta(struct e1000_hw *hw)
1273{
1274 uint32_t offset;
1275
1276 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1277 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1278}
1279
1280/******************************************************************************
1281 * Set the mac type member in the hw struct.
8bde7f77 1282 *
682011ff
WD		 1283 * hw - Struct containing variables accessed by shared code
1284 *****************************************************************************/
aa070789 1285int32_t
682011ff
WD		 1286e1000_set_mac_type(struct e1000_hw *hw)
1287{
1288 DEBUGFUNC();
1289
1290 switch (hw->device_id) {
1291 case E1000_DEV_ID_82542:
1292 switch (hw->revision_id) {
1293 case E1000_82542_2_0_REV_ID:
1294 hw->mac_type = e1000_82542_rev2_0;
1295 break;
1296 case E1000_82542_2_1_REV_ID:
1297 hw->mac_type = e1000_82542_rev2_1;
1298 break;
1299 default:
1300 /* Invalid 82542 revision ID */
1301 return -E1000_ERR_MAC_TYPE;
1302 }
1303 break;
1304 case E1000_DEV_ID_82543GC_FIBER:
1305 case E1000_DEV_ID_82543GC_COPPER:
1306 hw->mac_type = e1000_82543;
1307 break;
1308 case E1000_DEV_ID_82544EI_COPPER:
1309 case E1000_DEV_ID_82544EI_FIBER:
1310 case E1000_DEV_ID_82544GC_COPPER:
1311 case E1000_DEV_ID_82544GC_LOM:
1312 hw->mac_type = e1000_82544;
1313 break;
1314 case E1000_DEV_ID_82540EM:
1315 case E1000_DEV_ID_82540EM_LOM:
aa070789
RZ		 1316 case E1000_DEV_ID_82540EP:
1317 case E1000_DEV_ID_82540EP_LOM:
1318 case E1000_DEV_ID_82540EP_LP:
682011ff
WD		 1319 hw->mac_type = e1000_82540;
1320 break;
1321 case E1000_DEV_ID_82545EM_COPPER:
1322 case E1000_DEV_ID_82545EM_FIBER:
1323 hw->mac_type = e1000_82545;
1324 break;
aa070789
RZ		 1325 case E1000_DEV_ID_82545GM_COPPER:
1326 case E1000_DEV_ID_82545GM_FIBER:
1327 case E1000_DEV_ID_82545GM_SERDES:
1328 hw->mac_type = e1000_82545_rev_3;
1329 break;
682011ff
WD		 1330 case E1000_DEV_ID_82546EB_COPPER:
1331 case E1000_DEV_ID_82546EB_FIBER:
aa070789 1332 case E1000_DEV_ID_82546EB_QUAD_COPPER:
682011ff
WD		 1333 hw->mac_type = e1000_82546;
1334 break;
aa070789
RZ		 1335 case E1000_DEV_ID_82546GB_COPPER:
1336 case E1000_DEV_ID_82546GB_FIBER:
1337 case E1000_DEV_ID_82546GB_SERDES:
1338 case E1000_DEV_ID_82546GB_PCIE:
1339 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1340 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1341 hw->mac_type = e1000_82546_rev_3;
1342 break;
1343 case E1000_DEV_ID_82541EI:
1344 case E1000_DEV_ID_82541EI_MOBILE:
1345 case E1000_DEV_ID_82541ER_LOM:
1346 hw->mac_type = e1000_82541;
1347 break;
ac3315c2 1348 case E1000_DEV_ID_82541ER:
aa070789 1349 case E1000_DEV_ID_82541GI:
aa3b8bf9 1350 case E1000_DEV_ID_82541GI_LF:
aa070789 1351 case E1000_DEV_ID_82541GI_MOBILE:
1aeed8d7
WD		 1352 hw->mac_type = e1000_82541_rev_2;
1353 break;
aa070789
RZ		 1354 case E1000_DEV_ID_82547EI:
1355 case E1000_DEV_ID_82547EI_MOBILE:
1356 hw->mac_type = e1000_82547;
1357 break;
1358 case E1000_DEV_ID_82547GI:
1359 hw->mac_type = e1000_82547_rev_2;
1360 break;
1361 case E1000_DEV_ID_82571EB_COPPER:
1362 case E1000_DEV_ID_82571EB_FIBER:
1363 case E1000_DEV_ID_82571EB_SERDES:
1364 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1365 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1366 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1367 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1368 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1369 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1370 hw->mac_type = e1000_82571;
1371 break;
1372 case E1000_DEV_ID_82572EI_COPPER:
1373 case E1000_DEV_ID_82572EI_FIBER:
1374 case E1000_DEV_ID_82572EI_SERDES:
1375 case E1000_DEV_ID_82572EI:
1376 hw->mac_type = e1000_82572;
1377 break;
1378 case E1000_DEV_ID_82573E:
1379 case E1000_DEV_ID_82573E_IAMT:
1380 case E1000_DEV_ID_82573L:
1381 hw->mac_type = e1000_82573;
1382 break;
2c2668f9
RZ		 1383 case E1000_DEV_ID_82574L:
1384 hw->mac_type = e1000_82574;
1385 break;
aa070789
RZ		 1386 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1387 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1388 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1389 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1390 hw->mac_type = e1000_80003es2lan;
1391 break;
1392 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1393 case E1000_DEV_ID_ICH8_IGP_AMT:
1394 case E1000_DEV_ID_ICH8_IGP_C:
1395 case E1000_DEV_ID_ICH8_IFE:
1396 case E1000_DEV_ID_ICH8_IFE_GT:
1397 case E1000_DEV_ID_ICH8_IFE_G:
1398 case E1000_DEV_ID_ICH8_IGP_M:
1399 hw->mac_type = e1000_ich8lan;
1400 break;
6c499abe
MZ		 1401 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1402 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
95186063 1403 case PCI_DEVICE_ID_INTEL_I210_COPPER:
6c499abe 1404 case PCI_DEVICE_ID_INTEL_I211_COPPER:
95186063
MV		 1405 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1406 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1407 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1408 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1409 hw->mac_type = e1000_igb;
1410 break;
682011ff
WD		 1411 default:
1412 /* Should never have loaded on this device */
1413 return -E1000_ERR_MAC_TYPE;
1414 }
1415 return E1000_SUCCESS;
1416}
1417
1418/******************************************************************************
1419 * Reset the transmit and receive units; mask and clear all interrupts.
1420 *
1421 * hw - Struct containing variables accessed by shared code
1422 *****************************************************************************/
1423void
1424e1000_reset_hw(struct e1000_hw *hw)
1425{
1426 uint32_t ctrl;
1427 uint32_t ctrl_ext;
682011ff 1428 uint32_t manc;
9ea005fb 1429 uint32_t pba = 0;
95186063 1430 uint32_t reg;
682011ff
WD		 1431
1432 DEBUGFUNC();
1433
9ea005fb
RZ		 1434 /* get the correct pba value for both PCI and PCIe*/
1435 if (hw->mac_type < e1000_82571)
1436 pba = E1000_DEFAULT_PCI_PBA;
1437 else
1438 pba = E1000_DEFAULT_PCIE_PBA;
1439
682011ff
WD		 1440 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1441 if (hw->mac_type == e1000_82542_rev2_0) {
1442 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1443 pci_write_config_word(hw->pdev, PCI_COMMAND,
aa070789 1444 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
682011ff
WD		 1445 }
1446
1447 /* Clear interrupt mask to stop board from generating interrupts */
1448 DEBUGOUT("Masking off all interrupts\n");
95186063
MV		 1449 if (hw->mac_type == e1000_igb)
1450 E1000_WRITE_REG(hw, I210_IAM, 0);
682011ff
WD		 1451 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1452
1453 /* Disable the Transmit and Receive units. Then delay to allow
1454 * any pending transactions to complete before we hit the MAC with
1455 * the global reset.
1456 */
1457 E1000_WRITE_REG(hw, RCTL, 0);
1458 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1459 E1000_WRITE_FLUSH(hw);
1460
1461 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
472d5460 1462 hw->tbi_compatibility_on = false;
682011ff
WD		 1463
1464 /* Delay to allow any outstanding PCI transactions to complete before
1465 * resetting the device
1466 */
1467 mdelay(10);
1468
1469 /* Issue a global reset to the MAC. This will reset the chip's
1470 * transmit, receive, DMA, and link units. It will not effect
1471 * the current PCI configuration. The global reset bit is self-
1472 * clearing, and should clear within a microsecond.
1473 */
1474 DEBUGOUT("Issuing a global reset to MAC\n");
1475 ctrl = E1000_READ_REG(hw, CTRL);
1476
aa070789 1477 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
682011ff
WD		 1478
1479 /* Force a reload from the EEPROM if necessary */
95186063
MV		 1480 if (hw->mac_type == e1000_igb) {
1481 mdelay(20);
1482 reg = E1000_READ_REG(hw, STATUS);
1483 if (reg & E1000_STATUS_PF_RST_DONE)
1484 DEBUGOUT("PF OK\n");
1485 reg = E1000_READ_REG(hw, I210_EECD);
1486 if (reg & E1000_EECD_AUTO_RD)
1487 DEBUGOUT("EEC OK\n");
1488 } else if (hw->mac_type < e1000_82540) {
682011ff
WD		 1489 /* Wait for reset to complete */
1490 udelay(10);
1491 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1492 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1493 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1494 E1000_WRITE_FLUSH(hw);
1495 /* Wait for EEPROM reload */
1496 mdelay(2);
1497 } else {
1498 /* Wait for EEPROM reload (it happens automatically) */
1499 mdelay(4);
1500 /* Dissable HW ARPs on ASF enabled adapters */
1501 manc = E1000_READ_REG(hw, MANC);
1502 manc &= ~(E1000_MANC_ARP_EN);
1503 E1000_WRITE_REG(hw, MANC, manc);
1504 }
1505
1506 /* Clear interrupt mask to stop board from generating interrupts */
1507 DEBUGOUT("Masking off all interrupts\n");
95186063
MV		 1508 if (hw->mac_type == e1000_igb)
1509 E1000_WRITE_REG(hw, I210_IAM, 0);
682011ff
WD		 1510 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1511
1512 /* Clear any pending interrupt events. */
56b13b1e 1513 E1000_READ_REG(hw, ICR);
682011ff
WD		 1514
1515 /* If MWI was previously enabled, reenable it. */
1516 if (hw->mac_type == e1000_82542_rev2_0) {
1517 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1518 }
95186063
MV		 1519 if (hw->mac_type != e1000_igb)
1520 E1000_WRITE_REG(hw, PBA, pba);
aa070789
RZ		 1521}
1522
1523/******************************************************************************
1524 *
1525 * Initialize a number of hardware-dependent bits
1526 *
1527 * hw: Struct containing variables accessed by shared code
1528 *
1529 * This function contains hardware limitation workarounds for PCI-E adapters
1530 *
1531 *****************************************************************************/
1532static void
1533e1000_initialize_hardware_bits(struct e1000_hw *hw)
1534{
1535 if ((hw->mac_type >= e1000_82571) &&
1536 (!hw->initialize_hw_bits_disable)) {
1537 /* Settings common to all PCI-express silicon */
1538 uint32_t reg_ctrl, reg_ctrl_ext;
1539 uint32_t reg_tarc0, reg_tarc1;
1540 uint32_t reg_tctl;
1541 uint32_t reg_txdctl, reg_txdctl1;
1542
1543 /* link autonegotiation/sync workarounds */
1544 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1545 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1546
1547 /* Enable not-done TX descriptor counting */
1548 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1549 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1550 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1551
1552 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1553 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1554 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1555
95186063
MV		 1556 /* IGB is cool */
1557 if (hw->mac_type == e1000_igb)
1558 return;
1559
aa070789
RZ		 1560 switch (hw->mac_type) {
1561 case e1000_82571:
1562 case e1000_82572:
1563 /* Clear PHY TX compatible mode bits */
1564 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1565 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1566
1567 /* link autonegotiation/sync workarounds */
1568 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1569
1570 /* TX ring control fixes */
1571 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1572
1573 /* Multiple read bit is reversed polarity */
1574 reg_tctl = E1000_READ_REG(hw, TCTL);
1575 if (reg_tctl & E1000_TCTL_MULR)
1576 reg_tarc1 &= ~(1 << 28);
1577 else
1578 reg_tarc1 |= (1 << 28);
1579
1580 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1581 break;
1582 case e1000_82573:
2c2668f9 1583 case e1000_82574:
aa070789
RZ		 1584 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1585 reg_ctrl_ext &= ~(1 << 23);
1586 reg_ctrl_ext |= (1 << 22);
1587
1588 /* TX byte count fix */
1589 reg_ctrl = E1000_READ_REG(hw, CTRL);
1590 reg_ctrl &= ~(1 << 29);
1591
1592 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1593 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1594 break;
1595 case e1000_80003es2lan:
1596 /* improve small packet performace for fiber/serdes */
1597 if ((hw->media_type == e1000_media_type_fiber)
1598 || (hw->media_type ==
1599 e1000_media_type_internal_serdes)) {
1600 reg_tarc0 &= ~(1 << 20);
1601 }
1602
1603 /* Multiple read bit is reversed polarity */
1604 reg_tctl = E1000_READ_REG(hw, TCTL);
1605 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1606 if (reg_tctl & E1000_TCTL_MULR)
1607 reg_tarc1 &= ~(1 << 28);
1608 else
1609 reg_tarc1 |= (1 << 28);
1610
1611 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1612 break;
1613 case e1000_ich8lan:
1614 /* Reduce concurrent DMA requests to 3 from 4 */
1615 if ((hw->revision_id < 3) ||
1616 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1617 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1618 reg_tarc0 |= ((1 << 29)|(1 << 28));
1619
1620 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1621 reg_ctrl_ext |= (1 << 22);
1622 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1623
1624 /* workaround TX hang with TSO=on */
1625 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1626
1627 /* Multiple read bit is reversed polarity */
1628 reg_tctl = E1000_READ_REG(hw, TCTL);
1629 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1630 if (reg_tctl & E1000_TCTL_MULR)
1631 reg_tarc1 &= ~(1 << 28);
1632 else
1633 reg_tarc1 |= (1 << 28);
1634
1635 /* workaround TX hang with TSO=on */
1636 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1637
1638 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1639 break;
1640 default:
1641 break;
1642 }
1643
1644 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1645 }
682011ff
WD		 1646}
1647
1648/******************************************************************************
1649 * Performs basic configuration of the adapter.
1650 *
1651 * hw - Struct containing variables accessed by shared code
8bde7f77
WD		 1652 *
1653 * Assumes that the controller has previously been reset and is in a
682011ff
WD		 1654 * post-reset uninitialized state. Initializes the receive address registers,
1655 * multicast table, and VLAN filter table. Calls routines to setup link
1656 * configuration and flow control settings. Clears all on-chip counters. Leaves
1657 * the transmit and receive units disabled and uninitialized.
1658 *****************************************************************************/
1659static int
5c5e707a 1660e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
682011ff 1661{
aa070789 1662 uint32_t ctrl;
682011ff
WD		 1663 uint32_t i;
1664 int32_t ret_val;
1665 uint16_t pcix_cmd_word;
1666 uint16_t pcix_stat_hi_word;
1667 uint16_t cmd_mmrbc;
1668 uint16_t stat_mmrbc;
aa070789
RZ		 1669 uint32_t mta_size;
1670 uint32_t reg_data;
1671 uint32_t ctrl_ext;
682011ff 1672 DEBUGFUNC();
aa070789
RZ		 1673 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1674 if ((hw->mac_type == e1000_ich8lan) &&
1675 ((hw->revision_id < 3) ||
1676 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1677 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1678 reg_data = E1000_READ_REG(hw, STATUS);
1679 reg_data &= ~0x80000000;
1680 E1000_WRITE_REG(hw, STATUS, reg_data);
682011ff 1681 }
aa070789 1682 /* Do not need initialize Identification LED */
682011ff 1683
aa070789
RZ		 1684 /* Set the media type and TBI compatibility */
1685 e1000_set_media_type(hw);
1686
1687 /* Must be called after e1000_set_media_type
1688 * because media_type is used */
1689 e1000_initialize_hardware_bits(hw);
682011ff
WD		 1690
1691 /* Disabling VLAN filtering. */
1692 DEBUGOUT("Initializing the IEEE VLAN\n");
aa070789
RZ		 1693 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1694 if (hw->mac_type != e1000_ich8lan) {
1695 if (hw->mac_type < e1000_82545_rev_3)
1696 E1000_WRITE_REG(hw, VET, 0);
1697 e1000_clear_vfta(hw);
1698 }
682011ff
WD		 1699
1700 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1701 if (hw->mac_type == e1000_82542_rev2_0) {
1702 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1703 pci_write_config_word(hw->pdev, PCI_COMMAND,
1704 hw->
1705 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1706 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1707 E1000_WRITE_FLUSH(hw);
1708 mdelay(5);
1709 }
1710
1711 /* Setup the receive address. This involves initializing all of the Receive
1712 * Address Registers (RARs 0 - 15).
1713 */
5c5e707a 1714 e1000_init_rx_addrs(hw, enetaddr);
682011ff
WD		 1715
1716 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1717 if (hw->mac_type == e1000_82542_rev2_0) {
1718 E1000_WRITE_REG(hw, RCTL, 0);
1719 E1000_WRITE_FLUSH(hw);
1720 mdelay(1);
1721 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1722 }
1723
1724 /* Zero out the Multicast HASH table */
1725 DEBUGOUT("Zeroing the MTA\n");
aa070789
RZ		 1726 mta_size = E1000_MC_TBL_SIZE;
1727 if (hw->mac_type == e1000_ich8lan)
1728 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1729 for (i = 0; i < mta_size; i++) {
682011ff 1730 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
aa070789
RZ		 1731 /* use write flush to prevent Memory Write Block (MWB) from
1732 * occuring when accessing our register space */
1733 E1000_WRITE_FLUSH(hw);
1734 }
682011ff
WD		 1735#if 0
1736 /* Set the PCI priority bit correctly in the CTRL register. This
1737 * determines if the adapter gives priority to receives, or if it
aa070789
RZ		 1738 * gives equal priority to transmits and receives. Valid only on
1739 * 82542 and 82543 silicon.
682011ff 1740 */
aa070789 1741 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
682011ff
WD		 1742 ctrl = E1000_READ_REG(hw, CTRL);
1743 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1744 }
1745#endif
aa070789
RZ		 1746 switch (hw->mac_type) {
1747 case e1000_82545_rev_3:
1748 case e1000_82546_rev_3:
95186063 1749 case e1000_igb:
aa070789
RZ		 1750 break;
1751 default:
682011ff 1752 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
aa070789 1753 if (hw->bus_type == e1000_bus_type_pcix) {
682011ff
WD		 1754 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1755 &pcix_cmd_word);
1756 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1757 &pcix_stat_hi_word);
1758 cmd_mmrbc =
1759 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1760 PCIX_COMMAND_MMRBC_SHIFT;
1761 stat_mmrbc =
1762 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1763 PCIX_STATUS_HI_MMRBC_SHIFT;
1764 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1765 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1766 if (cmd_mmrbc > stat_mmrbc) {
1767 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1768 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1769 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1770 pcix_cmd_word);
1771 }
1772 }
aa070789
RZ		 1773 break;
1774 }
1775
1776 /* More time needed for PHY to initialize */
1777 if (hw->mac_type == e1000_ich8lan)
1778 mdelay(15);
95186063
MV		 1779 if (hw->mac_type == e1000_igb)
1780 mdelay(15);
682011ff
WD		 1781
1782 /* Call a subroutine to configure the link and setup flow control. */
5c5e707a 1783 ret_val = e1000_setup_link(hw);
682011ff
WD		 1784
1785 /* Set the transmit descriptor write-back policy */
1786 if (hw->mac_type > e1000_82544) {
1787 ctrl = E1000_READ_REG(hw, TXDCTL);
1788 ctrl =
1789 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1790 E1000_TXDCTL_FULL_TX_DESC_WB;
1791 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1792 }
aa070789 1793
776e66e8 1794 /* Set the receive descriptor write back policy */
776e66e8
RG		 1795 if (hw->mac_type >= e1000_82571) {
1796 ctrl = E1000_READ_REG(hw, RXDCTL);
1797 ctrl =
1798 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1799 E1000_RXDCTL_FULL_RX_DESC_WB;
1800 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1801 }
1802
aa070789
RZ		 1803 switch (hw->mac_type) {
1804 default:
1805 break;
1806 case e1000_80003es2lan:
1807 /* Enable retransmit on late collisions */
1808 reg_data = E1000_READ_REG(hw, TCTL);
1809 reg_data |= E1000_TCTL_RTLC;
1810 E1000_WRITE_REG(hw, TCTL, reg_data);
1811
1812 /* Configure Gigabit Carry Extend Padding */
1813 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1814 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1815 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1816 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1817
1818 /* Configure Transmit Inter-Packet Gap */
1819 reg_data = E1000_READ_REG(hw, TIPG);
1820 reg_data &= ~E1000_TIPG_IPGT_MASK;
1821 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1822 E1000_WRITE_REG(hw, TIPG, reg_data);
1823
1824 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1825 reg_data &= ~0x00100000;
1826 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1827 /* Fall through */
1828 case e1000_82571:
1829 case e1000_82572:
1830 case e1000_ich8lan:
1831 ctrl = E1000_READ_REG(hw, TXDCTL1);
1832 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1833 | E1000_TXDCTL_FULL_TX_DESC_WB;
1834 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1835 break;
2c2668f9
RZ		 1836 case e1000_82573:
1837 case e1000_82574:
1838 reg_data = E1000_READ_REG(hw, GCR);
1839 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1840 E1000_WRITE_REG(hw, GCR, reg_data);
95186063
MV		 1841 case e1000_igb:
1842 break;
aa070789
RZ		 1843 }
1844
682011ff
WD		 1845#if 0
1846 /* Clear all of the statistics registers (clear on read). It is
1847 * important that we do this after we have tried to establish link
1848 * because the symbol error count will increment wildly if there
1849 * is no link.
1850 */
1851 e1000_clear_hw_cntrs(hw);
aa070789
RZ		 1852
1853 /* ICH8 No-snoop bits are opposite polarity.
1854 * Set to snoop by default after reset. */
1855 if (hw->mac_type == e1000_ich8lan)
1856 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
682011ff
WD		 1857#endif
1858
aa070789
RZ		 1859 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1860 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1861 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1862 /* Relaxed ordering must be disabled to avoid a parity
1863 * error crash in a PCI slot. */
1864 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1865 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1866 }
1867
682011ff
WD		 1868 return ret_val;
1869}
1870
1871/******************************************************************************
1872 * Configures flow control and link settings.
8bde7f77 1873 *
682011ff 1874 * hw - Struct containing variables accessed by shared code
8bde7f77 1875 *
682011ff
WD		 1876 * Determines which flow control settings to use. Calls the apropriate media-
1877 * specific link configuration function. Configures the flow control settings.
1878 * Assuming the adapter has a valid link partner, a valid link should be
8bde7f77 1879 * established. Assumes the hardware has previously been reset and the
682011ff
WD		 1880 * transmitter and receiver are not enabled.
1881 *****************************************************************************/
1882static int
5c5e707a 1883e1000_setup_link(struct e1000_hw *hw)
682011ff 1884{
682011ff 1885 int32_t ret_val;
8712adfd
RI		 1886#ifndef CONFIG_E1000_NO_NVM
1887 uint32_t ctrl_ext;
682011ff 1888 uint16_t eeprom_data;
8712adfd 1889#endif
682011ff
WD		 1890
1891 DEBUGFUNC();
1892
aa070789
RZ		 1893 /* In the case of the phy reset being blocked, we already have a link.
1894 * We do not have to set it up again. */
1895 if (e1000_check_phy_reset_block(hw))
1896 return E1000_SUCCESS;
1897
8712adfd 1898#ifndef CONFIG_E1000_NO_NVM
682011ff
WD		 1899 /* Read and store word 0x0F of the EEPROM. This word contains bits
1900 * that determine the hardware's default PAUSE (flow control) mode,
1901 * a bit that determines whether the HW defaults to enabling or
1902 * disabling auto-negotiation, and the direction of the
1903 * SW defined pins. If there is no SW over-ride of the flow
1904 * control setting, then the variable hw->fc will
1905 * be initialized based on a value in the EEPROM.
1906 */
aa070789
RZ		 1907 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1908 &eeprom_data) < 0) {
682011ff
WD		 1909 DEBUGOUT("EEPROM Read Error\n");
1910 return -E1000_ERR_EEPROM;
1911 }
8712adfd 1912#endif
682011ff 1913 if (hw->fc == e1000_fc_default) {
aa070789
RZ		 1914 switch (hw->mac_type) {
1915 case e1000_ich8lan:
1916 case e1000_82573:
2c2668f9 1917 case e1000_82574:
95186063 1918 case e1000_igb:
682011ff 1919 hw->fc = e1000_fc_full;
aa070789
RZ		 1920 break;
1921 default:
8712adfd 1922#ifndef CONFIG_E1000_NO_NVM
aa070789
RZ		 1923 ret_val = e1000_read_eeprom(hw,
1924 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1925 if (ret_val) {
1926 DEBUGOUT("EEPROM Read Error\n");
1927 return -E1000_ERR_EEPROM;
1928 }
aa070789
RZ		 1929 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1930 hw->fc = e1000_fc_none;
1931 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1932 EEPROM_WORD0F_ASM_DIR)
1933 hw->fc = e1000_fc_tx_pause;
1934 else
8712adfd 1935#endif
aa070789
RZ		 1936 hw->fc = e1000_fc_full;
1937 break;
1938 }
682011ff
WD		 1939 }
1940
1941 /* We want to save off the original Flow Control configuration just
1942 * in case we get disconnected and then reconnected into a different
1943 * hub or switch with different Flow Control capabilities.
1944 */
1945 if (hw->mac_type == e1000_82542_rev2_0)
1946 hw->fc &= (~e1000_fc_tx_pause);
1947
1948 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1949 hw->fc &= (~e1000_fc_rx_pause);
1950
1951 hw->original_fc = hw->fc;
1952
1953 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1954
8712adfd 1955#ifndef CONFIG_E1000_NO_NVM
682011ff
WD		 1956 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1957 * polarity value for the SW controlled pins, and setup the
1958 * Extended Device Control reg with that info.
1959 * This is needed because one of the SW controlled pins is used for
1960 * signal detection. So this should be done before e1000_setup_pcs_link()
1961 * or e1000_phy_setup() is called.
1962 */
1963 if (hw->mac_type == e1000_82543) {
1964 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1965 SWDPIO__EXT_SHIFT);
1966 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1967 }
8712adfd 1968#endif
682011ff
WD		 1969
1970 /* Call the necessary subroutine to configure the link. */
1971 ret_val = (hw->media_type == e1000_media_type_fiber) ?
5c5e707a 1972 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
682011ff
WD		 1973 if (ret_val < 0) {
1974 return ret_val;
1975 }
1976
1977 /* Initialize the flow control address, type, and PAUSE timer
1978 * registers to their default values. This is done even if flow
1979 * control is disabled, because it does not hurt anything to
1980 * initialize these registers.
1981 */
aa070789
RZ		 1982 DEBUGOUT("Initializing the Flow Control address, type"
1983 "and timer regs\n");
1984
1985 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1986 if (hw->mac_type != e1000_ich8lan) {
1987 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1988 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1989 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1990 }
682011ff 1991
682011ff
WD		 1992 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1993
1994 /* Set the flow control receive threshold registers. Normally,
1995 * these registers will be set to a default threshold that may be
1996 * adjusted later by the driver's runtime code. However, if the
1997 * ability to transmit pause frames in not enabled, then these
8bde7f77 1998 * registers will be set to 0.
682011ff
WD		 1999 */
2000 if (!(hw->fc & e1000_fc_tx_pause)) {
2001 E1000_WRITE_REG(hw, FCRTL, 0);
2002 E1000_WRITE_REG(hw, FCRTH, 0);
2003 } else {
2004 /* We need to set up the Receive Threshold high and low water marks
2005 * as well as (optionally) enabling the transmission of XON frames.
2006 */
2007 if (hw->fc_send_xon) {
2008 E1000_WRITE_REG(hw, FCRTL,
2009 (hw->fc_low_water | E1000_FCRTL_XONE));
2010 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2011 } else {
2012 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2013 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2014 }
2015 }
2016 return ret_val;
2017}
2018
2019/******************************************************************************
2020 * Sets up link for a fiber based adapter
2021 *
2022 * hw - Struct containing variables accessed by shared code
2023 *
2024 * Manipulates Physical Coding Sublayer functions in order to configure
2025 * link. Assumes the hardware has been previously reset and the transmitter
2026 * and receiver are not enabled.
2027 *****************************************************************************/
2028static int
5c5e707a 2029e1000_setup_fiber_link(struct e1000_hw *hw)
682011ff 2030{
682011ff
WD		 2031 uint32_t ctrl;
2032 uint32_t status;
2033 uint32_t txcw = 0;
2034 uint32_t i;
2035 uint32_t signal;
2036 int32_t ret_val;
2037
2038 DEBUGFUNC();
8bde7f77
WD		 2039 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2040 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 2041 * cleared when there is a signal
2042 */
2043 ctrl = E1000_READ_REG(hw, CTRL);
2044 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2045 signal = E1000_CTRL_SWDPIN1;
2046 else
2047 signal = 0;
2048
5c5e707a 2049 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
682011ff
WD		 2050 ctrl);
2051 /* Take the link out of reset */
2052 ctrl &= ~(E1000_CTRL_LRST);
2053
2054 e1000_config_collision_dist(hw);
2055
2056 /* Check for a software override of the flow control settings, and setup
2057 * the device accordingly. If auto-negotiation is enabled, then software
2058 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2059 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
8bde7f77 2060 * auto-negotiation is disabled, then software will have to manually
682011ff
WD		 2061 * configure the two flow control enable bits in the CTRL register.
2062 *
2063 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 2064 * 0: Flow control is completely disabled
2065 * 1: Rx flow control is enabled (we can receive pause frames, but
2066 * not send pause frames).
2067 * 2: Tx flow control is enabled (we can send pause frames but we do
2068 * not support receiving pause frames).
2069 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff
WD		 2070 */
2071 switch (hw->fc) {
2072 case e1000_fc_none:
2073 /* Flow control is completely disabled by a software over-ride. */
2074 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2075 break;
2076 case e1000_fc_rx_pause:
8bde7f77
WD		 2077 /* RX Flow control is enabled and TX Flow control is disabled by a
2078 * software over-ride. Since there really isn't a way to advertise
682011ff
WD		 2079 * that we are capable of RX Pause ONLY, we will advertise that we
2080 * support both symmetric and asymmetric RX PAUSE. Later, we will
2081 * disable the adapter's ability to send PAUSE frames.
2082 */
2083 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2084 break;
2085 case e1000_fc_tx_pause:
8bde7f77 2086 /* TX Flow control is enabled, and RX Flow control is disabled, by a
682011ff
WD		 2087 * software over-ride.
2088 */
2089 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2090 break;
2091 case e1000_fc_full:
2092 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2093 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2094 break;
2095 default:
2096 DEBUGOUT("Flow control param set incorrectly\n");
2097 return -E1000_ERR_CONFIG;
2098 break;
2099 }
2100
2101 /* Since auto-negotiation is enabled, take the link out of reset (the link
2102 * will be in reset, because we previously reset the chip). This will
2103 * restart auto-negotiation. If auto-neogtiation is successful then the
2104 * link-up status bit will be set and the flow control enable bits (RFCE
2105 * and TFCE) will be set according to their negotiated value.
2106 */
2107 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2108
2109 E1000_WRITE_REG(hw, TXCW, txcw);
2110 E1000_WRITE_REG(hw, CTRL, ctrl);
2111 E1000_WRITE_FLUSH(hw);
2112
2113 hw->txcw = txcw;
2114 mdelay(1);
2115
2116 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
8bde7f77
WD		 2117 * indication in the Device Status Register. Time-out if a link isn't
2118 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
682011ff
WD		 2119 * less than 500 milliseconds even if the other end is doing it in SW).
2120 */
2121 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2122 DEBUGOUT("Looking for Link\n");
2123 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2124 mdelay(10);
2125 status = E1000_READ_REG(hw, STATUS);
2126 if (status & E1000_STATUS_LU)
2127 break;
2128 }
2129 if (i == (LINK_UP_TIMEOUT / 10)) {
8bde7f77 2130 /* AutoNeg failed to achieve a link, so we'll call
682011ff
WD		 2131 * e1000_check_for_link. This routine will force the link up if we
2132 * detect a signal. This will allow us to communicate with
2133 * non-autonegotiating link partners.
2134 */
2135 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2136 hw->autoneg_failed = 1;
5c5e707a 2137 ret_val = e1000_check_for_link(hw);
682011ff
WD		 2138 if (ret_val < 0) {
2139 DEBUGOUT("Error while checking for link\n");
2140 return ret_val;
2141 }
2142 hw->autoneg_failed = 0;
2143 } else {
2144 hw->autoneg_failed = 0;
2145 DEBUGOUT("Valid Link Found\n");
2146 }
aa070789
RZ		 2147 } else {
2148 DEBUGOUT("No Signal Detected\n");
2149 return -E1000_ERR_NOLINK;
2150 }
2151 return 0;
2152}
2153
aa070789
RZ		 2154/******************************************************************************
2155* Make sure we have a valid PHY and change PHY mode before link setup.
2156*
2157* hw - Struct containing variables accessed by shared code
2158******************************************************************************/
2159static int32_t
2160e1000_copper_link_preconfig(struct e1000_hw *hw)
2161{
2162 uint32_t ctrl;
2163 int32_t ret_val;
2164 uint16_t phy_data;
2165
2166 DEBUGFUNC();
2167
2168 ctrl = E1000_READ_REG(hw, CTRL);
2169 /* With 82543, we need to force speed and duplex on the MAC equal to what
2170 * the PHY speed and duplex configuration is. In addition, we need to
2171 * perform a hardware reset on the PHY to take it out of reset.
2172 */
2173 if (hw->mac_type > e1000_82543) {
2174 ctrl |= E1000_CTRL_SLU;
2175 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2176 E1000_WRITE_REG(hw, CTRL, ctrl);
2177 } else {
2178 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2179 | E1000_CTRL_SLU);
2180 E1000_WRITE_REG(hw, CTRL, ctrl);
2181 ret_val = e1000_phy_hw_reset(hw);
2182 if (ret_val)
2183 return ret_val;
2184 }
2185
2186 /* Make sure we have a valid PHY */
2187 ret_val = e1000_detect_gig_phy(hw);
2188 if (ret_val) {
2189 DEBUGOUT("Error, did not detect valid phy.\n");
2190 return ret_val;
2191 }
5abf13e4 2192 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
aa070789 2193
aa070789
RZ		 2194 /* Set PHY to class A mode (if necessary) */
2195 ret_val = e1000_set_phy_mode(hw);
2196 if (ret_val)
2197 return ret_val;
aa070789
RZ		 2198 if ((hw->mac_type == e1000_82545_rev_3) ||
2199 (hw->mac_type == e1000_82546_rev_3)) {
2200 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2201 &phy_data);
2202 phy_data |= 0x00000008;
2203 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2204 phy_data);
2205 }
2206
2207 if (hw->mac_type <= e1000_82543 ||
2208 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2209 hw->mac_type == e1000_82541_rev_2
2210 || hw->mac_type == e1000_82547_rev_2)
472d5460 2211 hw->phy_reset_disable = false;
aa070789
RZ		 2212
2213 return E1000_SUCCESS;
2214}
2215
2216/*****************************************************************************
2217 *
2218 * This function sets the lplu state according to the active flag. When
2219 * activating lplu this function also disables smart speed and vise versa.
2220 * lplu will not be activated unless the device autonegotiation advertisment
2221 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2222 * hw: Struct containing variables accessed by shared code
2223 * active - true to enable lplu false to disable lplu.
2224 *
2225 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2226 * E1000_SUCCESS at any other case.
2227 *
2228 ****************************************************************************/
2229
2230static int32_t
472d5460 2231e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
aa070789
RZ		 2232{
2233 uint32_t phy_ctrl = 0;
2234 int32_t ret_val;
2235 uint16_t phy_data;
2236 DEBUGFUNC();
2237
2238 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2239 && hw->phy_type != e1000_phy_igp_3)
2240 return E1000_SUCCESS;
2241
2242 /* During driver activity LPLU should not be used or it will attain link
2243 * from the lowest speeds starting from 10Mbps. The capability is used
2244 * for Dx transitions and states */
2245 if (hw->mac_type == e1000_82541_rev_2
2246 || hw->mac_type == e1000_82547_rev_2) {
2247 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2248 &phy_data);
2249 if (ret_val)
2250 return ret_val;
2251 } else if (hw->mac_type == e1000_ich8lan) {
2252 /* MAC writes into PHY register based on the state transition
2253 * and start auto-negotiation. SW driver can overwrite the
2254 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2255 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2256 } else {
2257 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2258 &phy_data);
2259 if (ret_val)
2260 return ret_val;
2261 }
2262
2263 if (!active) {
2264 if (hw->mac_type == e1000_82541_rev_2 ||
2265 hw->mac_type == e1000_82547_rev_2) {
2266 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2267 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2268 phy_data);
2269 if (ret_val)
2270 return ret_val;
2271 } else {
2272 if (hw->mac_type == e1000_ich8lan) {
2273 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2274 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2275 } else {
2276 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2277 ret_val = e1000_write_phy_reg(hw,
2278 IGP02E1000_PHY_POWER_MGMT, phy_data);
2279 if (ret_val)
2280 return ret_val;
2281 }
2282 }
2283
2284 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2285 * Dx states where the power conservation is most important. During
2286 * driver activity we should enable SmartSpeed, so performance is
2287 * maintained. */
2288 if (hw->smart_speed == e1000_smart_speed_on) {
2289 ret_val = e1000_read_phy_reg(hw,
2290 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2291 if (ret_val)
2292 return ret_val;
2293
2294 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2295 ret_val = e1000_write_phy_reg(hw,
2296 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2297 if (ret_val)
2298 return ret_val;
2299 } else if (hw->smart_speed == e1000_smart_speed_off) {
2300 ret_val = e1000_read_phy_reg(hw,
2301 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2302 if (ret_val)
2303 return ret_val;
2304
2305 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2306 ret_val = e1000_write_phy_reg(hw,
2307 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2308 if (ret_val)
2309 return ret_val;
2310 }
2311
2312 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2313 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2314 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2315
2316 if (hw->mac_type == e1000_82541_rev_2 ||
2317 hw->mac_type == e1000_82547_rev_2) {
2318 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2319 ret_val = e1000_write_phy_reg(hw,
2320 IGP01E1000_GMII_FIFO, phy_data);
2321 if (ret_val)
2322 return ret_val;
2323 } else {
2324 if (hw->mac_type == e1000_ich8lan) {
2325 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2326 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2327 } else {
2328 phy_data |= IGP02E1000_PM_D3_LPLU;
2329 ret_val = e1000_write_phy_reg(hw,
2330 IGP02E1000_PHY_POWER_MGMT, phy_data);
2331 if (ret_val)
2332 return ret_val;
2333 }
2334 }
2335
2336 /* When LPLU is enabled we should disable SmartSpeed */
2337 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2338 &phy_data);
2339 if (ret_val)
2340 return ret_val;
2341
2342 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2343 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2344 phy_data);
2345 if (ret_val)
2346 return ret_val;
2347 }
2348 return E1000_SUCCESS;
2349}
2350
2351/*****************************************************************************
2352 *
2353 * This function sets the lplu d0 state according to the active flag. When
2354 * activating lplu this function also disables smart speed and vise versa.
2355 * lplu will not be activated unless the device autonegotiation advertisment
2356 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2357 * hw: Struct containing variables accessed by shared code
2358 * active - true to enable lplu false to disable lplu.
2359 *
2360 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2361 * E1000_SUCCESS at any other case.
2362 *
2363 ****************************************************************************/
2364
2365static int32_t
472d5460 2366e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
aa070789
RZ		 2367{
2368 uint32_t phy_ctrl = 0;
2369 int32_t ret_val;
2370 uint16_t phy_data;
2371 DEBUGFUNC();
2372
2373 if (hw->mac_type <= e1000_82547_rev_2)
2374 return E1000_SUCCESS;
2375
2376 if (hw->mac_type == e1000_ich8lan) {
2377 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
95186063
MV		 2378 } else if (hw->mac_type == e1000_igb) {
2379 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
aa070789
RZ		 2380 } else {
2381 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2382 &phy_data);
2383 if (ret_val)
2384 return ret_val;
2385 }
2386
2387 if (!active) {
2388 if (hw->mac_type == e1000_ich8lan) {
2389 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2390 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
95186063
MV		 2391 } else if (hw->mac_type == e1000_igb) {
2392 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2393 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
aa070789
RZ		 2394 } else {
2395 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2396 ret_val = e1000_write_phy_reg(hw,
2397 IGP02E1000_PHY_POWER_MGMT, phy_data);
2398 if (ret_val)
2399 return ret_val;
2400 }
2401
95186063
MV		 2402 if (hw->mac_type == e1000_igb)
2403 return E1000_SUCCESS;
2404
aa070789
RZ		 2405 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2406 * Dx states where the power conservation is most important. During
2407 * driver activity we should enable SmartSpeed, so performance is
2408 * maintained. */
2409 if (hw->smart_speed == e1000_smart_speed_on) {
2410 ret_val = e1000_read_phy_reg(hw,
2411 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2412 if (ret_val)
2413 return ret_val;
2414
2415 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2416 ret_val = e1000_write_phy_reg(hw,
2417 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2418 if (ret_val)
2419 return ret_val;
2420 } else if (hw->smart_speed == e1000_smart_speed_off) {
2421 ret_val = e1000_read_phy_reg(hw,
2422 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2423 if (ret_val)
2424 return ret_val;
2425
2426 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2427 ret_val = e1000_write_phy_reg(hw,
2428 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2429 if (ret_val)
2430 return ret_val;
2431 }
2432
2433
2434 } else {
2435
2436 if (hw->mac_type == e1000_ich8lan) {
2437 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2438 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
95186063
MV		 2439 } else if (hw->mac_type == e1000_igb) {
2440 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2441 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
aa070789
RZ		 2442 } else {
2443 phy_data |= IGP02E1000_PM_D0_LPLU;
2444 ret_val = e1000_write_phy_reg(hw,
2445 IGP02E1000_PHY_POWER_MGMT, phy_data);
2446 if (ret_val)
2447 return ret_val;
2448 }
2449
95186063
MV		 2450 if (hw->mac_type == e1000_igb)
2451 return E1000_SUCCESS;
2452
aa070789
RZ		 2453 /* When LPLU is enabled we should disable SmartSpeed */
2454 ret_val = e1000_read_phy_reg(hw,
2455 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2456 if (ret_val)
2457 return ret_val;
2458
2459 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2460 ret_val = e1000_write_phy_reg(hw,
2461 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2462 if (ret_val)
2463 return ret_val;
2464
2465 }
2466 return E1000_SUCCESS;
2467}
2468
2469/********************************************************************
2470* Copper link setup for e1000_phy_igp series.
2471*
2472* hw - Struct containing variables accessed by shared code
2473*********************************************************************/
2474static int32_t
2475e1000_copper_link_igp_setup(struct e1000_hw *hw)
2476{
2477 uint32_t led_ctrl;
2478 int32_t ret_val;
2479 uint16_t phy_data;
2480
f81ecb5d 2481 DEBUGFUNC();
aa070789
RZ		 2482
2483 if (hw->phy_reset_disable)
2484 return E1000_SUCCESS;
2485
2486 ret_val = e1000_phy_reset(hw);
2487 if (ret_val) {
2488 DEBUGOUT("Error Resetting the PHY\n");
2489 return ret_val;
2490 }
2491
2492 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2493 mdelay(15);
2494 if (hw->mac_type != e1000_ich8lan) {
2495 /* Configure activity LED after PHY reset */
2496 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2497 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2498 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2499 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2500 }
2501
2502 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2503 if (hw->phy_type == e1000_phy_igp) {
2504 /* disable lplu d3 during driver init */
472d5460 2505 ret_val = e1000_set_d3_lplu_state(hw, false);
aa070789
RZ		 2506 if (ret_val) {
2507 DEBUGOUT("Error Disabling LPLU D3\n");
2508 return ret_val;
2509 }
2510 }
2511
2512 /* disable lplu d0 during driver init */
472d5460 2513 ret_val = e1000_set_d0_lplu_state(hw, false);
aa070789
RZ		 2514 if (ret_val) {
2515 DEBUGOUT("Error Disabling LPLU D0\n");
2516 return ret_val;
2517 }
2518 /* Configure mdi-mdix settings */
2519 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2520 if (ret_val)
2521 return ret_val;
2522
2523 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2524 hw->dsp_config_state = e1000_dsp_config_disabled;
2525 /* Force MDI for earlier revs of the IGP PHY */
2526 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2527 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2528 hw->mdix = 1;
2529
2530 } else {
2531 hw->dsp_config_state = e1000_dsp_config_enabled;
2532 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2533
2534 switch (hw->mdix) {
2535 case 1:
2536 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2537 break;
2538 case 2:
2539 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2540 break;
2541 case 0:
2542 default:
2543 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2544 break;
2545 }
2546 }
2547 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2548 if (ret_val)
2549 return ret_val;
2550
2551 /* set auto-master slave resolution settings */
2552 if (hw->autoneg) {
2553 e1000_ms_type phy_ms_setting = hw->master_slave;
2554
2555 if (hw->ffe_config_state == e1000_ffe_config_active)
2556 hw->ffe_config_state = e1000_ffe_config_enabled;
2557
2558 if (hw->dsp_config_state == e1000_dsp_config_activated)
2559 hw->dsp_config_state = e1000_dsp_config_enabled;
2560
2561 /* when autonegotiation advertisment is only 1000Mbps then we
2562 * should disable SmartSpeed and enable Auto MasterSlave
2563 * resolution as hardware default. */
2564 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2565 /* Disable SmartSpeed */
2566 ret_val = e1000_read_phy_reg(hw,
2567 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2568 if (ret_val)
2569 return ret_val;
2570 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2571 ret_val = e1000_write_phy_reg(hw,
2572 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2573 if (ret_val)
2574 return ret_val;
2575 /* Set auto Master/Slave resolution process */
2576 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2577 &phy_data);
2578 if (ret_val)
2579 return ret_val;
2580 phy_data &= ~CR_1000T_MS_ENABLE;
2581 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2582 phy_data);
2583 if (ret_val)
2584 return ret_val;
2585 }
2586
2587 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2588 if (ret_val)
2589 return ret_val;
2590
2591 /* load defaults for future use */
2592 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2593 ((phy_data & CR_1000T_MS_VALUE) ?
2594 e1000_ms_force_master :
2595 e1000_ms_force_slave) :
2596 e1000_ms_auto;
2597
2598 switch (phy_ms_setting) {
2599 case e1000_ms_force_master:
2600 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2601 break;
2602 case e1000_ms_force_slave:
2603 phy_data |= CR_1000T_MS_ENABLE;
2604 phy_data &= ~(CR_1000T_MS_VALUE);
2605 break;
2606 case e1000_ms_auto:
2607 phy_data &= ~CR_1000T_MS_ENABLE;
2608 default:
2609 break;
2610 }
2611 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2612 if (ret_val)
2613 return ret_val;
2614 }
2615
2616 return E1000_SUCCESS;
2617}
2618
2619/*****************************************************************************
2620 * This function checks the mode of the firmware.
2621 *
472d5460 2622 * returns - true when the mode is IAMT or false.
aa070789 2623 ****************************************************************************/
472d5460 2624bool
aa070789
RZ		 2625e1000_check_mng_mode(struct e1000_hw *hw)
2626{
2627 uint32_t fwsm;
2628 DEBUGFUNC();
2629
2630 fwsm = E1000_READ_REG(hw, FWSM);
2631
2632 if (hw->mac_type == e1000_ich8lan) {
2633 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2634 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
472d5460 2635 return true;
aa070789
RZ		 2636 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2637 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
472d5460 2638 return true;
aa070789 2639
472d5460 2640 return false;
aa070789
RZ		 2641}
2642
2643static int32_t
2644e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2645{
987b43a1 2646 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789 2647 uint32_t reg_val;
aa070789
RZ		 2648 DEBUGFUNC();
2649
987b43a1 2650 if (e1000_is_second_port(hw))
aa070789 2651 swfw = E1000_SWFW_PHY1_SM;
987b43a1 2652
aa070789
RZ		 2653 if (e1000_swfw_sync_acquire(hw, swfw))
2654 return -E1000_ERR_SWFW_SYNC;
2655
2656 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2657 & E1000_KUMCTRLSTA_OFFSET) | data;
2658 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2659 udelay(2);
2660
2661 return E1000_SUCCESS;
2662}
2663
2664static int32_t
2665e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2666{
987b43a1 2667 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789 2668 uint32_t reg_val;
aa070789
RZ		 2669 DEBUGFUNC();
2670
987b43a1 2671 if (e1000_is_second_port(hw))
aa070789 2672 swfw = E1000_SWFW_PHY1_SM;
987b43a1 2673
95186063
MV		 2674 if (e1000_swfw_sync_acquire(hw, swfw)) {
2675 debug("%s[%i]\n", __func__, __LINE__);
aa070789 2676 return -E1000_ERR_SWFW_SYNC;
95186063 2677 }
aa070789
RZ		 2678
2679 /* Write register address */
2680 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2681 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2682 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2683 udelay(2);
2684
2685 /* Read the data returned */
2686 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2687 *data = (uint16_t)reg_val;
2688
2689 return E1000_SUCCESS;
2690}
2691
2692/********************************************************************
2693* Copper link setup for e1000_phy_gg82563 series.
2694*
2695* hw - Struct containing variables accessed by shared code
2696*********************************************************************/
2697static int32_t
2698e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2699{
2700 int32_t ret_val;
2701 uint16_t phy_data;
2702 uint32_t reg_data;
2703
2704 DEBUGFUNC();
2705
2706 if (!hw->phy_reset_disable) {
2707 /* Enable CRS on TX for half-duplex operation. */
2708 ret_val = e1000_read_phy_reg(hw,
2709 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2710 if (ret_val)
2711 return ret_val;
2712
2713 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2714 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2715 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2716
2717 ret_val = e1000_write_phy_reg(hw,
2718 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2719 if (ret_val)
2720 return ret_val;
2721
2722 /* Options:
2723 * MDI/MDI-X = 0 (default)
2724 * 0 - Auto for all speeds
2725 * 1 - MDI mode
2726 * 2 - MDI-X mode
2727 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2728 */
2729 ret_val = e1000_read_phy_reg(hw,
2730 GG82563_PHY_SPEC_CTRL, &phy_data);
2731 if (ret_val)
2732 return ret_val;
2733
2734 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2735
2736 switch (hw->mdix) {
2737 case 1:
2738 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2739 break;
2740 case 2:
2741 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2742 break;
2743 case 0:
2744 default:
2745 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2746 break;
2747 }
2748
2749 /* Options:
2750 * disable_polarity_correction = 0 (default)
2751 * Automatic Correction for Reversed Cable Polarity
2752 * 0 - Disabled
2753 * 1 - Enabled
2754 */
2755 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2756 ret_val = e1000_write_phy_reg(hw,
2757 GG82563_PHY_SPEC_CTRL, phy_data);
2758
2759 if (ret_val)
2760 return ret_val;
2761
2762 /* SW Reset the PHY so all changes take effect */
2763 ret_val = e1000_phy_reset(hw);
2764 if (ret_val) {
2765 DEBUGOUT("Error Resetting the PHY\n");
2766 return ret_val;
2767 }
2768 } /* phy_reset_disable */
2769
2770 if (hw->mac_type == e1000_80003es2lan) {
2771 /* Bypass RX and TX FIFO's */
2772 ret_val = e1000_write_kmrn_reg(hw,
2773 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2774 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2775 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2776 if (ret_val)
2777 return ret_val;
2778
2779 ret_val = e1000_read_phy_reg(hw,
2780 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2781 if (ret_val)
2782 return ret_val;
2783
2784 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2785 ret_val = e1000_write_phy_reg(hw,
2786 GG82563_PHY_SPEC_CTRL_2, phy_data);
2787
2788 if (ret_val)
2789 return ret_val;
2790
2791 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2792 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2793 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2794
2795 ret_val = e1000_read_phy_reg(hw,
2796 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2797 if (ret_val)
2798 return ret_val;
2799
2800 /* Do not init these registers when the HW is in IAMT mode, since the
2801 * firmware will have already initialized them. We only initialize
2802 * them if the HW is not in IAMT mode.
2803 */
472d5460 2804 if (e1000_check_mng_mode(hw) == false) {
aa070789
RZ		 2805 /* Enable Electrical Idle on the PHY */
2806 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2807 ret_val = e1000_write_phy_reg(hw,
2808 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2809 if (ret_val)
2810 return ret_val;
2811
2812 ret_val = e1000_read_phy_reg(hw,
2813 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2814 if (ret_val)
2815 return ret_val;
2816
2817 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2818 ret_val = e1000_write_phy_reg(hw,
2819 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2820
2821 if (ret_val)
2822 return ret_val;
2823 }
2824
2825 /* Workaround: Disable padding in Kumeran interface in the MAC
2826 * and in the PHY to avoid CRC errors.
2827 */
2828 ret_val = e1000_read_phy_reg(hw,
2829 GG82563_PHY_INBAND_CTRL, &phy_data);
2830 if (ret_val)
2831 return ret_val;
2832 phy_data |= GG82563_ICR_DIS_PADDING;
2833 ret_val = e1000_write_phy_reg(hw,
2834 GG82563_PHY_INBAND_CTRL, phy_data);
2835 if (ret_val)
2836 return ret_val;
682011ff 2837 }
aa070789 2838 return E1000_SUCCESS;
682011ff
WD		 2839}
2840
aa070789
RZ		 2841/********************************************************************
2842* Copper link setup for e1000_phy_m88 series.
682011ff
WD		 2843*
2844* hw - Struct containing variables accessed by shared code
aa070789
RZ		 2845*********************************************************************/
2846static int32_t
2847e1000_copper_link_mgp_setup(struct e1000_hw *hw)
682011ff 2848{
682011ff 2849 int32_t ret_val;
682011ff
WD		 2850 uint16_t phy_data;
2851
2852 DEBUGFUNC();
2853
aa070789
RZ		 2854 if (hw->phy_reset_disable)
2855 return E1000_SUCCESS;
682011ff 2856
aa070789
RZ		 2857 /* Enable CRS on TX. This must be set for half-duplex operation. */
2858 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2859 if (ret_val)
682011ff 2860 return ret_val;
682011ff 2861
682011ff
WD		 2862 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2863
682011ff
WD		 2864 /* Options:
2865 * MDI/MDI-X = 0 (default)
2866 * 0 - Auto for all speeds
2867 * 1 - MDI mode
2868 * 2 - MDI-X mode
2869 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2870 */
2871 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
aa070789 2872
682011ff
WD		 2873 switch (hw->mdix) {
2874 case 1:
2875 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2876 break;
2877 case 2:
2878 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2879 break;
2880 case 3:
2881 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2882 break;
2883 case 0:
2884 default:
2885 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2886 break;
2887 }
682011ff 2888
682011ff
WD		 2889 /* Options:
2890 * disable_polarity_correction = 0 (default)
aa070789 2891 * Automatic Correction for Reversed Cable Polarity
682011ff
WD		 2892 * 0 - Disabled
2893 * 1 - Enabled
2894 */
2895 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
aa070789
RZ		 2896 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2897 if (ret_val)
2898 return ret_val;
682011ff 2899
aa070789
RZ		 2900 if (hw->phy_revision < M88E1011_I_REV_4) {
2901 /* Force TX_CLK in the Extended PHY Specific Control Register
2902 * to 25MHz clock.
2903 */
2904 ret_val = e1000_read_phy_reg(hw,
2905 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2906 if (ret_val)
2907 return ret_val;
2908
2909 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2910
2911 if ((hw->phy_revision == E1000_REVISION_2) &&
2912 (hw->phy_id == M88E1111_I_PHY_ID)) {
2913 /* Vidalia Phy, set the downshift counter to 5x */
2914 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2915 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2916 ret_val = e1000_write_phy_reg(hw,
2917 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2918 if (ret_val)
2919 return ret_val;
2920 } else {
2921 /* Configure Master and Slave downshift values */
2922 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2923 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2924 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2925 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2926 ret_val = e1000_write_phy_reg(hw,
2927 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2928 if (ret_val)
2929 return ret_val;
2930 }
682011ff
WD		 2931 }
2932
2933 /* SW Reset the PHY so all changes take effect */
2934 ret_val = e1000_phy_reset(hw);
aa070789 2935 if (ret_val) {
682011ff
WD		 2936 DEBUGOUT("Error Resetting the PHY\n");
2937 return ret_val;
2938 }
2939
aa070789
RZ		 2940 return E1000_SUCCESS;
2941}
2942
2943/********************************************************************
2944* Setup auto-negotiation and flow control advertisements,
2945* and then perform auto-negotiation.
2946*
2947* hw - Struct containing variables accessed by shared code
2948*********************************************************************/
2949static int32_t
2950e1000_copper_link_autoneg(struct e1000_hw *hw)
2951{
2952 int32_t ret_val;
2953 uint16_t phy_data;
2954
2955 DEBUGFUNC();
682011ff 2956
682011ff
WD		 2957 /* Perform some bounds checking on the hw->autoneg_advertised
2958 * parameter. If this variable is zero, then set it to the default.
2959 */
2960 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2961
2962 /* If autoneg_advertised is zero, we assume it was not defaulted
2963 * by the calling code so we set to advertise full capability.
2964 */
2965 if (hw->autoneg_advertised == 0)
2966 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2967
aa070789
RZ		 2968 /* IFE phy only supports 10/100 */
2969 if (hw->phy_type == e1000_phy_ife)
2970 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2971
682011ff
WD		 2972 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2973 ret_val = e1000_phy_setup_autoneg(hw);
aa070789 2974 if (ret_val) {
682011ff
WD		 2975 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2976 return ret_val;
2977 }
2978 DEBUGOUT("Restarting Auto-Neg\n");
2979
2980 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2981 * the Auto Neg Restart bit in the PHY control register.
2982 */
aa070789
RZ		 2983 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2984 if (ret_val)
2985 return ret_val;
2986
682011ff 2987 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
aa070789
RZ		 2988 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2989 if (ret_val)
2990 return ret_val;
2991
682011ff
WD		 2992 /* Does the user want to wait for Auto-Neg to complete here, or
2993 * check at a later time (for example, callback routine).
2994 */
aa070789
RZ		 2995 /* If we do not wait for autonegtation to complete I
2996 * do not see a valid link status.
2997 * wait_autoneg_complete = 1 .
2998 */
682011ff
WD		 2999 if (hw->wait_autoneg_complete) {
3000 ret_val = e1000_wait_autoneg(hw);
aa070789
RZ		 3001 if (ret_val) {
3002 DEBUGOUT("Error while waiting for autoneg"
3003 "to complete\n");
682011ff
WD		 3004 return ret_val;
3005 }
3006 }
aa070789 3007
472d5460 3008 hw->get_link_status = true;
aa070789
RZ		 3009
3010 return E1000_SUCCESS;
3011}
3012
3013/******************************************************************************
3014* Config the MAC and the PHY after link is up.
3015* 1) Set up the MAC to the current PHY speed/duplex
3016* if we are on 82543. If we
3017* are on newer silicon, we only need to configure
3018* collision distance in the Transmit Control Register.
3019* 2) Set up flow control on the MAC to that established with
3020* the link partner.
3021* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3022*
3023* hw - Struct containing variables accessed by shared code
3024******************************************************************************/
3025static int32_t
3026e1000_copper_link_postconfig(struct e1000_hw *hw)
3027{
3028 int32_t ret_val;
3029 DEBUGFUNC();
3030
3031 if (hw->mac_type >= e1000_82544) {
3032 e1000_config_collision_dist(hw);
3033 } else {
3034 ret_val = e1000_config_mac_to_phy(hw);
3035 if (ret_val) {
3036 DEBUGOUT("Error configuring MAC to PHY settings\n");
3037 return ret_val;
3038 }
3039 }
3040 ret_val = e1000_config_fc_after_link_up(hw);
3041 if (ret_val) {
3042 DEBUGOUT("Error Configuring Flow Control\n");
682011ff
WD		 3043 return ret_val;
3044 }
aa070789
RZ		 3045 return E1000_SUCCESS;
3046}
3047
3048/******************************************************************************
3049* Detects which PHY is present and setup the speed and duplex
3050*
3051* hw - Struct containing variables accessed by shared code
3052******************************************************************************/
3053static int
5c5e707a 3054e1000_setup_copper_link(struct e1000_hw *hw)
aa070789 3055{
aa070789
RZ		 3056 int32_t ret_val;
3057 uint16_t i;
3058 uint16_t phy_data;
3059 uint16_t reg_data;
3060
3061 DEBUGFUNC();
3062
3063 switch (hw->mac_type) {
3064 case e1000_80003es2lan:
3065 case e1000_ich8lan:
3066 /* Set the mac to wait the maximum time between each
3067 * iteration and increase the max iterations when
3068 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3069 ret_val = e1000_write_kmrn_reg(hw,
3070 GG82563_REG(0x34, 4), 0xFFFF);
3071 if (ret_val)
3072 return ret_val;
3073 ret_val = e1000_read_kmrn_reg(hw,
3074 GG82563_REG(0x34, 9), &reg_data);
3075 if (ret_val)
3076 return ret_val;
3077 reg_data |= 0x3F;
3078 ret_val = e1000_write_kmrn_reg(hw,
3079 GG82563_REG(0x34, 9), reg_data);
3080 if (ret_val)
3081 return ret_val;
3082 default:
3083 break;
3084 }
3085
3086 /* Check if it is a valid PHY and set PHY mode if necessary. */
3087 ret_val = e1000_copper_link_preconfig(hw);
3088 if (ret_val)
3089 return ret_val;
3090 switch (hw->mac_type) {
3091 case e1000_80003es2lan:
3092 /* Kumeran registers are written-only */
3093 reg_data =
3094 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3095 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3096 ret_val = e1000_write_kmrn_reg(hw,
3097 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3098 if (ret_val)
3099 return ret_val;
3100 break;
3101 default:
3102 break;
3103 }
3104
3105 if (hw->phy_type == e1000_phy_igp ||
3106 hw->phy_type == e1000_phy_igp_3 ||
3107 hw->phy_type == e1000_phy_igp_2) {
3108 ret_val = e1000_copper_link_igp_setup(hw);
3109 if (ret_val)
3110 return ret_val;
95186063
MV		 3111 } else if (hw->phy_type == e1000_phy_m88 ||
3112 hw->phy_type == e1000_phy_igb) {
aa070789
RZ		 3113 ret_val = e1000_copper_link_mgp_setup(hw);
3114 if (ret_val)
3115 return ret_val;
3116 } else if (hw->phy_type == e1000_phy_gg82563) {
3117 ret_val = e1000_copper_link_ggp_setup(hw);
3118 if (ret_val)
3119 return ret_val;
3120 }
3121
3122 /* always auto */
3123 /* Setup autoneg and flow control advertisement
3124 * and perform autonegotiation */
3125 ret_val = e1000_copper_link_autoneg(hw);
3126 if (ret_val)
3127 return ret_val;
682011ff
WD		 3128
3129 /* Check link status. Wait up to 100 microseconds for link to become
3130 * valid.
3131 */
3132 for (i = 0; i < 10; i++) {
aa070789
RZ		 3133 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3134 if (ret_val)
3135 return ret_val;
3136 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3137 if (ret_val)
3138 return ret_val;
3139
682011ff 3140 if (phy_data & MII_SR_LINK_STATUS) {
aa070789
RZ		 3141 /* Config the MAC and PHY after link is up */
3142 ret_val = e1000_copper_link_postconfig(hw);
3143 if (ret_val)
682011ff 3144 return ret_val;
aa070789 3145
682011ff 3146 DEBUGOUT("Valid link established!!!\n");
aa070789 3147 return E1000_SUCCESS;
682011ff
WD		 3148 }
3149 udelay(10);
3150 }
3151
3152 DEBUGOUT("Unable to establish link!!!\n");
aa070789 3153 return E1000_SUCCESS;
682011ff
WD		 3154}
3155
3156/******************************************************************************
3157* Configures PHY autoneg and flow control advertisement settings
3158*
3159* hw - Struct containing variables accessed by shared code
3160******************************************************************************/
aa070789 3161int32_t
682011ff
WD		 3162e1000_phy_setup_autoneg(struct e1000_hw *hw)
3163{
aa070789 3164 int32_t ret_val;
682011ff
WD		 3165 uint16_t mii_autoneg_adv_reg;
3166 uint16_t mii_1000t_ctrl_reg;
3167
3168 DEBUGFUNC();
3169
3170 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
aa070789
RZ		 3171 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3172 if (ret_val)
3173 return ret_val;
682011ff 3174
aa070789
RZ		 3175 if (hw->phy_type != e1000_phy_ife) {
3176 /* Read the MII 1000Base-T Control Register (Address 9). */
3177 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3178 &mii_1000t_ctrl_reg);
3179 if (ret_val)
3180 return ret_val;
3181 } else
3182 mii_1000t_ctrl_reg = 0;
682011ff
WD		 3183
3184 /* Need to parse both autoneg_advertised and fc and set up
3185 * the appropriate PHY registers. First we will parse for
3186 * autoneg_advertised software override. Since we can advertise
3187 * a plethora of combinations, we need to check each bit
3188 * individually.
3189 */
3190
3191 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3192 * Advertisement Register (Address 4) and the 1000 mb speed bits in
aa070789 3193 * the 1000Base-T Control Register (Address 9).
682011ff
WD		 3194 */
3195 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3196 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3197
3198 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3199
3200 /* Do we want to advertise 10 Mb Half Duplex? */
3201 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3202 DEBUGOUT("Advertise 10mb Half duplex\n");
3203 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3204 }
3205
3206 /* Do we want to advertise 10 Mb Full Duplex? */
3207 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3208 DEBUGOUT("Advertise 10mb Full duplex\n");
3209 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3210 }
3211
3212 /* Do we want to advertise 100 Mb Half Duplex? */
3213 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3214 DEBUGOUT("Advertise 100mb Half duplex\n");
3215 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3216 }
3217
3218 /* Do we want to advertise 100 Mb Full Duplex? */
3219 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3220 DEBUGOUT("Advertise 100mb Full duplex\n");
3221 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3222 }
3223
3224 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3225 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3226 DEBUGOUT
3227 ("Advertise 1000mb Half duplex requested, request denied!\n");
3228 }
3229
3230 /* Do we want to advertise 1000 Mb Full Duplex? */
3231 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3232 DEBUGOUT("Advertise 1000mb Full duplex\n");
3233 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3234 }
3235
3236 /* Check for a software override of the flow control settings, and
3237 * setup the PHY advertisement registers accordingly. If
3238 * auto-negotiation is enabled, then software will have to set the
3239 * "PAUSE" bits to the correct value in the Auto-Negotiation
3240 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3241 *
3242 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3243 * 0: Flow control is completely disabled
3244 * 1: Rx flow control is enabled (we can receive pause frames
3245 * but not send pause frames).
3246 * 2: Tx flow control is enabled (we can send pause frames
3247 * but we do not support receiving pause frames).
3248 * 3: Both Rx and TX flow control (symmetric) are enabled.
682011ff 3249 * other: No software override. The flow control configuration
1aeed8d7 3250 * in the EEPROM is used.
682011ff
WD		 3251 */
3252 switch (hw->fc) {
3253 case e1000_fc_none: /* 0 */
3254 /* Flow control (RX & TX) is completely disabled by a
3255 * software over-ride.
3256 */
3257 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3258 break;
3259 case e1000_fc_rx_pause: /* 1 */
3260 /* RX Flow control is enabled, and TX Flow control is
3261 * disabled, by a software over-ride.
3262 */
3263 /* Since there really isn't a way to advertise that we are
3264 * capable of RX Pause ONLY, we will advertise that we
3265 * support both symmetric and asymmetric RX PAUSE. Later
3266 * (in e1000_config_fc_after_link_up) we will disable the
3267 *hw's ability to send PAUSE frames.
3268 */
3269 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3270 break;
3271 case e1000_fc_tx_pause: /* 2 */
3272 /* TX Flow control is enabled, and RX Flow control is
3273 * disabled, by a software over-ride.
3274 */
3275 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3276 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3277 break;
3278 case e1000_fc_full: /* 3 */
3279 /* Flow control (both RX and TX) is enabled by a software
3280 * over-ride.
3281 */
3282 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3283 break;
3284 default:
3285 DEBUGOUT("Flow control param set incorrectly\n");
3286 return -E1000_ERR_CONFIG;
3287 }
3288
aa070789
RZ		 3289 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3290 if (ret_val)
3291 return ret_val;
682011ff
WD		 3292
3293 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3294
aa070789
RZ		 3295 if (hw->phy_type != e1000_phy_ife) {
3296 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3297 mii_1000t_ctrl_reg);
3298 if (ret_val)
3299 return ret_val;
682011ff 3300 }
aa070789
RZ		 3301
3302 return E1000_SUCCESS;
682011ff
WD		 3303}
3304
3305/******************************************************************************
3306* Sets the collision distance in the Transmit Control register
3307*
3308* hw - Struct containing variables accessed by shared code
3309*
3310* Link should have been established previously. Reads the speed and duplex
3311* information from the Device Status register.
3312******************************************************************************/
3313static void
3314e1000_config_collision_dist(struct e1000_hw *hw)
3315{
aa070789
RZ		 3316 uint32_t tctl, coll_dist;
3317
3318 DEBUGFUNC();
3319
3320 if (hw->mac_type < e1000_82543)
3321 coll_dist = E1000_COLLISION_DISTANCE_82542;
3322 else
3323 coll_dist = E1000_COLLISION_DISTANCE;
682011ff
WD		 3324
3325 tctl = E1000_READ_REG(hw, TCTL);
3326
3327 tctl &= ~E1000_TCTL_COLD;
aa070789 3328 tctl |= coll_dist << E1000_COLD_SHIFT;
682011ff
WD		 3329
3330 E1000_WRITE_REG(hw, TCTL, tctl);
3331 E1000_WRITE_FLUSH(hw);
3332}
3333
3334/******************************************************************************
3335* Sets MAC speed and duplex settings to reflect the those in the PHY
3336*
3337* hw - Struct containing variables accessed by shared code
3338* mii_reg - data to write to the MII control register
3339*
3340* The contents of the PHY register containing the needed information need to
3341* be passed in.
3342******************************************************************************/
3343static int
3344e1000_config_mac_to_phy(struct e1000_hw *hw)
3345{
3346 uint32_t ctrl;
3347 uint16_t phy_data;
3348
3349 DEBUGFUNC();
3350
3351 /* Read the Device Control Register and set the bits to Force Speed
3352 * and Duplex.
3353 */
3354 ctrl = E1000_READ_REG(hw, CTRL);
3355 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
95186063
MV		 3356 ctrl &= ~(E1000_CTRL_ILOS);
3357 ctrl |= (E1000_CTRL_SPD_SEL);
682011ff
WD		 3358
3359 /* Set up duplex in the Device Control and Transmit Control
3360 * registers depending on negotiated values.
3361 */
3362 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3363 DEBUGOUT("PHY Read Error\n");
3364 return -E1000_ERR_PHY;
3365 }
3366 if (phy_data & M88E1000_PSSR_DPLX)
3367 ctrl |= E1000_CTRL_FD;
3368 else
3369 ctrl &= ~E1000_CTRL_FD;
3370
3371 e1000_config_collision_dist(hw);
3372
3373 /* Set up speed in the Device Control register depending on
3374 * negotiated values.
3375 */
3376 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3377 ctrl |= E1000_CTRL_SPD_1000;
3378 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3379 ctrl |= E1000_CTRL_SPD_100;
3380 /* Write the configured values back to the Device Control Reg. */
3381 E1000_WRITE_REG(hw, CTRL, ctrl);
3382 return 0;
3383}
3384
3385/******************************************************************************
3386 * Forces the MAC's flow control settings.
8bde7f77 3387 *
682011ff
WD		 3388 * hw - Struct containing variables accessed by shared code
3389 *
3390 * Sets the TFCE and RFCE bits in the device control register to reflect
3391 * the adapter settings. TFCE and RFCE need to be explicitly set by
3392 * software when a Copper PHY is used because autonegotiation is managed
3393 * by the PHY rather than the MAC. Software must also configure these
3394 * bits when link is forced on a fiber connection.
3395 *****************************************************************************/
3396static int
3397e1000_force_mac_fc(struct e1000_hw *hw)
3398{
3399 uint32_t ctrl;
3400
3401 DEBUGFUNC();
3402
3403 /* Get the current configuration of the Device Control Register */
3404 ctrl = E1000_READ_REG(hw, CTRL);
3405
3406 /* Because we didn't get link via the internal auto-negotiation
3407 * mechanism (we either forced link or we got link via PHY
3408 * auto-neg), we have to manually enable/disable transmit an
3409 * receive flow control.
3410 *
3411 * The "Case" statement below enables/disable flow control
3412 * according to the "hw->fc" parameter.
3413 *
3414 * The possible values of the "fc" parameter are:
1aeed8d7
WD		 3415 * 0: Flow control is completely disabled
3416 * 1: Rx flow control is enabled (we can receive pause
3417 * frames but not send pause frames).
3418 * 2: Tx flow control is enabled (we can send pause frames
3419 * frames but we do not receive pause frames).
3420 * 3: Both Rx and TX flow control (symmetric) is enabled.
682011ff
WD		 3421 * other: No other values should be possible at this point.
3422 */
3423
3424 switch (hw->fc) {
3425 case e1000_fc_none:
3426 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3427 break;
3428 case e1000_fc_rx_pause:
3429 ctrl &= (~E1000_CTRL_TFCE);
3430 ctrl |= E1000_CTRL_RFCE;
3431 break;
3432 case e1000_fc_tx_pause:
3433 ctrl &= (~E1000_CTRL_RFCE);
3434 ctrl |= E1000_CTRL_TFCE;
3435 break;
3436 case e1000_fc_full:
3437 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3438 break;
3439 default:
3440 DEBUGOUT("Flow control param set incorrectly\n");
3441 return -E1000_ERR_CONFIG;
3442 }
3443
3444 /* Disable TX Flow Control for 82542 (rev 2.0) */
3445 if (hw->mac_type == e1000_82542_rev2_0)
3446 ctrl &= (~E1000_CTRL_TFCE);
3447
3448 E1000_WRITE_REG(hw, CTRL, ctrl);
3449 return 0;
3450}
3451
3452/******************************************************************************
3453 * Configures flow control settings after link is established
8bde7f77 3454 *
682011ff
WD		 3455 * hw - Struct containing variables accessed by shared code
3456 *
3457 * Should be called immediately after a valid link has been established.
3458 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3459 * and autonegotiation is enabled, the MAC flow control settings will be set
3460 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3461 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3462 *****************************************************************************/
aa070789 3463static int32_t
682011ff
WD		 3464e1000_config_fc_after_link_up(struct e1000_hw *hw)
3465{
3466 int32_t ret_val;
3467 uint16_t mii_status_reg;
3468 uint16_t mii_nway_adv_reg;
3469 uint16_t mii_nway_lp_ability_reg;
3470 uint16_t speed;
3471 uint16_t duplex;
3472
3473 DEBUGFUNC();
3474
3475 /* Check for the case where we have fiber media and auto-neg failed
3476 * so we had to force link. In this case, we need to force the
3477 * configuration of the MAC to match the "fc" parameter.
3478 */
aa070789
RZ		 3479 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3480 || ((hw->media_type == e1000_media_type_internal_serdes)
3481 && (hw->autoneg_failed))
3482 || ((hw->media_type == e1000_media_type_copper)
3483 && (!hw->autoneg))) {
682011ff
WD		 3484 ret_val = e1000_force_mac_fc(hw);
3485 if (ret_val < 0) {
3486 DEBUGOUT("Error forcing flow control settings\n");
3487 return ret_val;
3488 }
3489 }
3490
3491 /* Check for the case where we have copper media and auto-neg is
3492 * enabled. In this case, we need to check and see if Auto-Neg
3493 * has completed, and if so, how the PHY and link partner has
3494 * flow control configured.
3495 */
3496 if (hw->media_type == e1000_media_type_copper) {
3497 /* Read the MII Status Register and check to see if AutoNeg
3498 * has completed. We read this twice because this reg has
3499 * some "sticky" (latched) bits.
3500 */
3501 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
5abf13e4 3502 DEBUGOUT("PHY Read Error\n");
682011ff
WD		 3503 return -E1000_ERR_PHY;
3504 }
3505 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
5abf13e4 3506 DEBUGOUT("PHY Read Error\n");
682011ff
WD		 3507 return -E1000_ERR_PHY;
3508 }
3509
3510 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3511 /* The AutoNeg process has completed, so we now need to
3512 * read both the Auto Negotiation Advertisement Register
3513 * (Address 4) and the Auto_Negotiation Base Page Ability
3514 * Register (Address 5) to determine how flow control was
3515 * negotiated.
3516 */
3517 if (e1000_read_phy_reg
3518 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3519 DEBUGOUT("PHY Read Error\n");
3520 return -E1000_ERR_PHY;
3521 }
3522 if (e1000_read_phy_reg
3523 (hw, PHY_LP_ABILITY,
3524 &mii_nway_lp_ability_reg) < 0) {
3525 DEBUGOUT("PHY Read Error\n");
3526 return -E1000_ERR_PHY;
3527 }
3528
3529 /* Two bits in the Auto Negotiation Advertisement Register
3530 * (Address 4) and two bits in the Auto Negotiation Base
3531 * Page Ability Register (Address 5) determine flow control
3532 * for both the PHY and the link partner. The following
3533 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3534 * 1999, describes these PAUSE resolution bits and how flow
3535 * control is determined based upon these settings.
3536 * NOTE: DC = Don't Care
3537 *
3538 * LOCAL DEVICE | LINK PARTNER
3539 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3540 *-------|---------|-------|---------|--------------------
1aeed8d7
WD		 3541 * 0 | 0 | DC | DC | e1000_fc_none
3542 * 0 | 1 | 0 | DC | e1000_fc_none
3543 * 0 | 1 | 1 | 0 | e1000_fc_none
3544 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3545 * 1 | 0 | 0 | DC | e1000_fc_none
3546 * 1 | DC | 1 | DC | e1000_fc_full
3547 * 1 | 1 | 0 | 0 | e1000_fc_none
3548 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3549 *
3550 */
3551 /* Are both PAUSE bits set to 1? If so, this implies
3552 * Symmetric Flow Control is enabled at both ends. The
3553 * ASM_DIR bits are irrelevant per the spec.
3554 *
3555 * For Symmetric Flow Control:
3556 *
3557 * LOCAL DEVICE | LINK PARTNER
3558 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3559 *-------|---------|-------|---------|--------------------
1aeed8d7 3560 * 1 | DC | 1 | DC | e1000_fc_full
682011ff
WD		 3561 *
3562 */
3563 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3564 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3565 /* Now we need to check if the user selected RX ONLY
3566 * of pause frames. In this case, we had to advertise
3567 * FULL flow control because we could not advertise RX
3568 * ONLY. Hence, we must now check to see if we need to
3569 * turn OFF the TRANSMISSION of PAUSE frames.
3570 */
3571 if (hw->original_fc == e1000_fc_full) {
3572 hw->fc = e1000_fc_full;
3573 DEBUGOUT("Flow Control = FULL.\r\n");
3574 } else {
3575 hw->fc = e1000_fc_rx_pause;
3576 DEBUGOUT
3577 ("Flow Control = RX PAUSE frames only.\r\n");
3578 }
3579 }
3580 /* For receiving PAUSE frames ONLY.
3581 *
3582 * LOCAL DEVICE | LINK PARTNER
3583 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3584 *-------|---------|-------|---------|--------------------
1aeed8d7 3585 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
682011ff
WD		 3586 *
3587 */
3588 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3589 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3590 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3591 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3592 {
3593 hw->fc = e1000_fc_tx_pause;
3594 DEBUGOUT
3595 ("Flow Control = TX PAUSE frames only.\r\n");
3596 }
3597 /* For transmitting PAUSE frames ONLY.
3598 *
3599 * LOCAL DEVICE | LINK PARTNER
3600 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3601 *-------|---------|-------|---------|--------------------
1aeed8d7 3602 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
682011ff
WD		 3603 *
3604 */
3605 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3606 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3607 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3608 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3609 {
3610 hw->fc = e1000_fc_rx_pause;
3611 DEBUGOUT
3612 ("Flow Control = RX PAUSE frames only.\r\n");
3613 }
3614 /* Per the IEEE spec, at this point flow control should be
3615 * disabled. However, we want to consider that we could
3616 * be connected to a legacy switch that doesn't advertise
3617 * desired flow control, but can be forced on the link
3618 * partner. So if we advertised no flow control, that is
3619 * what we will resolve to. If we advertised some kind of
3620 * receive capability (Rx Pause Only or Full Flow Control)
3621 * and the link partner advertised none, we will configure
3622 * ourselves to enable Rx Flow Control only. We can do
3623 * this safely for two reasons: If the link partner really
3624 * didn't want flow control enabled, and we enable Rx, no
3625 * harm done since we won't be receiving any PAUSE frames
3626 * anyway. If the intent on the link partner was to have
3627 * flow control enabled, then by us enabling RX only, we
3628 * can at least receive pause frames and process them.
3629 * This is a good idea because in most cases, since we are
3630 * predominantly a server NIC, more times than not we will
3631 * be asked to delay transmission of packets than asking
3632 * our link partner to pause transmission of frames.
3633 */
3634 else if (hw->original_fc == e1000_fc_none ||
3635 hw->original_fc == e1000_fc_tx_pause) {
3636 hw->fc = e1000_fc_none;
3637 DEBUGOUT("Flow Control = NONE.\r\n");
3638 } else {
3639 hw->fc = e1000_fc_rx_pause;
3640 DEBUGOUT
3641 ("Flow Control = RX PAUSE frames only.\r\n");
3642 }
3643
1aeed8d7 3644 /* Now we need to do one last check... If we auto-
682011ff
WD		 3645 * negotiated to HALF DUPLEX, flow control should not be
3646 * enabled per IEEE 802.3 spec.
3647 */
3648 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3649
3650 if (duplex == HALF_DUPLEX)
3651 hw->fc = e1000_fc_none;
3652
3653 /* Now we call a subroutine to actually force the MAC
3654 * controller to use the correct flow control settings.
3655 */
3656 ret_val = e1000_force_mac_fc(hw);
3657 if (ret_val < 0) {
3658 DEBUGOUT
3659 ("Error forcing flow control settings\n");
3660 return ret_val;
3661 }
3662 } else {
3663 DEBUGOUT
3664 ("Copper PHY and Auto Neg has not completed.\r\n");
3665 }
3666 }
aa070789 3667 return E1000_SUCCESS;
682011ff
WD		 3668}
3669
3670/******************************************************************************
3671 * Checks to see if the link status of the hardware has changed.
3672 *
3673 * hw - Struct containing variables accessed by shared code
3674 *
3675 * Called by any function that needs to check the link status of the adapter.
3676 *****************************************************************************/
3677static int
5c5e707a 3678e1000_check_for_link(struct e1000_hw *hw)
682011ff 3679{
682011ff
WD		 3680 uint32_t rxcw;
3681 uint32_t ctrl;
3682 uint32_t status;
3683 uint32_t rctl;
3684 uint32_t signal;
3685 int32_t ret_val;
3686 uint16_t phy_data;
3687 uint16_t lp_capability;
3688
3689 DEBUGFUNC();
3690
8bde7f77
WD		 3691 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3692 * set when the optics detect a signal. On older adapters, it will be
682011ff
WD		 3693 * cleared when there is a signal
3694 */
3695 ctrl = E1000_READ_REG(hw, CTRL);
3696 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3697 signal = E1000_CTRL_SWDPIN1;
3698 else
3699 signal = 0;
3700
3701 status = E1000_READ_REG(hw, STATUS);
3702 rxcw = E1000_READ_REG(hw, RXCW);
3703 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3704
3705 /* If we have a copper PHY then we only want to go out to the PHY
3706 * registers to see if Auto-Neg has completed and/or if our link
1aeed8d7 3707 * status has changed. The get_link_status flag will be set if we
682011ff
WD		 3708 * receive a Link Status Change interrupt or we have Rx Sequence
3709 * Errors.
3710 */
3711 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3712 /* First we want to see if the MII Status Register reports
3713 * link. If so, then we want to get the current speed/duplex
3714 * of the PHY.
3715 * Read the register twice since the link bit is sticky.
3716 */
3717 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3718 DEBUGOUT("PHY Read Error\n");
3719 return -E1000_ERR_PHY;
3720 }
3721 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3722 DEBUGOUT("PHY Read Error\n");
3723 return -E1000_ERR_PHY;
3724 }
3725
3726 if (phy_data & MII_SR_LINK_STATUS) {
472d5460 3727 hw->get_link_status = false;
682011ff
WD		 3728 } else {
3729 /* No link detected */
3730 return -E1000_ERR_NOLINK;
3731 }
3732
3733 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3734 * have Si on board that is 82544 or newer, Auto
3735 * Speed Detection takes care of MAC speed/duplex
3736 * configuration. So we only need to configure Collision
3737 * Distance in the MAC. Otherwise, we need to force
3738 * speed/duplex on the MAC to the current PHY speed/duplex
3739 * settings.
3740 */
3741 if (hw->mac_type >= e1000_82544)
3742 e1000_config_collision_dist(hw);
3743 else {
3744 ret_val = e1000_config_mac_to_phy(hw);
3745 if (ret_val < 0) {
3746 DEBUGOUT
3747 ("Error configuring MAC to PHY settings\n");
3748 return ret_val;
3749 }
3750 }
3751
8bde7f77 3752 /* Configure Flow Control now that Auto-Neg has completed. First, we
682011ff
WD		 3753 * need to restore the desired flow control settings because we may
3754 * have had to re-autoneg with a different link partner.
3755 */
3756 ret_val = e1000_config_fc_after_link_up(hw);
3757 if (ret_val < 0) {
3758 DEBUGOUT("Error configuring flow control\n");
3759 return ret_val;
3760 }
3761
3762 /* At this point we know that we are on copper and we have
3763 * auto-negotiated link. These are conditions for checking the link
1aeed8d7 3764 * parter capability register. We use the link partner capability to
682011ff
WD		 3765 * determine if TBI Compatibility needs to be turned on or off. If
3766 * the link partner advertises any speed in addition to Gigabit, then
3767 * we assume that they are GMII-based, and TBI compatibility is not
3768 * needed. If no other speeds are advertised, we assume the link
3769 * partner is TBI-based, and we turn on TBI Compatibility.
3770 */
3771 if (hw->tbi_compatibility_en) {
3772 if (e1000_read_phy_reg
3773 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3774 DEBUGOUT("PHY Read Error\n");
3775 return -E1000_ERR_PHY;
3776 }
3777 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3778 NWAY_LPAR_10T_FD_CAPS |
3779 NWAY_LPAR_100TX_HD_CAPS |
3780 NWAY_LPAR_100TX_FD_CAPS |
3781 NWAY_LPAR_100T4_CAPS)) {
8bde7f77 3782 /* If our link partner advertises anything in addition to
682011ff
WD		 3783 * gigabit, we do not need to enable TBI compatibility.
3784 */
3785 if (hw->tbi_compatibility_on) {
3786 /* If we previously were in the mode, turn it off. */
3787 rctl = E1000_READ_REG(hw, RCTL);
3788 rctl &= ~E1000_RCTL_SBP;
3789 E1000_WRITE_REG(hw, RCTL, rctl);
472d5460 3790 hw->tbi_compatibility_on = false;
682011ff
WD		 3791 }
3792 } else {
3793 /* If TBI compatibility is was previously off, turn it on. For
3794 * compatibility with a TBI link partner, we will store bad
3795 * packets. Some frames have an additional byte on the end and
3796 * will look like CRC errors to to the hardware.
3797 */
3798 if (!hw->tbi_compatibility_on) {
472d5460 3799 hw->tbi_compatibility_on = true;
682011ff
WD		 3800 rctl = E1000_READ_REG(hw, RCTL);
3801 rctl |= E1000_RCTL_SBP;
3802 E1000_WRITE_REG(hw, RCTL, rctl);
3803 }
3804 }
3805 }
3806 }
3807 /* If we don't have link (auto-negotiation failed or link partner cannot
3808 * auto-negotiate), the cable is plugged in (we have signal), and our
3809 * link partner is not trying to auto-negotiate with us (we are receiving
3810 * idles or data), we need to force link up. We also need to give
3811 * auto-negotiation time to complete, in case the cable was just plugged
3812 * in. The autoneg_failed flag does this.
3813 */
3814 else if ((hw->media_type == e1000_media_type_fiber) &&
3815 (!(status & E1000_STATUS_LU)) &&
3816 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3817 (!(rxcw & E1000_RXCW_C))) {
3818 if (hw->autoneg_failed == 0) {
3819 hw->autoneg_failed = 1;
3820 return 0;
3821 }
3822 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3823
3824 /* Disable auto-negotiation in the TXCW register */
3825 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3826
3827 /* Force link-up and also force full-duplex. */
3828 ctrl = E1000_READ_REG(hw, CTRL);
3829 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3830 E1000_WRITE_REG(hw, CTRL, ctrl);
3831
3832 /* Configure Flow Control after forcing link up. */
3833 ret_val = e1000_config_fc_after_link_up(hw);
3834 if (ret_val < 0) {
3835 DEBUGOUT("Error configuring flow control\n");
3836 return ret_val;
3837 }
3838 }
3839 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3840 * auto-negotiation in the TXCW register and disable forced link in the
3841 * Device Control register in an attempt to auto-negotiate with our link
3842 * partner.
3843 */
3844 else if ((hw->media_type == e1000_media_type_fiber) &&
3845 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3846 DEBUGOUT
3847 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3848 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3849 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3850 }
3851 return 0;
3852}
3853
aa070789
RZ		 3854/******************************************************************************
3855* Configure the MAC-to-PHY interface for 10/100Mbps
3856*
3857* hw - Struct containing variables accessed by shared code
3858******************************************************************************/
3859static int32_t
3860e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3861{
3862 int32_t ret_val = E1000_SUCCESS;
3863 uint32_t tipg;
3864 uint16_t reg_data;
3865
3866 DEBUGFUNC();
3867
3868 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3869 ret_val = e1000_write_kmrn_reg(hw,
3870 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3871 if (ret_val)
3872 return ret_val;
3873
3874 /* Configure Transmit Inter-Packet Gap */
3875 tipg = E1000_READ_REG(hw, TIPG);
3876 tipg &= ~E1000_TIPG_IPGT_MASK;
3877 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3878 E1000_WRITE_REG(hw, TIPG, tipg);
3879
3880 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3881
3882 if (ret_val)
3883 return ret_val;
3884
3885 if (duplex == HALF_DUPLEX)
3886 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3887 else
3888 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3889
3890 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3891
3892 return ret_val;
3893}
3894
3895static int32_t
3896e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3897{
3898 int32_t ret_val = E1000_SUCCESS;
3899 uint16_t reg_data;
3900 uint32_t tipg;
3901
3902 DEBUGFUNC();
3903
3904 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3905 ret_val = e1000_write_kmrn_reg(hw,
3906 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3907 if (ret_val)
3908 return ret_val;
3909
3910 /* Configure Transmit Inter-Packet Gap */
3911 tipg = E1000_READ_REG(hw, TIPG);
3912 tipg &= ~E1000_TIPG_IPGT_MASK;
3913 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3914 E1000_WRITE_REG(hw, TIPG, tipg);
3915
3916 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3917
3918 if (ret_val)
3919 return ret_val;
3920
3921 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3922 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3923
3924 return ret_val;
3925}
3926
682011ff
WD		 3927/******************************************************************************
3928 * Detects the current speed and duplex settings of the hardware.
3929 *
3930 * hw - Struct containing variables accessed by shared code
3931 * speed - Speed of the connection
3932 * duplex - Duplex setting of the connection
3933 *****************************************************************************/
aa070789
RZ		 3934static int
3935e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3936 uint16_t *duplex)
682011ff
WD		 3937{
3938 uint32_t status;
aa070789
RZ		 3939 int32_t ret_val;
3940 uint16_t phy_data;
682011ff
WD		 3941
3942 DEBUGFUNC();
3943
3944 if (hw->mac_type >= e1000_82543) {
3945 status = E1000_READ_REG(hw, STATUS);
3946 if (status & E1000_STATUS_SPEED_1000) {
3947 *speed = SPEED_1000;
3948 DEBUGOUT("1000 Mbs, ");
3949 } else if (status & E1000_STATUS_SPEED_100) {
3950 *speed = SPEED_100;
3951 DEBUGOUT("100 Mbs, ");
3952 } else {
3953 *speed = SPEED_10;
3954 DEBUGOUT("10 Mbs, ");
3955 }
3956
3957 if (status & E1000_STATUS_FD) {
3958 *duplex = FULL_DUPLEX;
3959 DEBUGOUT("Full Duplex\r\n");
3960 } else {
3961 *duplex = HALF_DUPLEX;
3962 DEBUGOUT(" Half Duplex\r\n");
3963 }
3964 } else {
3965 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3966 *speed = SPEED_1000;
3967 *duplex = FULL_DUPLEX;
3968 }
aa070789
RZ		 3969
3970 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3971 * even if it is operating at half duplex. Here we set the duplex
3972 * settings to match the duplex in the link partner's capabilities.
3973 */
3974 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3975 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3976 if (ret_val)
3977 return ret_val;
3978
3979 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3980 *duplex = HALF_DUPLEX;
3981 else {
3982 ret_val = e1000_read_phy_reg(hw,
3983 PHY_LP_ABILITY, &phy_data);
3984 if (ret_val)
3985 return ret_val;
3986 if ((*speed == SPEED_100 &&
3987 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3988 || (*speed == SPEED_10
3989 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3990 *duplex = HALF_DUPLEX;
3991 }
3992 }
3993
3994 if ((hw->mac_type == e1000_80003es2lan) &&
3995 (hw->media_type == e1000_media_type_copper)) {
3996 if (*speed == SPEED_1000)
3997 ret_val = e1000_configure_kmrn_for_1000(hw);
3998 else
3999 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4000 if (ret_val)
4001 return ret_val;
4002 }
4003 return E1000_SUCCESS;
682011ff
WD		 4004}
4005
4006/******************************************************************************
4007* Blocks until autoneg completes or times out (~4.5 seconds)
4008*
4009* hw - Struct containing variables accessed by shared code
4010******************************************************************************/
4011static int
4012e1000_wait_autoneg(struct e1000_hw *hw)
4013{
4014 uint16_t i;
4015 uint16_t phy_data;
4016
4017 DEBUGFUNC();
4018 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4019
faa765d4 4020 /* We will wait for autoneg to complete or timeout to expire. */
682011ff
WD		 4021 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4022 /* Read the MII Status Register and wait for Auto-Neg
4023 * Complete bit to be set.
4024 */
4025 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4026 DEBUGOUT("PHY Read Error\n");
4027 return -E1000_ERR_PHY;
4028 }
4029 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4030 DEBUGOUT("PHY Read Error\n");
4031 return -E1000_ERR_PHY;
4032 }
4033 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4034 DEBUGOUT("Auto-Neg complete.\n");
4035 return 0;
4036 }
4037 mdelay(100);
4038 }
4039 DEBUGOUT("Auto-Neg timedout.\n");
4040 return -E1000_ERR_TIMEOUT;
4041}
4042
4043/******************************************************************************
4044* Raises the Management Data Clock
4045*
4046* hw - Struct containing variables accessed by shared code
4047* ctrl - Device control register's current value
4048******************************************************************************/
4049static void
4050e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4051{
4052 /* Raise the clock input to the Management Data Clock (by setting the MDC
4053 * bit), and then delay 2 microseconds.
4054 */
4055 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4056 E1000_WRITE_FLUSH(hw);
4057 udelay(2);
4058}
4059
4060/******************************************************************************
4061* Lowers the Management Data Clock
4062*
4063* hw - Struct containing variables accessed by shared code
4064* ctrl - Device control register's current value
4065******************************************************************************/
4066static void
4067e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4068{
4069 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4070 * bit), and then delay 2 microseconds.
4071 */
4072 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4073 E1000_WRITE_FLUSH(hw);
4074 udelay(2);
4075}
4076
4077/******************************************************************************
4078* Shifts data bits out to the PHY
4079*
4080* hw - Struct containing variables accessed by shared code
4081* data - Data to send out to the PHY
4082* count - Number of bits to shift out
4083*
4084* Bits are shifted out in MSB to LSB order.
4085******************************************************************************/
4086static void
4087e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4088{
4089 uint32_t ctrl;
4090 uint32_t mask;
4091
4092 /* We need to shift "count" number of bits out to the PHY. So, the value
8bde7f77 4093 * in the "data" parameter will be shifted out to the PHY one bit at a
682011ff
WD		 4094 * time. In order to do this, "data" must be broken down into bits.
4095 */
4096 mask = 0x01;
4097 mask <<= (count - 1);
4098
4099 ctrl = E1000_READ_REG(hw, CTRL);
4100
4101 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4102 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4103
4104 while (mask) {
4105 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4106 * then raising and lowering the Management Data Clock. A "0" is
4107 * shifted out to the PHY by setting the MDIO bit to "0" and then
4108 * raising and lowering the clock.
4109 */
4110 if (data & mask)
4111 ctrl |= E1000_CTRL_MDIO;
4112 else
4113 ctrl &= ~E1000_CTRL_MDIO;
4114
4115 E1000_WRITE_REG(hw, CTRL, ctrl);
4116 E1000_WRITE_FLUSH(hw);
4117
4118 udelay(2);
4119
4120 e1000_raise_mdi_clk(hw, &ctrl);
4121 e1000_lower_mdi_clk(hw, &ctrl);
4122
4123 mask = mask >> 1;
4124 }
4125}
4126
4127/******************************************************************************
4128* Shifts data bits in from the PHY
4129*
4130* hw - Struct containing variables accessed by shared code
4131*
8bde7f77 4132* Bits are shifted in in MSB to LSB order.
682011ff
WD		 4133******************************************************************************/
4134static uint16_t
4135e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4136{
4137 uint32_t ctrl;
4138 uint16_t data = 0;
4139 uint8_t i;
4140
4141 /* In order to read a register from the PHY, we need to shift in a total
4142 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4143 * to avoid contention on the MDIO pin when a read operation is performed.
4144 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4145 * by raising the input to the Management Data Clock (setting the MDC bit),
4146 * and then reading the value of the MDIO bit.
4147 */
4148 ctrl = E1000_READ_REG(hw, CTRL);
4149
4150 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4151 ctrl &= ~E1000_CTRL_MDIO_DIR;
4152 ctrl &= ~E1000_CTRL_MDIO;
4153
4154 E1000_WRITE_REG(hw, CTRL, ctrl);
4155 E1000_WRITE_FLUSH(hw);
4156
4157 /* Raise and Lower the clock before reading in the data. This accounts for
4158 * the turnaround bits. The first clock occurred when we clocked out the
4159 * last bit of the Register Address.
4160 */
4161 e1000_raise_mdi_clk(hw, &ctrl);
4162 e1000_lower_mdi_clk(hw, &ctrl);
4163
4164 for (data = 0, i = 0; i < 16; i++) {
4165 data = data << 1;
4166 e1000_raise_mdi_clk(hw, &ctrl);
4167 ctrl = E1000_READ_REG(hw, CTRL);
4168 /* Check to see if we shifted in a "1". */
4169 if (ctrl & E1000_CTRL_MDIO)
4170 data |= 1;
4171 e1000_lower_mdi_clk(hw, &ctrl);
4172 }
4173
4174 e1000_raise_mdi_clk(hw, &ctrl);
4175 e1000_lower_mdi_clk(hw, &ctrl);
4176
4177 return data;
4178}
4179
4180/*****************************************************************************
4181* Reads the value from a PHY register
4182*
4183* hw - Struct containing variables accessed by shared code
4184* reg_addr - address of the PHY register to read
4185******************************************************************************/
4186static int
4187e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4188{
4189 uint32_t i;
4190 uint32_t mdic = 0;
4191 const uint32_t phy_addr = 1;
4192
4193 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4194 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4195 return -E1000_ERR_PARAM;
4196 }
4197
4198 if (hw->mac_type > e1000_82543) {
4199 /* Set up Op-code, Phy Address, and register address in the MDI
4200 * Control register. The MAC will take care of interfacing with the
4201 * PHY to retrieve the desired data.
4202 */
4203 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4204 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4205 (E1000_MDIC_OP_READ));
4206
4207 E1000_WRITE_REG(hw, MDIC, mdic);
4208
4209 /* Poll the ready bit to see if the MDI read completed */
4210 for (i = 0; i < 64; i++) {
4211 udelay(10);
4212 mdic = E1000_READ_REG(hw, MDIC);
4213 if (mdic & E1000_MDIC_READY)
4214 break;
4215 }
4216 if (!(mdic & E1000_MDIC_READY)) {
4217 DEBUGOUT("MDI Read did not complete\n");
4218 return -E1000_ERR_PHY;
4219 }
4220 if (mdic & E1000_MDIC_ERROR) {
4221 DEBUGOUT("MDI Error\n");
4222 return -E1000_ERR_PHY;
4223 }
4224 *phy_data = (uint16_t) mdic;
4225 } else {
4226 /* We must first send a preamble through the MDIO pin to signal the
4227 * beginning of an MII instruction. This is done by sending 32
4228 * consecutive "1" bits.
4229 */
4230 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4231
4232 /* Now combine the next few fields that are required for a read
4233 * operation. We use this method instead of calling the
4234 * e1000_shift_out_mdi_bits routine five different times. The format of
4235 * a MII read instruction consists of a shift out of 14 bits and is
4236 * defined as follows:
4237 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4238 * followed by a shift in of 18 bits. This first two bits shifted in
4239 * are TurnAround bits used to avoid contention on the MDIO pin when a
4240 * READ operation is performed. These two bits are thrown away
4241 * followed by a shift in of 16 bits which contains the desired data.
4242 */
4243 mdic = ((reg_addr) | (phy_addr << 5) |
4244 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4245
4246 e1000_shift_out_mdi_bits(hw, mdic, 14);
4247
4248 /* Now that we've shifted out the read command to the MII, we need to
4249 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4250 * register address.
4251 */
4252 *phy_data = e1000_shift_in_mdi_bits(hw);
4253 }
4254 return 0;
4255}
4256
4257/******************************************************************************
4258* Writes a value to a PHY register
4259*
4260* hw - Struct containing variables accessed by shared code
4261* reg_addr - address of the PHY register to write
4262* data - data to write to the PHY
4263******************************************************************************/
4264static int
4265e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4266{
4267 uint32_t i;
4268 uint32_t mdic = 0;
4269 const uint32_t phy_addr = 1;
4270
4271 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4272 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4273 return -E1000_ERR_PARAM;
4274 }
4275
4276 if (hw->mac_type > e1000_82543) {
4277 /* Set up Op-code, Phy Address, register address, and data intended
4278 * for the PHY register in the MDI Control register. The MAC will take
4279 * care of interfacing with the PHY to send the desired data.
4280 */
4281 mdic = (((uint32_t) phy_data) |
4282 (reg_addr << E1000_MDIC_REG_SHIFT) |
4283 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4284 (E1000_MDIC_OP_WRITE));
4285
4286 E1000_WRITE_REG(hw, MDIC, mdic);
4287
4288 /* Poll the ready bit to see if the MDI read completed */
4289 for (i = 0; i < 64; i++) {
4290 udelay(10);
4291 mdic = E1000_READ_REG(hw, MDIC);
4292 if (mdic & E1000_MDIC_READY)
4293 break;
4294 }
4295 if (!(mdic & E1000_MDIC_READY)) {
4296 DEBUGOUT("MDI Write did not complete\n");
4297 return -E1000_ERR_PHY;
4298 }
4299 } else {
4300 /* We'll need to use the SW defined pins to shift the write command
4301 * out to the PHY. We first send a preamble to the PHY to signal the
8bde7f77 4302 * beginning of the MII instruction. This is done by sending 32
682011ff
WD		 4303 * consecutive "1" bits.
4304 */
4305 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4306
8bde7f77 4307 /* Now combine the remaining required fields that will indicate a
682011ff
WD		 4308 * write operation. We use this method instead of calling the
4309 * e1000_shift_out_mdi_bits routine for each field in the command. The
4310 * format of a MII write instruction is as follows:
4311 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4312 */
4313 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4314 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4315 mdic <<= 16;
4316 mdic |= (uint32_t) phy_data;
4317
4318 e1000_shift_out_mdi_bits(hw, mdic, 32);
4319 }
4320 return 0;
4321}
4322
aa070789
RZ		 4323/******************************************************************************
4324 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4325 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4326 * the caller to figure out how to deal with it.
4327 *
4328 * hw - Struct containing variables accessed by shared code
4329 *
4330 * returns: - E1000_BLK_PHY_RESET
4331 * E1000_SUCCESS
4332 *
4333 *****************************************************************************/
4334int32_t
4335e1000_check_phy_reset_block(struct e1000_hw *hw)
4336{
4337 uint32_t manc = 0;
4338 uint32_t fwsm = 0;
4339
4340 if (hw->mac_type == e1000_ich8lan) {
4341 fwsm = E1000_READ_REG(hw, FWSM);
4342 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4343 : E1000_BLK_PHY_RESET;
4344 }
4345
4346 if (hw->mac_type > e1000_82547_rev_2)
4347 manc = E1000_READ_REG(hw, MANC);
4348 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4349 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4350}
4351
4352/***************************************************************************
4353 * Checks if the PHY configuration is done
4354 *
4355 * hw: Struct containing variables accessed by shared code
4356 *
4357 * returns: - E1000_ERR_RESET if fail to reset MAC
4358 * E1000_SUCCESS at any other case.
4359 *
4360 ***************************************************************************/
4361static int32_t
4362e1000_get_phy_cfg_done(struct e1000_hw *hw)
4363{
4364 int32_t timeout = PHY_CFG_TIMEOUT;
4365 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4366
4367 DEBUGFUNC();
4368
4369 switch (hw->mac_type) {
4370 default:
4371 mdelay(10);
4372 break;
987b43a1 4373
aa070789
RZ		 4374 case e1000_80003es2lan:
4375 /* Separate *_CFG_DONE_* bit for each port */
987b43a1 4376 if (e1000_is_second_port(hw))
aa070789 4377 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
987b43a1
KM		 4378 /* Fall Through */
4379
aa070789
RZ		 4380 case e1000_82571:
4381 case e1000_82572:
95186063 4382 case e1000_igb:
aa070789 4383 while (timeout) {
95186063
MV		 4384 if (hw->mac_type == e1000_igb) {
4385 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4386 break;
4387 } else {
4388 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4389 break;
4390 }
4391 mdelay(1);
aa070789
RZ		 4392 timeout--;
4393 }
4394 if (!timeout) {
4395 DEBUGOUT("MNG configuration cycle has not "
4396 "completed.\n");
4397 return -E1000_ERR_RESET;
4398 }
4399 break;
4400 }
4401
4402 return E1000_SUCCESS;
4403}
4404
682011ff
WD		 4405/******************************************************************************
4406* Returns the PHY to the power-on reset state
4407*
4408* hw - Struct containing variables accessed by shared code
4409******************************************************************************/
aa070789 4410int32_t
682011ff
WD		 4411e1000_phy_hw_reset(struct e1000_hw *hw)
4412{
987b43a1 4413 uint16_t swfw = E1000_SWFW_PHY0_SM;
aa070789
RZ		 4414 uint32_t ctrl, ctrl_ext;
4415 uint32_t led_ctrl;
4416 int32_t ret_val;
682011ff
WD		 4417
4418 DEBUGFUNC();
4419
aa070789
RZ		 4420 /* In the case of the phy reset being blocked, it's not an error, we
4421 * simply return success without performing the reset. */
4422 ret_val = e1000_check_phy_reset_block(hw);
4423 if (ret_val)
4424 return E1000_SUCCESS;
4425
682011ff
WD		 4426 DEBUGOUT("Resetting Phy...\n");
4427
4428 if (hw->mac_type > e1000_82543) {
987b43a1 4429 if (e1000_is_second_port(hw))
aa070789 4430 swfw = E1000_SWFW_PHY1_SM;
987b43a1 4431
aa070789
RZ		 4432 if (e1000_swfw_sync_acquire(hw, swfw)) {
4433 DEBUGOUT("Unable to acquire swfw sync\n");
4434 return -E1000_ERR_SWFW_SYNC;
4435 }
987b43a1 4436
682011ff
WD		 4437 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4438 * bit. Then, take it out of reset.
4439 */
4440 ctrl = E1000_READ_REG(hw, CTRL);
4441 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4442 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4443
4444 if (hw->mac_type < e1000_82571)
4445 udelay(10);
4446 else
4447 udelay(100);
4448
682011ff
WD		 4449 E1000_WRITE_REG(hw, CTRL, ctrl);
4450 E1000_WRITE_FLUSH(hw);
aa070789
RZ		 4451
4452 if (hw->mac_type >= e1000_82571)
4453 mdelay(10);
3c63dd53 4454
682011ff
WD		 4455 } else {
4456 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4457 * bit to put the PHY into reset. Then, take it out of reset.
4458 */
4459 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4460 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4461 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4462 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4463 E1000_WRITE_FLUSH(hw);
4464 mdelay(10);
4465 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4466 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4467 E1000_WRITE_FLUSH(hw);
4468 }
4469 udelay(150);
aa070789
RZ		 4470
4471 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4472 /* Configure activity LED after PHY reset */
4473 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4474 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4475 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4476 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4477 }
4478
7e2d991d
TH		 4479 e1000_swfw_sync_release(hw, swfw);
4480
aa070789
RZ		 4481 /* Wait for FW to finish PHY configuration. */
4482 ret_val = e1000_get_phy_cfg_done(hw);
4483 if (ret_val != E1000_SUCCESS)
4484 return ret_val;
4485
4486 return ret_val;
4487}
4488
4489/******************************************************************************
4490 * IGP phy init script - initializes the GbE PHY
4491 *
4492 * hw - Struct containing variables accessed by shared code
4493 *****************************************************************************/
4494static void
4495e1000_phy_init_script(struct e1000_hw *hw)
4496{
4497 uint32_t ret_val;
4498 uint16_t phy_saved_data;
4499 DEBUGFUNC();
4500
4501 if (hw->phy_init_script) {
4502 mdelay(20);
4503
4504 /* Save off the current value of register 0x2F5B to be
4505 * restored at the end of this routine. */
4506 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4507
4508 /* Disabled the PHY transmitter */
4509 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4510
4511 mdelay(20);
4512
4513 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4514
4515 mdelay(5);
4516
4517 switch (hw->mac_type) {
4518 case e1000_82541:
4519 case e1000_82547:
4520 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4521
4522 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4523
4524 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4525
4526 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4527
4528 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4529
4530 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4531
4532 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4533
4534 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4535
4536 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4537 break;
4538
4539 case e1000_82541_rev_2:
4540 case e1000_82547_rev_2:
4541 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4542 break;
4543 default:
4544 break;
4545 }
4546
4547 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4548
4549 mdelay(20);
4550
4551 /* Now enable the transmitter */
56b13b1e
ZRR		 4552 if (!ret_val)
4553 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
aa070789
RZ		 4554
4555 if (hw->mac_type == e1000_82547) {
4556 uint16_t fused, fine, coarse;
4557
4558 /* Move to analog registers page */
4559 e1000_read_phy_reg(hw,
4560 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4561
4562 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4563 e1000_read_phy_reg(hw,
4564 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4565
4566 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4567 coarse = fused
4568 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4569
4570 if (coarse >
4571 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4572 coarse -=
4573 IGP01E1000_ANALOG_FUSE_COARSE_10;
4574 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4575 } else if (coarse
4576 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4577 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4578
4579 fused = (fused
4580 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4581 (fine
4582 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4583 (coarse
4584 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4585
4586 e1000_write_phy_reg(hw,
4587 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4588 e1000_write_phy_reg(hw,
4589 IGP01E1000_ANALOG_FUSE_BYPASS,
4590 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4591 }
4592 }
4593 }
682011ff
WD		 4594}
4595
4596/******************************************************************************
4597* Resets the PHY
4598*
4599* hw - Struct containing variables accessed by shared code
4600*
aa070789 4601* Sets bit 15 of the MII Control register
682011ff 4602******************************************************************************/
aa070789 4603int32_t
682011ff
WD		 4604e1000_phy_reset(struct e1000_hw *hw)
4605{
aa070789 4606 int32_t ret_val;
682011ff
WD		 4607 uint16_t phy_data;
4608
4609 DEBUGFUNC();
4610
aa070789
RZ		 4611 /* In the case of the phy reset being blocked, it's not an error, we
4612 * simply return success without performing the reset. */
4613 ret_val = e1000_check_phy_reset_block(hw);
4614 if (ret_val)
4615 return E1000_SUCCESS;
4616
4617 switch (hw->phy_type) {
4618 case e1000_phy_igp:
4619 case e1000_phy_igp_2:
4620 case e1000_phy_igp_3:
4621 case e1000_phy_ife:
95186063 4622 case e1000_phy_igb:
aa070789
RZ		 4623 ret_val = e1000_phy_hw_reset(hw);
4624 if (ret_val)
4625 return ret_val;
4626 break;
4627 default:
4628 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4629 if (ret_val)
4630 return ret_val;
4631
4632 phy_data |= MII_CR_RESET;
4633 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4634 if (ret_val)
4635 return ret_val;
4636
4637 udelay(1);
4638 break;
682011ff 4639 }
aa070789
RZ		 4640
4641 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4642 e1000_phy_init_script(hw);
4643
4644 return E1000_SUCCESS;
682011ff
WD		 4645}
4646
1aeed8d7 4647static int e1000_set_phy_type (struct e1000_hw *hw)
ac3315c2 4648{
1aeed8d7
WD		 4649 DEBUGFUNC ();
4650
4651 if (hw->mac_type == e1000_undefined)
4652 return -E1000_ERR_PHY_TYPE;
4653
4654 switch (hw->phy_id) {
4655 case M88E1000_E_PHY_ID:
4656 case M88E1000_I_PHY_ID:
4657 case M88E1011_I_PHY_ID:
aa070789 4658 case M88E1111_I_PHY_ID:
1aeed8d7
WD		 4659 hw->phy_type = e1000_phy_m88;
4660 break;
4661 case IGP01E1000_I_PHY_ID:
4662 if (hw->mac_type == e1000_82541 ||
aa070789
RZ		 4663 hw->mac_type == e1000_82541_rev_2 ||
4664 hw->mac_type == e1000_82547 ||
4665 hw->mac_type == e1000_82547_rev_2) {
1aeed8d7 4666 hw->phy_type = e1000_phy_igp;
aa070789
RZ		 4667 break;
4668 }
4669 case IGP03E1000_E_PHY_ID:
4670 hw->phy_type = e1000_phy_igp_3;
4671 break;
4672 case IFE_E_PHY_ID:
4673 case IFE_PLUS_E_PHY_ID:
4674 case IFE_C_E_PHY_ID:
4675 hw->phy_type = e1000_phy_ife;
4676 break;
4677 case GG82563_E_PHY_ID:
4678 if (hw->mac_type == e1000_80003es2lan) {
4679 hw->phy_type = e1000_phy_gg82563;
1aeed8d7
WD		 4680 break;
4681 }
2c2668f9
RZ		 4682 case BME1000_E_PHY_ID:
4683 hw->phy_type = e1000_phy_bm;
4684 break;
95186063
MV		 4685 case I210_I_PHY_ID:
4686 hw->phy_type = e1000_phy_igb;
4687 break;
1aeed8d7
WD		 4688 /* Fall Through */
4689 default:
4690 /* Should never have loaded on this device */
4691 hw->phy_type = e1000_phy_undefined;
4692 return -E1000_ERR_PHY_TYPE;
4693 }
4694
4695 return E1000_SUCCESS;
ac3315c2
AS		 4696}
4697
682011ff
WD		 4698/******************************************************************************
4699* Probes the expected PHY address for known PHY IDs
4700*
4701* hw - Struct containing variables accessed by shared code
4702******************************************************************************/
aa070789 4703static int32_t
682011ff
WD		 4704e1000_detect_gig_phy(struct e1000_hw *hw)
4705{
aa070789 4706 int32_t phy_init_status, ret_val;
682011ff 4707 uint16_t phy_id_high, phy_id_low;
472d5460 4708 bool match = false;
682011ff
WD		 4709
4710 DEBUGFUNC();
4711
aa070789
RZ		 4712 /* The 82571 firmware may still be configuring the PHY. In this
4713 * case, we cannot access the PHY until the configuration is done. So
4714 * we explicitly set the PHY values. */
4715 if (hw->mac_type == e1000_82571 ||
4716 hw->mac_type == e1000_82572) {
4717 hw->phy_id = IGP01E1000_I_PHY_ID;
4718 hw->phy_type = e1000_phy_igp_2;
4719 return E1000_SUCCESS;
682011ff 4720 }
aa070789
RZ		 4721
4722 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4723 * work- around that forces PHY page 0 to be set or the reads fail.
4724 * The rest of the code in this routine uses e1000_read_phy_reg to
4725 * read the PHY ID. So for ESB-2 we need to have this set so our
4726 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4727 * the routines below will figure this out as well. */
4728 if (hw->mac_type == e1000_80003es2lan)
4729 hw->phy_type = e1000_phy_gg82563;
4730
4731 /* Read the PHY ID Registers to identify which PHY is onboard. */
4732 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4733 if (ret_val)
4734 return ret_val;
4735
682011ff 4736 hw->phy_id = (uint32_t) (phy_id_high << 16);
aa070789
RZ		 4737 udelay(20);
4738 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4739 if (ret_val)
4740 return ret_val;
4741
682011ff 4742 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
aa070789 4743 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
682011ff
WD		 4744
4745 switch (hw->mac_type) {
4746 case e1000_82543:
4747 if (hw->phy_id == M88E1000_E_PHY_ID)
472d5460 4748 match = true;
682011ff
WD		 4749 break;
4750 case e1000_82544:
4751 if (hw->phy_id == M88E1000_I_PHY_ID)
472d5460 4752 match = true;
682011ff
WD		 4753 break;
4754 case e1000_82540:
4755 case e1000_82545:
aa070789 4756 case e1000_82545_rev_3:
682011ff 4757 case e1000_82546:
aa070789 4758 case e1000_82546_rev_3:
682011ff 4759 if (hw->phy_id == M88E1011_I_PHY_ID)
472d5460 4760 match = true;
682011ff 4761 break;
aa070789 4762 case e1000_82541:
ac3315c2 4763 case e1000_82541_rev_2:
aa070789
RZ		 4764 case e1000_82547:
4765 case e1000_82547_rev_2:
ac3315c2 4766 if(hw->phy_id == IGP01E1000_I_PHY_ID)
472d5460 4767 match = true;
ac3315c2
AS		 4768
4769 break;
aa070789
RZ		 4770 case e1000_82573:
4771 if (hw->phy_id == M88E1111_I_PHY_ID)
472d5460 4772 match = true;
aa070789 4773 break;
2c2668f9
RZ		 4774 case e1000_82574:
4775 if (hw->phy_id == BME1000_E_PHY_ID)
472d5460 4776 match = true;
2c2668f9 4777 break;
aa070789
RZ		 4778 case e1000_80003es2lan:
4779 if (hw->phy_id == GG82563_E_PHY_ID)
472d5460 4780 match = true;
aa070789
RZ		 4781 break;
4782 case e1000_ich8lan:
4783 if (hw->phy_id == IGP03E1000_E_PHY_ID)
472d5460 4784 match = true;
aa070789 4785 if (hw->phy_id == IFE_E_PHY_ID)
472d5460 4786 match = true;
aa070789 4787 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
472d5460 4788 match = true;
aa070789 4789 if (hw->phy_id == IFE_C_E_PHY_ID)
472d5460 4790 match = true;
aa070789 4791 break;
95186063
MV		 4792 case e1000_igb:
4793 if (hw->phy_id == I210_I_PHY_ID)
4794 match = true;
4795 break;
682011ff
WD		 4796 default:
4797 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4798 return -E1000_ERR_CONFIG;
4799 }
ac3315c2
AS		 4800
4801 phy_init_status = e1000_set_phy_type(hw);
4802
4803 if ((match) && (phy_init_status == E1000_SUCCESS)) {
682011ff
WD		 4804 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4805 return 0;
4806 }
4807 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4808 return -E1000_ERR_PHY;
4809}
4810
aa070789
RZ		 4811/*****************************************************************************
4812 * Set media type and TBI compatibility.
4813 *
4814 * hw - Struct containing variables accessed by shared code
4815 * **************************************************************************/
4816void
4817e1000_set_media_type(struct e1000_hw *hw)
4818{
4819 uint32_t status;
4820
4821 DEBUGFUNC();
4822
4823 if (hw->mac_type != e1000_82543) {
4824 /* tbi_compatibility is only valid on 82543 */
472d5460 4825 hw->tbi_compatibility_en = false;
aa070789
RZ		 4826 }
4827
4828 switch (hw->device_id) {
4829 case E1000_DEV_ID_82545GM_SERDES:
4830 case E1000_DEV_ID_82546GB_SERDES:
4831 case E1000_DEV_ID_82571EB_SERDES:
4832 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4833 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4834 case E1000_DEV_ID_82572EI_SERDES:
4835 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4836 hw->media_type = e1000_media_type_internal_serdes;
4837 break;
4838 default:
4839 switch (hw->mac_type) {
4840 case e1000_82542_rev2_0:
4841 case e1000_82542_rev2_1:
4842 hw->media_type = e1000_media_type_fiber;
4843 break;
4844 case e1000_ich8lan:
4845 case e1000_82573:
2c2668f9 4846 case e1000_82574:
95186063 4847 case e1000_igb:
aa070789
RZ		 4848 /* The STATUS_TBIMODE bit is reserved or reused
4849 * for the this device.
4850 */
4851 hw->media_type = e1000_media_type_copper;
4852 break;
4853 default:
4854 status = E1000_READ_REG(hw, STATUS);
4855 if (status & E1000_STATUS_TBIMODE) {
4856 hw->media_type = e1000_media_type_fiber;
4857 /* tbi_compatibility not valid on fiber */
472d5460 4858 hw->tbi_compatibility_en = false;
aa070789
RZ		 4859 } else {
4860 hw->media_type = e1000_media_type_copper;
4861 }
4862 break;
4863 }
4864 }
4865}
4866
682011ff
WD		 4867/**
4868 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4869 *
4870 * e1000_sw_init initializes the Adapter private data structure.
4871 * Fields are initialized based on PCI device information and
4872 * OS network device settings (MTU size).
4873 **/
4874
4875static int
5c5e707a 4876e1000_sw_init(struct e1000_hw *hw)
682011ff 4877{
682011ff
WD		 4878 int result;
4879
4880 /* PCI config space info */
4881 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4882 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4883 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4884 &hw->subsystem_vendor_id);
4885 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4886
4887 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4888 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4889
4890 /* identify the MAC */
4891 result = e1000_set_mac_type(hw);
4892 if (result) {
5c5e707a 4893 E1000_ERR(hw, "Unknown MAC Type\n");
682011ff
WD		 4894 return result;
4895 }
4896
aa070789
RZ		 4897 switch (hw->mac_type) {
4898 default:
4899 break;
4900 case e1000_82541:
4901 case e1000_82547:
4902 case e1000_82541_rev_2:
4903 case e1000_82547_rev_2:
4904 hw->phy_init_script = 1;
4905 break;
4906 }
4907
682011ff
WD		 4908 /* flow control settings */
4909 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4910 hw->fc_low_water = E1000_FC_LOW_THRESH;
4911 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4912 hw->fc_send_xon = 1;
4913
4914 /* Media type - copper or fiber */
95186063 4915 hw->tbi_compatibility_en = true;
aa070789 4916 e1000_set_media_type(hw);
682011ff
WD		 4917
4918 if (hw->mac_type >= e1000_82543) {
4919 uint32_t status = E1000_READ_REG(hw, STATUS);
4920
4921 if (status & E1000_STATUS_TBIMODE) {
4922 DEBUGOUT("fiber interface\n");
4923 hw->media_type = e1000_media_type_fiber;
4924 } else {
4925 DEBUGOUT("copper interface\n");
4926 hw->media_type = e1000_media_type_copper;
4927 }
4928 } else {
4929 hw->media_type = e1000_media_type_fiber;
4930 }
4931
472d5460 4932 hw->wait_autoneg_complete = true;
682011ff
WD		 4933 if (hw->mac_type < e1000_82543)
4934 hw->report_tx_early = 0;
4935 else
4936 hw->report_tx_early = 1;
4937
682011ff
WD		 4938 return E1000_SUCCESS;
4939}
4940
4941void
4942fill_rx(struct e1000_hw *hw)
4943{
4944 struct e1000_rx_desc *rd;
06e07f65 4945 unsigned long flush_start, flush_end;
682011ff
WD		 4946
4947 rx_last = rx_tail;
4948 rd = rx_base + rx_tail;
4949 rx_tail = (rx_tail + 1) % 8;
4950 memset(rd, 0, 16);
06e07f65 4951 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
873e8e01
MV		 4952
4953 /*
4954 * Make sure there are no stale data in WB over this area, which
4955 * might get written into the memory while the e1000 also writes
4956 * into the same memory area.
4957 */
06e07f65
ML		 4958 invalidate_dcache_range((unsigned long)packet,
4959 (unsigned long)packet + 4096);
873e8e01 4960 /* Dump the DMA descriptor into RAM. */
06e07f65 4961 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 4962 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4963 flush_dcache_range(flush_start, flush_end);
4964
682011ff
WD		 4965 E1000_WRITE_REG(hw, RDT, rx_tail);
4966}
4967
4968/**
4969 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4970 * @adapter: board private structure
4971 *
4972 * Configure the Tx unit of the MAC after a reset.
4973 **/
4974
4975static void
4976e1000_configure_tx(struct e1000_hw *hw)
4977{
682011ff 4978 unsigned long tctl;
aa070789
RZ		 4979 unsigned long tipg, tarc;
4980 uint32_t ipgr1, ipgr2;
682011ff 4981
1d8a078b
BM		 4982 E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
4983 E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
682011ff
WD		 4984
4985 E1000_WRITE_REG(hw, TDLEN, 128);
4986
4987 /* Setup the HW Tx Head and Tail descriptor pointers */
4988 E1000_WRITE_REG(hw, TDH, 0);
4989 E1000_WRITE_REG(hw, TDT, 0);
4990 tx_tail = 0;
4991
aa070789
RZ		 4992 /* Set the default values for the Tx Inter Packet Gap timer */
4993 if (hw->mac_type <= e1000_82547_rev_2 &&
4994 (hw->media_type == e1000_media_type_fiber ||
4995 hw->media_type == e1000_media_type_internal_serdes))
4996 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4997 else
4998 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4999
682011ff
WD		 5000 /* Set the default values for the Tx Inter Packet Gap timer */
5001 switch (hw->mac_type) {
5002 case e1000_82542_rev2_0:
5003 case e1000_82542_rev2_1:
5004 tipg = DEFAULT_82542_TIPG_IPGT;
aa070789
RZ		 5005 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5006 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5007 break;
5008 case e1000_80003es2lan:
5009 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5010 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
682011ff
WD		 5011 break;
5012 default:
aa070789
RZ		 5013 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5014 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5015 break;
682011ff 5016 }
aa070789
RZ		 5017 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5018 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
682011ff 5019 E1000_WRITE_REG(hw, TIPG, tipg);
682011ff
WD		 5020 /* Program the Transmit Control Register */
5021 tctl = E1000_READ_REG(hw, TCTL);
5022 tctl &= ~E1000_TCTL_CT;
5023 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5024 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
aa070789
RZ		 5025
5026 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5027 tarc = E1000_READ_REG(hw, TARC0);
5028 /* set the speed mode bit, we'll clear it if we're not at
5029 * gigabit link later */
5030 /* git bit can be set to 1*/
5031 } else if (hw->mac_type == e1000_80003es2lan) {
5032 tarc = E1000_READ_REG(hw, TARC0);
5033 tarc |= 1;
5034 E1000_WRITE_REG(hw, TARC0, tarc);
5035 tarc = E1000_READ_REG(hw, TARC1);
5036 tarc |= 1;
5037 E1000_WRITE_REG(hw, TARC1, tarc);
5038 }
5039
682011ff
WD		 5040
5041 e1000_config_collision_dist(hw);
aa070789
RZ		 5042 /* Setup Transmit Descriptor Settings for eop descriptor */
5043 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
682011ff 5044
aa070789
RZ		 5045 /* Need to set up RS bit */
5046 if (hw->mac_type < e1000_82543)
5047 hw->txd_cmd |= E1000_TXD_CMD_RPS;
682011ff 5048 else
aa070789 5049 hw->txd_cmd |= E1000_TXD_CMD_RS;
95186063
MV		 5050
5051
5052 if (hw->mac_type == e1000_igb) {
5053 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5054
5055 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5056 reg_txdctl |= 1 << 25;
5057 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5058 mdelay(20);
5059 }
5060
5061
5062
aa070789 5063 E1000_WRITE_REG(hw, TCTL, tctl);
95186063
MV		 5064
5065
682011ff
WD		 5066}
5067
5068/**
5069 * e1000_setup_rctl - configure the receive control register
5070 * @adapter: Board private structure
5071 **/
5072static void
5073e1000_setup_rctl(struct e1000_hw *hw)
5074{
5075 uint32_t rctl;
5076
5077 rctl = E1000_READ_REG(hw, RCTL);
5078
5079 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5080
aa070789
RZ		 5081 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5082 | E1000_RCTL_RDMTS_HALF; /* |
5083 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
682011ff
WD		 5084
5085 if (hw->tbi_compatibility_on == 1)
5086 rctl |= E1000_RCTL_SBP;
5087 else
5088 rctl &= ~E1000_RCTL_SBP;
5089
5090 rctl &= ~(E1000_RCTL_SZ_4096);
682011ff
WD		 5091 rctl |= E1000_RCTL_SZ_2048;
5092 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
682011ff
WD		 5093 E1000_WRITE_REG(hw, RCTL, rctl);
5094}
5095
5096/**
5097 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5098 * @adapter: board private structure
5099 *
5100 * Configure the Rx unit of the MAC after a reset.
5101 **/
5102static void
5103e1000_configure_rx(struct e1000_hw *hw)
5104{
aa070789 5105 unsigned long rctl, ctrl_ext;
682011ff 5106 rx_tail = 0;
1d8a078b 5107
682011ff
WD		 5108 /* make sure receives are disabled while setting up the descriptors */
5109 rctl = E1000_READ_REG(hw, RCTL);
5110 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
682011ff 5111 if (hw->mac_type >= e1000_82540) {
682011ff
WD		 5112 /* Set the interrupt throttling rate. Value is calculated
5113 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
1aeed8d7
WD		 5114#define MAX_INTS_PER_SEC 8000
5115#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
682011ff
WD		 5116 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5117 }
5118
aa070789
RZ		 5119 if (hw->mac_type >= e1000_82571) {
5120 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5121 /* Reset delay timers after every interrupt */
5122 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5123 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5124 E1000_WRITE_FLUSH(hw);
5125 }
682011ff 5126 /* Setup the Base and Length of the Rx Descriptor Ring */
1d8a078b
BM		 5127 E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5128 E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
682011ff
WD		 5129
5130 E1000_WRITE_REG(hw, RDLEN, 128);
5131
5132 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5133 E1000_WRITE_REG(hw, RDH, 0);
5134 E1000_WRITE_REG(hw, RDT, 0);
682011ff
WD		 5135 /* Enable Receives */
5136
95186063
MV		 5137 if (hw->mac_type == e1000_igb) {
5138
5139 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5140 reg_rxdctl |= 1 << 25;
5141 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5142 mdelay(20);
5143 }
5144
682011ff 5145 E1000_WRITE_REG(hw, RCTL, rctl);
95186063 5146
682011ff
WD		 5147 fill_rx(hw);
5148}
5149
5150/**************************************************************************
5151POLL - Wait for a frame
5152***************************************************************************/
5153static int
5c5e707a 5154_e1000_poll(struct e1000_hw *hw)
682011ff 5155{
682011ff 5156 struct e1000_rx_desc *rd;
06e07f65 5157 unsigned long inval_start, inval_end;
873e8e01
MV		 5158 uint32_t len;
5159
682011ff
WD		 5160 /* return true if there's an ethernet packet ready to read */
5161 rd = rx_base + rx_last;
873e8e01
MV		 5162
5163 /* Re-load the descriptor from RAM. */
06e07f65 5164 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5165 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5166 invalidate_dcache_range(inval_start, inval_end);
5167
682011ff
WD		 5168 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5169 return 0;
5abf13e4 5170 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
873e8e01
MV		 5171 /* Packet received, make sure the data are re-loaded from RAM. */
5172 len = le32_to_cpu(rd->length);
06e07f65
ML		 5173 invalidate_dcache_range((unsigned long)packet,
5174 (unsigned long)packet +
5175 roundup(len, ARCH_DMA_MINALIGN));
5c5e707a 5176 return len;
682011ff
WD		 5177}
5178
5c5e707a 5179static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
682011ff 5180{
873e8e01 5181 void *nv_packet = (void *)txpacket;
682011ff
WD		 5182 struct e1000_tx_desc *txp;
5183 int i = 0;
06e07f65 5184 unsigned long flush_start, flush_end;
682011ff
WD		 5185
5186 txp = tx_base + tx_tail;
5187 tx_tail = (tx_tail + 1) % 8;
5188
8aa858cb 5189 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
aa070789 5190 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
682011ff 5191 txp->upper.data = 0;
873e8e01
MV		 5192
5193 /* Dump the packet into RAM so e1000 can pick them. */
06e07f65
ML		 5194 flush_dcache_range((unsigned long)nv_packet,
5195 (unsigned long)nv_packet +
5196 roundup(length, ARCH_DMA_MINALIGN));
873e8e01 5197 /* Dump the descriptor into RAM as well. */
06e07f65 5198 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
873e8e01
MV		 5199 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5200 flush_dcache_range(flush_start, flush_end);
5201
682011ff
WD		 5202 E1000_WRITE_REG(hw, TDT, tx_tail);
5203
aa070789 5204 E1000_WRITE_FLUSH(hw);
873e8e01
MV		 5205 while (1) {
5206 invalidate_dcache_range(flush_start, flush_end);
5207 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5208 break;
682011ff
WD		 5209 if (i++ > TOUT_LOOP) {
5210 DEBUGOUT("e1000: tx timeout\n");
5211 return 0;
5212 }
5213 udelay(10); /* give the nic a chance to write to the register */
5214 }
5215 return 1;
5216}
5217
682011ff 5218static void
5c5e707a 5219_e1000_disable(struct e1000_hw *hw)
682011ff 5220{
682011ff
WD		 5221 /* Turn off the ethernet interface */
5222 E1000_WRITE_REG(hw, RCTL, 0);
5223 E1000_WRITE_REG(hw, TCTL, 0);
5224
5225 /* Clear the transmit ring */
5226 E1000_WRITE_REG(hw, TDH, 0);
5227 E1000_WRITE_REG(hw, TDT, 0);
5228
5229 /* Clear the receive ring */
5230 E1000_WRITE_REG(hw, RDH, 0);
5231 E1000_WRITE_REG(hw, RDT, 0);
5232
5233 /* put the card in its initial state */
5234#if 0
5235 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5236#endif
5237 mdelay(10);
5c5e707a 5238}
682011ff 5239
5c5e707a
SG		 5240/*reset function*/
5241static inline int
5242e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5243{
5244 e1000_reset_hw(hw);
5245 if (hw->mac_type >= e1000_82544)
5246 E1000_WRITE_REG(hw, WUC, 0);
5247
5248 return e1000_init_hw(hw, enetaddr);
682011ff
WD		 5249}
5250
682011ff 5251static int
5c5e707a 5252_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
682011ff 5253{
682011ff
WD		 5254 int ret_val = 0;
5255
5c5e707a 5256 ret_val = e1000_reset(hw, enetaddr);
682011ff
WD		 5257 if (ret_val < 0) {
5258 if ((ret_val == -E1000_ERR_NOLINK) ||
5259 (ret_val == -E1000_ERR_TIMEOUT)) {
5c5e707a 5260 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
682011ff 5261 } else {
5c5e707a 5262 E1000_ERR(hw, "Hardware Initialization Failed\n");
682011ff 5263 }
5c5e707a 5264 return ret_val;
682011ff
WD		 5265 }
5266 e1000_configure_tx(hw);
5267 e1000_setup_rctl(hw);
5268 e1000_configure_rx(hw);
5c5e707a 5269 return 0;
682011ff
WD		 5270}
5271
aa070789
RZ		 5272/******************************************************************************
5273 * Gets the current PCI bus type of hardware
5274 *
5275 * hw - Struct containing variables accessed by shared code
5276 *****************************************************************************/
5277void e1000_get_bus_type(struct e1000_hw *hw)
5278{
5279 uint32_t status;
5280
5281 switch (hw->mac_type) {
5282 case e1000_82542_rev2_0:
5283 case e1000_82542_rev2_1:
5284 hw->bus_type = e1000_bus_type_pci;
5285 break;
5286 case e1000_82571:
5287 case e1000_82572:
5288 case e1000_82573:
2c2668f9 5289 case e1000_82574:
aa070789 5290 case e1000_80003es2lan:
aa070789 5291 case e1000_ich8lan:
95186063 5292 case e1000_igb:
aa070789
RZ		 5293 hw->bus_type = e1000_bus_type_pci_express;
5294 break;
5295 default:
5296 status = E1000_READ_REG(hw, STATUS);
5297 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5298 e1000_bus_type_pcix : e1000_bus_type_pci;
5299 break;
5300 }
5301}
5302
c6d80a15 5303#ifndef CONFIG_DM_ETH
ce5207e1
KM		 5304/* A list of all registered e1000 devices */
5305static LIST_HEAD(e1000_hw_list);
c6d80a15 5306#endif
ce5207e1 5307
5c5e707a
SG		 5308static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5309 unsigned char enetaddr[6])
5310{
5311 u32 val;
5312
5313 /* Assign the passed-in values */
5314 hw->pdev = devno;
5315 hw->cardnum = cardnum;
5316
5317 /* Print a debug message with the IO base address */
5318 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5319 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5320
5321 /* Try to enable I/O accesses and bus-mastering */
5322 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5323 pci_write_config_dword(devno, PCI_COMMAND, val);
5324
5325 /* Make sure it worked */
5326 pci_read_config_dword(devno, PCI_COMMAND, &val);
5327 if (!(val & PCI_COMMAND_MEMORY)) {
5328 E1000_ERR(hw, "Can't enable I/O memory\n");
5329 return -ENOSPC;
5330 }
5331 if (!(val & PCI_COMMAND_MASTER)) {
5332 E1000_ERR(hw, "Can't enable bus-mastering\n");
5333 return -EPERM;
5334 }
5335
5336 /* Are these variables needed? */
5337 hw->fc = e1000_fc_default;
5338 hw->original_fc = e1000_fc_default;
5339 hw->autoneg_failed = 0;
5340 hw->autoneg = 1;
5341 hw->get_link_status = true;
5342#ifndef CONFIG_E1000_NO_NVM
5343 hw->eeprom_semaphore_present = true;
5344#endif
5345 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5346 PCI_REGION_MEM);
5347 hw->mac_type = e1000_undefined;
5348
5349 /* MAC and Phy settings */
5350 if (e1000_sw_init(hw) < 0) {
5351 E1000_ERR(hw, "Software init failed\n");
5352 return -EIO;
5353 }
5354 if (e1000_check_phy_reset_block(hw))
5355 E1000_ERR(hw, "PHY Reset is blocked!\n");
5356
5357 /* Basic init was OK, reset the hardware and allow SPI access */
5358 e1000_reset_hw(hw);
5359
5360#ifndef CONFIG_E1000_NO_NVM
5361 /* Validate the EEPROM and get chipset information */
5362#if !defined(CONFIG_MVBC_1G)
5363 if (e1000_init_eeprom_params(hw)) {
5364 E1000_ERR(hw, "EEPROM is invalid!\n");
5365 return -EINVAL;
5366 }
5367 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5368 e1000_validate_eeprom_checksum(hw))
5369 return -ENXIO;
5370#endif
5371 e1000_read_mac_addr(hw, enetaddr);
5372#endif
5373 e1000_get_bus_type(hw);
5374
5375#ifndef CONFIG_E1000_NO_NVM
5376 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5377 enetaddr[0], enetaddr[1], enetaddr[2],
5378 enetaddr[3], enetaddr[4], enetaddr[5]);
5379#else
5380 memset(enetaddr, 0, 6);
5381 printf("e1000: no NVM\n");
5382#endif
5383
5384 return 0;
5385}
5386
5387/* Put the name of a device in a string */
5388static void e1000_name(char *str, int cardnum)
5389{
5390 sprintf(str, "e1000#%u", cardnum);
5391}
5392
c6d80a15 5393#ifndef CONFIG_DM_ETH
5c5e707a
SG		 5394/**************************************************************************
5395TRANSMIT - Transmit a frame
5396***************************************************************************/
5397static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5398{
5399 struct e1000_hw *hw = nic->priv;
5400
5401 return _e1000_transmit(hw, txpacket, length);
5402}
5403
5404/**************************************************************************
5405DISABLE - Turn off ethernet interface
5406***************************************************************************/
5407static void
5408e1000_disable(struct eth_device *nic)
5409{
5410 struct e1000_hw *hw = nic->priv;
5411
5412 _e1000_disable(hw);
5413}
5414
5415/**************************************************************************
5416INIT - set up ethernet interface(s)
5417***************************************************************************/
5418static int
5419e1000_init(struct eth_device *nic, bd_t *bis)
5420{
5421 struct e1000_hw *hw = nic->priv;
5422
5423 return _e1000_init(hw, nic->enetaddr);
5424}
5425
5426static int
5427e1000_poll(struct eth_device *nic)
5428{
5429 struct e1000_hw *hw = nic->priv;
5430 int len;
5431
5432 len = _e1000_poll(hw);
5433 if (len) {
5434 net_process_received_packet((uchar *)packet, len);
5435 fill_rx(hw);
5436 }
5437
5438 return len ? 1 : 0;
5439}
5440
682011ff
WD		 5441/**************************************************************************
5442PROBE - Look for an adapter, this routine's visible to the outside
5443You should omit the last argument struct pci_device * for a non-PCI NIC
5444***************************************************************************/
5445int
5446e1000_initialize(bd_t * bis)
5447{
d60626f8 5448 unsigned int i;
682011ff 5449 pci_dev_t devno;
5c5e707a 5450 int ret;
682011ff 5451
f81ecb5d
TT		 5452 DEBUGFUNC();
5453
d60626f8
KM		 5454 /* Find and probe all the matching PCI devices */
5455 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
d60626f8
KM		 5456 /*
5457 * These will never get freed due to errors, this allows us to
5458 * perform SPI EEPROM programming from U-boot, for example.
5459 */
5460 struct eth_device *nic = malloc(sizeof(*nic));
5461 struct e1000_hw *hw = malloc(sizeof(*hw));
5462 if (!nic || !hw) {
5463 printf("e1000#%u: Out of Memory!\n", i);
4b29bdb0 5464 free(nic);
d60626f8
KM		 5465 free(hw);
5466 continue;
4b29bdb0
KG		 5467 }
5468
d60626f8 5469 /* Make sure all of the fields are initially zeroed */
f7ac99fd 5470 memset(nic, 0, sizeof(*nic));
4b29bdb0 5471 memset(hw, 0, sizeof(*hw));
682011ff 5472 nic->priv = hw;
682011ff 5473
d60626f8 5474 /* Generate a card name */
5c5e707a
SG		 5475 e1000_name(nic->name, i);
5476 hw->name = nic->name;
682011ff 5477
5c5e707a
SG		 5478 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5479 if (ret)
d60626f8 5480 continue;
ce5207e1 5481 list_add_tail(&hw->list_node, &e1000_hw_list);
d60626f8 5482
5c5e707a 5483 hw->nic = nic;
682011ff 5484
d60626f8 5485 /* Set up the function pointers and register the device */
682011ff
WD		 5486 nic->init = e1000_init;
5487 nic->recv = e1000_poll;
5488 nic->send = e1000_transmit;
5489 nic->halt = e1000_disable;
682011ff 5490 eth_register(nic);
682011ff 5491 }
d60626f8
KM		 5492
5493 return i;
682011ff 5494}
ce5207e1
KM		 5495
5496struct e1000_hw *e1000_find_card(unsigned int cardnum)
5497{
5498 struct e1000_hw *hw;
5499
5500 list_for_each_entry(hw, &e1000_hw_list, list_node)
5501 if (hw->cardnum == cardnum)
5502 return hw;
5503
5504 return NULL;
5505}
c6d80a15 5506#endif /* !CONFIG_DM_ETH */
ce5207e1
KM		 5507
5508#ifdef CONFIG_CMD_E1000
5509static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5510 int argc, char * const argv[])
5511{
5c5e707a 5512 unsigned char *mac = NULL;
c6d80a15
SG		 5513#ifdef CONFIG_DM_ETH
5514 struct eth_pdata *plat;
5515 struct udevice *dev;
5516 char name[30];
5517 int ret;
5518#else
ce5207e1 5519 struct e1000_hw *hw;
c6d80a15
SG		 5520#endif
5521 int cardnum;
ce5207e1
KM		 5522
5523 if (argc < 3) {
5524 cmd_usage(cmdtp);
5525 return 1;
5526 }
5527
5528 /* Make sure we can find the requested e1000 card */
5c5e707a 5529 cardnum = simple_strtoul(argv[1], NULL, 10);
c6d80a15
SG		 5530#ifdef CONFIG_DM_ETH
5531 e1000_name(name, cardnum);
5532 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5533 if (!ret) {
5534 plat = dev_get_platdata(dev);
5535 mac = plat->enetaddr;
5536 }
5537#else
5c5e707a
SG		 5538 hw = e1000_find_card(cardnum);
5539 if (hw)
5540 mac = hw->nic->enetaddr;
c6d80a15 5541#endif
5c5e707a 5542 if (!mac) {
ce5207e1
KM		 5543 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5544 return 1;
5545 }
5546
5547 if (!strcmp(argv[2], "print-mac-address")) {
ce5207e1
KM		 5548 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5549 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5550 return 0;
5551 }
5552
5553#ifdef CONFIG_E1000_SPI
5554 /* Handle the "SPI" subcommand */
5555 if (!strcmp(argv[2], "spi"))
5556 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5557#endif
5558
5559 cmd_usage(cmdtp);
5560 return 1;
5561}
5562
5563U_BOOT_CMD(
5564 e1000, 7, 0, do_e1000,
5565 "Intel e1000 controller management",
5566 /* */"<card#> print-mac-address\n"
5567#ifdef CONFIG_E1000_SPI
5568 "e1000 <card#> spi show [<offset> [<length>]]\n"
5569 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5570 "e1000 <card#> spi program <addr> <offset> <length>\n"
5571 "e1000 <card#> spi checksum [update]\n"
5572#endif
5573 " - Manage the Intel E1000 PCI device"
5574);
5575#endif /* not CONFIG_CMD_E1000 */
c6d80a15
SG		 5576
5577#ifdef CONFIG_DM_ETH
5578static int e1000_eth_start(struct udevice *dev)
5579{
5580 struct eth_pdata *plat = dev_get_platdata(dev);
5581 struct e1000_hw *hw = dev_get_priv(dev);
5582
5583 return _e1000_init(hw, plat->enetaddr);
5584}
5585
5586static void e1000_eth_stop(struct udevice *dev)
5587{
5588 struct e1000_hw *hw = dev_get_priv(dev);
5589
5590 _e1000_disable(hw);
5591}
5592
5593static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5594{
5595 struct e1000_hw *hw = dev_get_priv(dev);
5596 int ret;
5597
5598 ret = _e1000_transmit(hw, packet, length);
5599
5600 return ret ? 0 : -ETIMEDOUT;
5601}
5602
5603static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5604{
5605 struct e1000_hw *hw = dev_get_priv(dev);
5606 int len;
5607
5608 len = _e1000_poll(hw);
5609 if (len)
5610 *packetp = packet;
5611
5612 return len ? len : -EAGAIN;
5613}
5614
5615static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5616{
5617 struct e1000_hw *hw = dev_get_priv(dev);
5618
5619 fill_rx(hw);
5620
5621 return 0;
5622}
5623
5624static int e1000_eth_probe(struct udevice *dev)
5625{
5626 struct eth_pdata *plat = dev_get_platdata(dev);
5627 struct e1000_hw *hw = dev_get_priv(dev);
5628 int ret;
5629
5630 hw->name = dev->name;
5631 ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev),
5632 plat->enetaddr);
5633 if (ret < 0) {
5634 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5635 return ret;
5636 }
5637
5638 return 0;
5639}
5640
5641static int e1000_eth_bind(struct udevice *dev)
5642{
5643 char name[20];
5644
5645 /*
5646 * A simple way to number the devices. When device tree is used this
5647 * is unnecessary, but when the device is just discovered on the PCI
5648 * bus we need a name. We could instead have the uclass figure out
5649 * which devices are different and number them.
5650 */
5651 e1000_name(name, num_cards++);
5652
5653 return device_set_name(dev, name);
5654}
5655
5656static const struct eth_ops e1000_eth_ops = {
5657 .start = e1000_eth_start,
5658 .send = e1000_eth_send,
5659 .recv = e1000_eth_recv,
5660 .stop = e1000_eth_stop,
5661 .free_pkt = e1000_free_pkt,
5662};
5663
5664static const struct udevice_id e1000_eth_ids[] = {
5665 { .compatible = "intel,e1000" },
5666 { }
5667};
5668
5669U_BOOT_DRIVER(eth_e1000) = {
5670 .name = "eth_e1000",
5671 .id = UCLASS_ETH,
5672 .of_match = e1000_eth_ids,
5673 .bind = e1000_eth_bind,
5674 .probe = e1000_eth_probe,
5675 .ops = &e1000_eth_ops,
5676 .priv_auto_alloc_size = sizeof(struct e1000_hw),
5677 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5678};
5679
5680U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
5681#endif
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