[people/ms/u-boot.git] / drivers / net / ethoc.c

/*
 * Opencore 10/100 ethernet mac driver
 *
 * Copyright (C) 2007-2008 Avionic Design Development GmbH
 * Copyright (C) 2008-2009 Avionic Design GmbH
 *   Thierry Reding <thierry.reding@avionic-design.de>
 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <common.h>
#include <linux/io.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/cache.h>

/* register offsets */
#define	MODER		0x00
#define	INT_SOURCE	0x04
#define	INT_MASK	0x08
#define	IPGT		0x0c
#define	IPGR1		0x10
#define	IPGR2		0x14
#define	PACKETLEN	0x18
#define	COLLCONF	0x1c
#define	TX_BD_NUM	0x20
#define	CTRLMODER	0x24
#define	MIIMODER	0x28
#define	MIICOMMAND	0x2c
#define	MIIADDRESS	0x30
#define	MIITX_DATA	0x34
#define	MIIRX_DATA	0x38
#define	MIISTATUS	0x3c
#define	MAC_ADDR0	0x40
#define	MAC_ADDR1	0x44
#define	ETH_HASH0	0x48
#define	ETH_HASH1	0x4c
#define	ETH_TXCTRL	0x50

/* mode register */
#define	MODER_RXEN	(1 <<  0)	/* receive enable */
#define	MODER_TXEN	(1 <<  1)	/* transmit enable */
#define	MODER_NOPRE	(1 <<  2)	/* no preamble */
#define	MODER_BRO	(1 <<  3)	/* broadcast address */
#define	MODER_IAM	(1 <<  4)	/* individual address mode */
#define	MODER_PRO	(1 <<  5)	/* promiscuous mode */
#define	MODER_IFG	(1 <<  6)	/* interframe gap for incoming frames */
#define	MODER_LOOP	(1 <<  7)	/* loopback */
#define	MODER_NBO	(1 <<  8)	/* no back-off */
#define	MODER_EDE	(1 <<  9)	/* excess defer enable */
#define	MODER_FULLD	(1 << 10)	/* full duplex */
#define	MODER_RESET	(1 << 11)	/* FIXME: reset (undocumented) */
#define	MODER_DCRC	(1 << 12)	/* delayed CRC enable */
#define	MODER_CRC	(1 << 13)	/* CRC enable */
#define	MODER_HUGE	(1 << 14)	/* huge packets enable */
#define	MODER_PAD	(1 << 15)	/* padding enabled */
#define	MODER_RSM	(1 << 16)	/* receive small packets */

/* interrupt source and mask registers */
#define	INT_MASK_TXF	(1 << 0)	/* transmit frame */
#define	INT_MASK_TXE	(1 << 1)	/* transmit error */
#define	INT_MASK_RXF	(1 << 2)	/* receive frame */
#define	INT_MASK_RXE	(1 << 3)	/* receive error */
#define	INT_MASK_BUSY	(1 << 4)
#define	INT_MASK_TXC	(1 << 5)	/* transmit control frame */
#define	INT_MASK_RXC	(1 << 6)	/* receive control frame */

#define	INT_MASK_TX	(INT_MASK_TXF | INT_MASK_TXE)
#define	INT_MASK_RX	(INT_MASK_RXF | INT_MASK_RXE)

#define	INT_MASK_ALL ( \
		INT_MASK_TXF | INT_MASK_TXE | \
		INT_MASK_RXF | INT_MASK_RXE | \
		INT_MASK_TXC | INT_MASK_RXC | \
		INT_MASK_BUSY \
	)

/* packet length register */
#define	PACKETLEN_MIN(min)		(((min) & 0xffff) << 16)
#define	PACKETLEN_MAX(max)		(((max) & 0xffff) <<  0)
#define	PACKETLEN_MIN_MAX(min, max)	(PACKETLEN_MIN(min) | \
					PACKETLEN_MAX(max))

/* transmit buffer number register */
#define	TX_BD_NUM_VAL(x)	(((x) <= 0x80) ? (x) : 0x80)

/* control module mode register */
#define	CTRLMODER_PASSALL	(1 << 0)	/* pass all receive frames */
#define	CTRLMODER_RXFLOW	(1 << 1)	/* receive control flow */
#define	CTRLMODER_TXFLOW	(1 << 2)	/* transmit control flow */

/* MII mode register */
#define	MIIMODER_CLKDIV(x)	((x) & 0xfe)	/* needs to be an even number */
#define	MIIMODER_NOPRE		(1 << 8)	/* no preamble */

/* MII command register */
#define	MIICOMMAND_SCAN		(1 << 0)	/* scan status */
#define	MIICOMMAND_READ		(1 << 1)	/* read status */
#define	MIICOMMAND_WRITE	(1 << 2)	/* write control data */

/* MII address register */
#define	MIIADDRESS_FIAD(x)		(((x) & 0x1f) << 0)
#define	MIIADDRESS_RGAD(x)		(((x) & 0x1f) << 8)
#define	MIIADDRESS_ADDR(phy, reg)	(MIIADDRESS_FIAD(phy) | \
					MIIADDRESS_RGAD(reg))

/* MII transmit data register */
#define	MIITX_DATA_VAL(x)	((x) & 0xffff)

/* MII receive data register */
#define	MIIRX_DATA_VAL(x)	((x) & 0xffff)

/* MII status register */
#define	MIISTATUS_LINKFAIL	(1 << 0)
#define	MIISTATUS_BUSY		(1 << 1)
#define	MIISTATUS_INVALID	(1 << 2)

/* TX buffer descriptor */
#define	TX_BD_CS		(1 <<  0)	/* carrier sense lost */
#define	TX_BD_DF		(1 <<  1)	/* defer indication */
#define	TX_BD_LC		(1 <<  2)	/* late collision */
#define	TX_BD_RL		(1 <<  3)	/* retransmission limit */
#define	TX_BD_RETRY_MASK	(0x00f0)
#define	TX_BD_RETRY(x)		(((x) & 0x00f0) >>  4)
#define	TX_BD_UR		(1 <<  8)	/* transmitter underrun */
#define	TX_BD_CRC		(1 << 11)	/* TX CRC enable */
#define	TX_BD_PAD		(1 << 12)	/* pad enable */
#define	TX_BD_WRAP		(1 << 13)
#define	TX_BD_IRQ		(1 << 14)	/* interrupt request enable */
#define	TX_BD_READY		(1 << 15)	/* TX buffer ready */
#define	TX_BD_LEN(x)		(((x) & 0xffff) << 16)
#define	TX_BD_LEN_MASK		(0xffff << 16)

#define	TX_BD_STATS		(TX_BD_CS | TX_BD_DF | TX_BD_LC | \
				TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)

/* RX buffer descriptor */
#define	RX_BD_LC	(1 <<  0)	/* late collision */
#define	RX_BD_CRC	(1 <<  1)	/* RX CRC error */
#define	RX_BD_SF	(1 <<  2)	/* short frame */
#define	RX_BD_TL	(1 <<  3)	/* too long */
#define	RX_BD_DN	(1 <<  4)	/* dribble nibble */
#define	RX_BD_IS	(1 <<  5)	/* invalid symbol */
#define	RX_BD_OR	(1 <<  6)	/* receiver overrun */
#define	RX_BD_MISS	(1 <<  7)
#define	RX_BD_CF	(1 <<  8)	/* control frame */
#define	RX_BD_WRAP	(1 << 13)
#define	RX_BD_IRQ	(1 << 14)	/* interrupt request enable */
#define	RX_BD_EMPTY	(1 << 15)
#define	RX_BD_LEN(x)	(((x) & 0xffff) << 16)

#define	RX_BD_STATS	(RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
			RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)

#define	ETHOC_BUFSIZ		1536
#define	ETHOC_ZLEN		64
#define	ETHOC_BD_BASE		0x400
#define	ETHOC_TIMEOUT		(HZ / 2)
#define	ETHOC_MII_TIMEOUT	(1 + (HZ / 5))
#define	ETHOC_IOSIZE		0x54

/**
 * struct ethoc - driver-private device structure
 * @num_tx:	number of send buffers
 * @cur_tx:	last send buffer written
 * @dty_tx:	last buffer actually sent
 * @num_rx:	number of receive buffers
 * @cur_rx:	current receive buffer
 */
struct ethoc {
	u32 num_tx;
	u32 cur_tx;
	u32 dty_tx;
	u32 num_rx;
	u32 cur_rx;
	void __iomem *iobase;
};

/**
 * struct ethoc_bd - buffer descriptor
 * @stat:	buffer statistics
 * @addr:	physical memory address
 */
struct ethoc_bd {
	u32 stat;
	u32 addr;
};

static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
{
	return readl(priv->iobase + offset);
}

static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
{
	writel(data, priv->iobase + offset);
}

static inline void ethoc_read_bd(struct ethoc *priv, int index,
				 struct ethoc_bd *bd)
{
	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
	bd->stat = ethoc_read(priv, offset + 0);
	bd->addr = ethoc_read(priv, offset + 4);
}

static inline void ethoc_write_bd(struct ethoc *priv, int index,
				  const struct ethoc_bd *bd)
{
	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
	ethoc_write(priv, offset + 0, bd->stat);
	ethoc_write(priv, offset + 4, bd->addr);
}

static int ethoc_set_mac_address(struct eth_device *dev)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;
	u8 *mac = dev->enetaddr;

	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
		    (mac[4] << 8) | (mac[5] << 0));
	ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
	return 0;
}

static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
{
	ethoc_write(priv, INT_SOURCE, mask);
}

static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
{
	u32 mode = ethoc_read(priv, MODER);
	mode |= MODER_RXEN | MODER_TXEN;
	ethoc_write(priv, MODER, mode);
}

static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
{
	u32 mode = ethoc_read(priv, MODER);
	mode &= ~(MODER_RXEN | MODER_TXEN);
	ethoc_write(priv, MODER, mode);
}

static int ethoc_init_ring(struct ethoc *priv)
{
	struct ethoc_bd bd;
	int i;

	priv->cur_tx = 0;
	priv->dty_tx = 0;
	priv->cur_rx = 0;

	/* setup transmission buffers */
	bd.stat = TX_BD_IRQ | TX_BD_CRC;

	for (i = 0; i < priv->num_tx; i++) {
		if (i == priv->num_tx - 1)
			bd.stat |= TX_BD_WRAP;

		ethoc_write_bd(priv, i, &bd);
	}

	bd.stat = RX_BD_EMPTY | RX_BD_IRQ;

	for (i = 0; i < priv->num_rx; i++) {
		bd.addr = (u32)net_rx_packets[i];
		if (i == priv->num_rx - 1)
			bd.stat |= RX_BD_WRAP;

		flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
		ethoc_write_bd(priv, priv->num_tx + i, &bd);
	}

	return 0;
}

static int ethoc_reset(struct ethoc *priv)
{
	u32 mode;

	/* TODO: reset controller? */

	ethoc_disable_rx_and_tx(priv);

	/* TODO: setup registers */

	/* enable FCS generation and automatic padding */
	mode = ethoc_read(priv, MODER);
	mode |= MODER_CRC | MODER_PAD;
	ethoc_write(priv, MODER, mode);

	/* set full-duplex mode */
	mode = ethoc_read(priv, MODER);
	mode |= MODER_FULLD;
	ethoc_write(priv, MODER, mode);
	ethoc_write(priv, IPGT, 0x15);

	ethoc_ack_irq(priv, INT_MASK_ALL);
	ethoc_enable_rx_and_tx(priv);
	return 0;
}

static int ethoc_init(struct eth_device *dev, bd_t * bd)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;
	printf("ethoc\n");

	priv->num_tx = 1;
	priv->num_rx = PKTBUFSRX;
	ethoc_write(priv, TX_BD_NUM, priv->num_tx);
	ethoc_init_ring(priv);
	ethoc_reset(priv);

	return 0;
}

static int ethoc_update_rx_stats(struct ethoc_bd *bd)
{
	int ret = 0;

	if (bd->stat & RX_BD_TL) {
		debug("ETHOC: " "RX: frame too long\n");
		ret++;
	}

	if (bd->stat & RX_BD_SF) {
		debug("ETHOC: " "RX: frame too short\n");
		ret++;
	}

	if (bd->stat & RX_BD_DN)
		debug("ETHOC: " "RX: dribble nibble\n");

	if (bd->stat & RX_BD_CRC) {
		debug("ETHOC: " "RX: wrong CRC\n");
		ret++;
	}

	if (bd->stat & RX_BD_OR) {
		debug("ETHOC: " "RX: overrun\n");
		ret++;
	}

	if (bd->stat & RX_BD_LC) {
		debug("ETHOC: " "RX: late collision\n");
		ret++;
	}

	return ret;
}

static int ethoc_rx(struct ethoc *priv, int limit)
{
	int count;

	for (count = 0; count < limit; ++count) {
		u32 entry;
		struct ethoc_bd bd;

		entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
		ethoc_read_bd(priv, entry, &bd);
		if (bd.stat & RX_BD_EMPTY)
			break;

		debug("%s(): RX buffer %d, %x received\n",
		      __func__, priv->cur_rx, bd.stat);
		if (ethoc_update_rx_stats(&bd) == 0) {
			int size = bd.stat >> 16;
			size -= 4;	/* strip the CRC */
			net_process_received_packet((void *)bd.addr, size);
		}

		/* clear the buffer descriptor so it can be reused */
		flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
		bd.stat &= ~RX_BD_STATS;
		bd.stat |= RX_BD_EMPTY;
		ethoc_write_bd(priv, entry, &bd);
		priv->cur_rx++;
	}

	return count;
}

static int ethoc_update_tx_stats(struct ethoc_bd *bd)
{
	if (bd->stat & TX_BD_LC)
		debug("ETHOC: " "TX: late collision\n");

	if (bd->stat & TX_BD_RL)
		debug("ETHOC: " "TX: retransmit limit\n");

	if (bd->stat & TX_BD_UR)
		debug("ETHOC: " "TX: underrun\n");

	if (bd->stat & TX_BD_CS)
		debug("ETHOC: " "TX: carrier sense lost\n");

	return 0;
}

static void ethoc_tx(struct ethoc *priv)
{
	u32 entry = priv->dty_tx % priv->num_tx;
	struct ethoc_bd bd;

	ethoc_read_bd(priv, entry, &bd);
	if ((bd.stat & TX_BD_READY) == 0)
		(void)ethoc_update_tx_stats(&bd);
}

static int ethoc_send(struct eth_device *dev, void *packet, int length)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;
	struct ethoc_bd bd;
	u32 entry;
	u32 pending;
	int tmo;

	entry = priv->cur_tx % priv->num_tx;
	ethoc_read_bd(priv, entry, &bd);
	if (unlikely(length < ETHOC_ZLEN))
		bd.stat |= TX_BD_PAD;
	else
		bd.stat &= ~TX_BD_PAD;
	bd.addr = (u32)packet;

	flush_dcache_range(bd.addr, bd.addr + length);
	bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
	bd.stat |= TX_BD_LEN(length);
	ethoc_write_bd(priv, entry, &bd);

	/* start transmit */
	bd.stat |= TX_BD_READY;
	ethoc_write_bd(priv, entry, &bd);

	/* wait for transfer to succeed */
	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	while (1) {
		pending = ethoc_read(priv, INT_SOURCE);
		ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
		if (pending & INT_MASK_BUSY)
			debug("%s(): packet dropped\n", __func__);

		if (pending & INT_MASK_TX) {
			ethoc_tx(priv);
			break;
		}
		if (get_timer(0) >= tmo) {
			debug("%s(): timed out\n", __func__);
			return -1;
		}
	}

	debug("%s(): packet sent\n", __func__);
	return 0;
}

static void ethoc_halt(struct eth_device *dev)
{
	ethoc_disable_rx_and_tx(dev->priv);
}

static int ethoc_recv(struct eth_device *dev)
{
	struct ethoc *priv = (struct ethoc *)dev->priv;
	u32 pending;

	pending = ethoc_read(priv, INT_SOURCE);
	ethoc_ack_irq(priv, pending);
	if (pending & INT_MASK_BUSY)
		debug("%s(): packet dropped\n", __func__);
	if (pending & INT_MASK_RX) {
		debug("%s(): rx irq\n", __func__);
		ethoc_rx(priv, PKTBUFSRX);
	}

	return 0;
}

int ethoc_initialize(u8 dev_num, int base_addr)
{
	struct ethoc *priv;
	struct eth_device *dev;

	priv = malloc(sizeof(*priv));
	if (!priv)
		return 0;
	dev = malloc(sizeof(*dev));
	if (!dev) {
		free(priv);
		return 0;
	}

	memset(dev, 0, sizeof(*dev));
	dev->priv = priv;
	dev->iobase = base_addr;
	dev->init = ethoc_init;
	dev->halt = ethoc_halt;
	dev->send = ethoc_send;
	dev->recv = ethoc_recv;
	dev->write_hwaddr = ethoc_set_mac_address;
	sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
	priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);

	eth_register(dev);
	return 1;
}
Commit	Line	Data
f6569884 TC	1	/*
	2	* Opencore 10/100 ethernet mac driver
	3	*
	4	* Copyright (C) 2007-2008 Avionic Design Development GmbH
	5	* Copyright (C) 2008-2009 Avionic Design GmbH
	6	* Thierry Reding <thierry.reding@avionic-design.de>
	7	* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <common.h>
a84a757a	15	#include <linux/io.h>
f6569884 TC	16	#include <malloc.h>
	17	#include <net.h>
	18	#include <miiphy.h>
f6569884 TC	19	#include <asm/cache.h>
	20
	21	/* register offsets */
	22	#define MODER 0x00
	23	#define INT_SOURCE 0x04
	24	#define INT_MASK 0x08
	25	#define IPGT 0x0c
	26	#define IPGR1 0x10
	27	#define IPGR2 0x14
	28	#define PACKETLEN 0x18
	29	#define COLLCONF 0x1c
	30	#define TX_BD_NUM 0x20
	31	#define CTRLMODER 0x24
	32	#define MIIMODER 0x28
	33	#define MIICOMMAND 0x2c
	34	#define MIIADDRESS 0x30
	35	#define MIITX_DATA 0x34
	36	#define MIIRX_DATA 0x38
	37	#define MIISTATUS 0x3c
	38	#define MAC_ADDR0 0x40
	39	#define MAC_ADDR1 0x44
	40	#define ETH_HASH0 0x48
	41	#define ETH_HASH1 0x4c
	42	#define ETH_TXCTRL 0x50
	43
	44	/* mode register */
	45	#define MODER_RXEN (1 << 0) /* receive enable */
	46	#define MODER_TXEN (1 << 1) /* transmit enable */
	47	#define MODER_NOPRE (1 << 2) /* no preamble */
	48	#define MODER_BRO (1 << 3) /* broadcast address */
	49	#define MODER_IAM (1 << 4) /* individual address mode */
	50	#define MODER_PRO (1 << 5) /* promiscuous mode */
	51	#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
	52	#define MODER_LOOP (1 << 7) /* loopback */
	53	#define MODER_NBO (1 << 8) /* no back-off */
	54	#define MODER_EDE (1 << 9) /* excess defer enable */
	55	#define MODER_FULLD (1 << 10) /* full duplex */
	56	#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
	57	#define MODER_DCRC (1 << 12) /* delayed CRC enable */
	58	#define MODER_CRC (1 << 13) /* CRC enable */
	59	#define MODER_HUGE (1 << 14) /* huge packets enable */
	60	#define MODER_PAD (1 << 15) /* padding enabled */
	61	#define MODER_RSM (1 << 16) /* receive small packets */
	62
	63	/* interrupt source and mask registers */
	64	#define INT_MASK_TXF (1 << 0) /* transmit frame */
	65	#define INT_MASK_TXE (1 << 1) /* transmit error */
	66	#define INT_MASK_RXF (1 << 2) /* receive frame */
	67	#define INT_MASK_RXE (1 << 3) /* receive error */
	68	#define INT_MASK_BUSY (1 << 4)
	69	#define INT_MASK_TXC (1 << 5) /* transmit control frame */
	70	#define INT_MASK_RXC (1 << 6) /* receive control frame */
	71
	72	#define INT_MASK_TX (INT_MASK_TXF \| INT_MASK_TXE)
	73	#define INT_MASK_RX (INT_MASK_RXF \| INT_MASK_RXE)
	74
	75	#define INT_MASK_ALL ( \
	76	INT_MASK_TXF \| INT_MASK_TXE \| \
	77	INT_MASK_RXF \| INT_MASK_RXE \| \
	78	INT_MASK_TXC \| INT_MASK_RXC \| \
	79	INT_MASK_BUSY \
	80	)
	81
	82	/* packet length register */
83	#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
84	#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
85	#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) \| \
86	PACKETLEN_MAX(max))
87
88	/* transmit buffer number register */
89	#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
90
91	/* control module mode register */
92	#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
93	#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
94	#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
95
96	/* MII mode register */
97	#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
98	#define MIIMODER_NOPRE (1 << 8) /* no preamble */
99
100	/* MII command register */
101	#define MIICOMMAND_SCAN (1 << 0) /* scan status */
102	#define MIICOMMAND_READ (1 << 1) /* read status */
103	#define MIICOMMAND_WRITE (1 << 2) /* write control data */
104
105	/* MII address register */
106	#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
107	#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
108	#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) \| \
109	MIIADDRESS_RGAD(reg))
110
111	/* MII transmit data register */
112	#define MIITX_DATA_VAL(x) ((x) & 0xffff)
113
114	/* MII receive data register */
115	#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
116
117	/* MII status register */
118	#define MIISTATUS_LINKFAIL (1 << 0)
119	#define MIISTATUS_BUSY (1 << 1)
120	#define MIISTATUS_INVALID (1 << 2)
121
122	/* TX buffer descriptor */
123	#define TX_BD_CS (1 << 0) /* carrier sense lost */
124	#define TX_BD_DF (1 << 1) /* defer indication */
125	#define TX_BD_LC (1 << 2) /* late collision */
126	#define TX_BD_RL (1 << 3) /* retransmission limit */
127	#define TX_BD_RETRY_MASK (0x00f0)
128	#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
129	#define TX_BD_UR (1 << 8) /* transmitter underrun */
130	#define TX_BD_CRC (1 << 11) /* TX CRC enable */
131	#define TX_BD_PAD (1 << 12) /* pad enable */
132	#define TX_BD_WRAP (1 << 13)
133	#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
134	#define TX_BD_READY (1 << 15) /* TX buffer ready */
135	#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
136	#define TX_BD_LEN_MASK (0xffff << 16)
137
138	#define TX_BD_STATS (TX_BD_CS \| TX_BD_DF \| TX_BD_LC \| \
139	TX_BD_RL \| TX_BD_RETRY_MASK \| TX_BD_UR)
140
141	/* RX buffer descriptor */
142	#define RX_BD_LC (1 << 0) /* late collision */
143	#define RX_BD_CRC (1 << 1) /* RX CRC error */
144	#define RX_BD_SF (1 << 2) /* short frame */
145	#define RX_BD_TL (1 << 3) /* too long */
146	#define RX_BD_DN (1 << 4) /* dribble nibble */
147	#define RX_BD_IS (1 << 5) /* invalid symbol */
148	#define RX_BD_OR (1 << 6) /* receiver overrun */
149	#define RX_BD_MISS (1 << 7)
150	#define RX_BD_CF (1 << 8) /* control frame */
151	#define RX_BD_WRAP (1 << 13)
152	#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
153	#define RX_BD_EMPTY (1 << 15)
154	#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
155
156	#define RX_BD_STATS (RX_BD_LC \| RX_BD_CRC \| RX_BD_SF \| RX_BD_TL \| \
157	RX_BD_DN \| RX_BD_IS \| RX_BD_OR \| RX_BD_MISS)
158
159	#define ETHOC_BUFSIZ 1536
160	#define ETHOC_ZLEN 64
161	#define ETHOC_BD_BASE 0x400
162	#define ETHOC_TIMEOUT (HZ / 2)
163	#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
a84a757a	164	#define ETHOC_IOSIZE 0x54
f6569884 TC	165
	166	/**
	167	* struct ethoc - driver-private device structure
	168	* @num_tx: number of send buffers
	169	* @cur_tx: last send buffer written
	170	* @dty_tx: last buffer actually sent
	171	* @num_rx: number of receive buffers
	172	* @cur_rx: current receive buffer
	173	*/
	174	struct ethoc {
	175	u32 num_tx;
	176	u32 cur_tx;
	177	u32 dty_tx;
	178	u32 num_rx;
	179	u32 cur_rx;
a84a757a	180	void __iomem *iobase;
f6569884 TC	181	};
	182
	183	/**
	184	* struct ethoc_bd - buffer descriptor
	185	* @stat: buffer statistics
	186	* @addr: physical memory address
	187	*/
	188	struct ethoc_bd {
	189	u32 stat;
	190	u32 addr;
	191	};
	192
a84a757a	193	static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
f6569884	194	{
a84a757a	195	return readl(priv->iobase + offset);
f6569884 TC	196	}
f6569884 TC	197
a84a757a	198	static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
f6569884	199	{
a84a757a	200	writel(data, priv->iobase + offset);
f6569884 TC	201	}
f6569884 TC	202
a84a757a	203	static inline void ethoc_read_bd(struct ethoc *priv, int index,
f6569884 TC	204	struct ethoc_bd *bd)
f6569884 TC	205	{
9f680d2d	206	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
a84a757a MF	207	bd->stat = ethoc_read(priv, offset + 0);
a84a757a MF	208	bd->addr = ethoc_read(priv, offset + 4);
f6569884 TC	209	}
f6569884 TC	210
a84a757a	211	static inline void ethoc_write_bd(struct ethoc *priv, int index,
f6569884 TC	212	const struct ethoc_bd *bd)
f6569884 TC	213	{
9f680d2d	214	size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
a84a757a MF	215	ethoc_write(priv, offset + 0, bd->stat);
a84a757a MF	216	ethoc_write(priv, offset + 4, bd->addr);
f6569884 TC	217	}
f6569884 TC	218
3ac9d6c6	219	static int ethoc_set_mac_address(struct eth_device *dev)
f6569884	220	{
a84a757a	221	struct ethoc priv = (struct ethoc )dev->priv;
f6569884 TC	222	u8 *mac = dev->enetaddr;
f6569884 TC	223
a84a757a	224	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) \| (mac[3] << 16) \|
f6569884	225	(mac[4] << 8) \| (mac[5] << 0));
a84a757a	226	ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) \| (mac[1] << 0));
3ac9d6c6	227	return 0;
f6569884 TC	228	}
f6569884 TC	229
a84a757a	230	static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
f6569884	231	{
a84a757a	232	ethoc_write(priv, INT_SOURCE, mask);
f6569884 TC	233	}
f6569884 TC	234
a84a757a	235	static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
f6569884	236	{
a84a757a	237	u32 mode = ethoc_read(priv, MODER);
f6569884	238	mode \|= MODER_RXEN \| MODER_TXEN;
a84a757a	239	ethoc_write(priv, MODER, mode);
f6569884 TC	240	}
f6569884 TC	241
a84a757a	242	static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
f6569884	243	{
a84a757a	244	u32 mode = ethoc_read(priv, MODER);
f6569884	245	mode &= ~(MODER_RXEN \| MODER_TXEN);
a84a757a	246	ethoc_write(priv, MODER, mode);
f6569884 TC	247	}
f6569884 TC	248
a84a757a	249	static int ethoc_init_ring(struct ethoc *priv)
f6569884	250	{
f6569884 TC	251	struct ethoc_bd bd;
	252	int i;
	253
	254	priv->cur_tx = 0;
	255	priv->dty_tx = 0;
	256	priv->cur_rx = 0;
	257
	258	/* setup transmission buffers */
	259	bd.stat = TX_BD_IRQ \| TX_BD_CRC;
	260
	261	for (i = 0; i < priv->num_tx; i++) {
	262	if (i == priv->num_tx - 1)
	263	bd.stat \|= TX_BD_WRAP;
	264
a84a757a	265	ethoc_write_bd(priv, i, &bd);
f6569884 TC	266	}
	267
	268	bd.stat = RX_BD_EMPTY \| RX_BD_IRQ;
	269
	270	for (i = 0; i < priv->num_rx; i++) {
1fd92db8	271	bd.addr = (u32)net_rx_packets[i];
f6569884 TC	272	if (i == priv->num_rx - 1)
	273	bd.stat \|= RX_BD_WRAP;
	274
83ea1308	275	flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
a84a757a	276	ethoc_write_bd(priv, priv->num_tx + i, &bd);
f6569884 TC	277	}
	278
	279	return 0;
	280	}
	281
a84a757a	282	static int ethoc_reset(struct ethoc *priv)
f6569884 TC	283	{
	284	u32 mode;
	285
	286	/* TODO: reset controller? */
	287
a84a757a	288	ethoc_disable_rx_and_tx(priv);
f6569884 TC	289
	290	/* TODO: setup registers */
	291
	292	/* enable FCS generation and automatic padding */
a84a757a	293	mode = ethoc_read(priv, MODER);
f6569884	294	mode \|= MODER_CRC \| MODER_PAD;
a84a757a	295	ethoc_write(priv, MODER, mode);
f6569884 TC	296
f6569884 TC	297	/* set full-duplex mode */
a84a757a	298	mode = ethoc_read(priv, MODER);
f6569884	299	mode \|= MODER_FULLD;
a84a757a MF	300	ethoc_write(priv, MODER, mode);
a84a757a MF	301	ethoc_write(priv, IPGT, 0x15);
f6569884	302
a84a757a MF	303	ethoc_ack_irq(priv, INT_MASK_ALL);
a84a757a MF	304	ethoc_enable_rx_and_tx(priv);
f6569884 TC	305	return 0;
	306	}
	307
	308	static int ethoc_init(struct eth_device dev, bd_t bd)
	309	{
	310	struct ethoc priv = (struct ethoc )dev->priv;
	311	printf("ethoc\n");
	312
f6569884 TC	313	priv->num_tx = 1;
f6569884 TC	314	priv->num_rx = PKTBUFSRX;
a84a757a MF	315	ethoc_write(priv, TX_BD_NUM, priv->num_tx);
	316	ethoc_init_ring(priv);
	317	ethoc_reset(priv);
f6569884 TC	318
	319	return 0;
	320	}
	321
	322	static int ethoc_update_rx_stats(struct ethoc_bd *bd)
	323	{
	324	int ret = 0;
	325
	326	if (bd->stat & RX_BD_TL) {
	327	debug("ETHOC: " "RX: frame too long\n");
	328	ret++;
	329	}
	330
	331	if (bd->stat & RX_BD_SF) {
	332	debug("ETHOC: " "RX: frame too short\n");
	333	ret++;
	334	}
	335
	336	if (bd->stat & RX_BD_DN)
	337	debug("ETHOC: " "RX: dribble nibble\n");
	338
	339	if (bd->stat & RX_BD_CRC) {
	340	debug("ETHOC: " "RX: wrong CRC\n");
	341	ret++;
	342	}
	343
	344	if (bd->stat & RX_BD_OR) {
	345	debug("ETHOC: " "RX: overrun\n");
	346	ret++;
	347	}
	348
	349	if (bd->stat & RX_BD_LC) {
	350	debug("ETHOC: " "RX: late collision\n");
	351	ret++;
	352	}
	353
	354	return ret;
	355	}
	356
a84a757a	357	static int ethoc_rx(struct ethoc *priv, int limit)
f6569884	358	{
f6569884 TC	359	int count;
	360
	361	for (count = 0; count < limit; ++count) {
	362	u32 entry;
	363	struct ethoc_bd bd;
	364
	365	entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
a84a757a	366	ethoc_read_bd(priv, entry, &bd);
f6569884 TC	367	if (bd.stat & RX_BD_EMPTY)
	368	break;
	369
	370	debug("%s(): RX buffer %d, %x received\n",
	371	__func__, priv->cur_rx, bd.stat);
	372	if (ethoc_update_rx_stats(&bd) == 0) {
	373	int size = bd.stat >> 16;
	374	size -= 4; /* strip the CRC */
1fd92db8	375	net_process_received_packet((void *)bd.addr, size);
f6569884 TC	376	}
	377
	378	/* clear the buffer descriptor so it can be reused */
83ea1308	379	flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN);
f6569884 TC	380	bd.stat &= ~RX_BD_STATS;
f6569884 TC	381	bd.stat \|= RX_BD_EMPTY;
a84a757a	382	ethoc_write_bd(priv, entry, &bd);
f6569884 TC	383	priv->cur_rx++;
	384	}
	385
	386	return count;
	387	}
	388
	389	static int ethoc_update_tx_stats(struct ethoc_bd *bd)
	390	{
	391	if (bd->stat & TX_BD_LC)
	392	debug("ETHOC: " "TX: late collision\n");
	393
	394	if (bd->stat & TX_BD_RL)
	395	debug("ETHOC: " "TX: retransmit limit\n");
	396
	397	if (bd->stat & TX_BD_UR)
	398	debug("ETHOC: " "TX: underrun\n");
	399
	400	if (bd->stat & TX_BD_CS)
	401	debug("ETHOC: " "TX: carrier sense lost\n");
	402
	403	return 0;
	404	}
	405
a84a757a	406	static void ethoc_tx(struct ethoc *priv)
f6569884	407	{
f6569884 TC	408	u32 entry = priv->dty_tx % priv->num_tx;
	409	struct ethoc_bd bd;
	410
a84a757a	411	ethoc_read_bd(priv, entry, &bd);
f6569884 TC	412	if ((bd.stat & TX_BD_READY) == 0)
	413	(void)ethoc_update_tx_stats(&bd);
	414	}
	415
10cbe3b6	416	static int ethoc_send(struct eth_device dev, void packet, int length)
f6569884 TC	417	{
	418	struct ethoc priv = (struct ethoc )dev->priv;
	419	struct ethoc_bd bd;
	420	u32 entry;
	421	u32 pending;
	422	int tmo;
	423
	424	entry = priv->cur_tx % priv->num_tx;
a84a757a	425	ethoc_read_bd(priv, entry, &bd);
f6569884 TC	426	if (unlikely(length < ETHOC_ZLEN))
	427	bd.stat \|= TX_BD_PAD;
	428	else
	429	bd.stat &= ~TX_BD_PAD;
	430	bd.addr = (u32)packet;
	431
83ea1308	432	flush_dcache_range(bd.addr, bd.addr + length);
f6569884 TC	433	bd.stat &= ~(TX_BD_STATS \| TX_BD_LEN_MASK);
f6569884 TC	434	bd.stat \|= TX_BD_LEN(length);
a84a757a	435	ethoc_write_bd(priv, entry, &bd);
f6569884 TC	436
	437	/* start transmit */
	438	bd.stat \|= TX_BD_READY;
a84a757a	439	ethoc_write_bd(priv, entry, &bd);
f6569884 TC	440
	441	/* wait for transfer to succeed */
	442	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	443	while (1) {
a84a757a MF	444	pending = ethoc_read(priv, INT_SOURCE);
a84a757a MF	445	ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
f6569884 TC	446	if (pending & INT_MASK_BUSY)
	447	debug("%s(): packet dropped\n", __func__);
	448
	449	if (pending & INT_MASK_TX) {
a84a757a	450	ethoc_tx(priv);
f6569884 TC	451	break;
	452	}
	453	if (get_timer(0) >= tmo) {
	454	debug("%s(): timed out\n", __func__);
	455	return -1;
	456	}
	457	}
	458
	459	debug("%s(): packet sent\n", __func__);
	460	return 0;
	461	}
	462
	463	static void ethoc_halt(struct eth_device *dev)
	464	{
a84a757a	465	ethoc_disable_rx_and_tx(dev->priv);
f6569884 TC	466	}
	467
	468	static int ethoc_recv(struct eth_device *dev)
	469	{
a84a757a	470	struct ethoc priv = (struct ethoc )dev->priv;
f6569884 TC	471	u32 pending;
f6569884 TC	472
a84a757a MF	473	pending = ethoc_read(priv, INT_SOURCE);
a84a757a MF	474	ethoc_ack_irq(priv, pending);
f6569884 TC	475	if (pending & INT_MASK_BUSY)
	476	debug("%s(): packet dropped\n", __func__);
	477	if (pending & INT_MASK_RX) {
	478	debug("%s(): rx irq\n", __func__);
a84a757a	479	ethoc_rx(priv, PKTBUFSRX);
f6569884 TC	480	}
	481
	482	return 0;
	483	}
	484
	485	int ethoc_initialize(u8 dev_num, int base_addr)
	486	{
	487	struct ethoc *priv;
	488	struct eth_device *dev;
	489
	490	priv = malloc(sizeof(*priv));
	491	if (!priv)
	492	return 0;
	493	dev = malloc(sizeof(*dev));
	494	if (!dev) {
	495	free(priv);
	496	return 0;
	497	}
	498
	499	memset(dev, 0, sizeof(*dev));
	500	dev->priv = priv;
	501	dev->iobase = base_addr;
	502	dev->init = ethoc_init;
	503	dev->halt = ethoc_halt;
	504	dev->send = ethoc_send;
	505	dev->recv = ethoc_recv;
3ac9d6c6	506	dev->write_hwaddr = ethoc_set_mac_address;
f6569884	507	sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
a84a757a	508	priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
f6569884 TC	509
	510	eth_register(dev);
	511	return 1;
	512	}