[people/ms/u-boot.git] / drivers / net / ftmac110.c

/*
 * Faraday 10/100Mbps Ethernet Controller
 *
 * (C) Copyright 2010 Faraday Technology
 * Dante Su <dantesu@faraday-tech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/dma-mapping.h>

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif

#include "ftmac110.h"

#define CFG_RXDES_NUM   8
#define CFG_TXDES_NUM   2
#define CFG_XBUF_SIZE   1536

#define CFG_MDIORD_TIMEOUT  (CONFIG_SYS_HZ >> 1) /* 500 ms */
#define CFG_MDIOWR_TIMEOUT  (CONFIG_SYS_HZ >> 1) /* 500 ms */
#define CFG_LINKUP_TIMEOUT  (CONFIG_SYS_HZ << 2) /* 4 sec */

/*
 * FTMAC110 DMA design issue
 *
 * Its DMA engine has a weird restriction that its Rx DMA engine
 * accepts only 16-bits aligned address, 32-bits aligned is not
 * acceptable. However this restriction does not apply to Tx DMA.
 *
 * Conclusion:
 * (1) Tx DMA Buffer Address:
 *     1 bytes aligned: Invalid
 *     2 bytes aligned: O.K
 *     4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
 * (2) Rx DMA Buffer Address:
 *     1 bytes aligned: Invalid
 *     2 bytes aligned: O.K
 *     4 bytes aligned: Invalid
 */

struct ftmac110_chip {
	void __iomem *regs;
	uint32_t imr;
	uint32_t maccr;
	uint32_t lnkup;
	uint32_t phy_addr;

	struct ftmac110_rxd *rxd;
	ulong                rxd_dma;
	uint32_t             rxd_idx;

	struct ftmac110_txd *txd;
	ulong                txd_dma;
	uint32_t             txd_idx;
};

static int ftmac110_reset(struct eth_device *dev);

static uint16_t mdio_read(struct eth_device *dev,
	uint8_t phyaddr, uint8_t phyreg)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs __iomem *regs = chip->regs;
	uint32_t tmp, ts;
	uint16_t ret = 0xffff;

	tmp = PHYCR_READ
		| (phyaddr << PHYCR_ADDR_SHIFT)
		| (phyreg  << PHYCR_REG_SHIFT);

	writel(tmp, &regs->phycr);

	for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
		tmp = readl(&regs->phycr);
		if (tmp & PHYCR_READ)
			continue;
		break;
	}

	if (tmp & PHYCR_READ)
		printf("ftmac110: mdio read timeout\n");
	else
		ret = (uint16_t)(tmp & 0xffff);

	return ret;
}

static void mdio_write(struct eth_device *dev,
	uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs __iomem *regs = chip->regs;
	uint32_t tmp, ts;

	tmp = PHYCR_WRITE
		| (phyaddr << PHYCR_ADDR_SHIFT)
		| (phyreg  << PHYCR_REG_SHIFT);

	writel(phydata, &regs->phydr);
	writel(tmp, &regs->phycr);

	for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
		if (readl(&regs->phycr) & PHYCR_WRITE)
			continue;
		break;
	}

	if (readl(&regs->phycr) & PHYCR_WRITE)
		printf("ftmac110: mdio write timeout\n");
}

static uint32_t ftmac110_phyqry(struct eth_device *dev)
{
	ulong ts;
	uint32_t maccr;
	uint16_t pa, tmp, bmsr, bmcr;
	struct ftmac110_chip *chip = dev->priv;

	/* Default = 100Mbps Full */
	maccr = MACCR_100M | MACCR_FD;

	/* 1. find the phy device  */
	for (pa = 0; pa < 32; ++pa) {
		tmp = mdio_read(dev, pa, MII_PHYSID1);
		if (tmp == 0xFFFF || tmp == 0x0000)
			continue;
		chip->phy_addr = pa;
		break;
	}
	if (pa >= 32) {
		puts("ftmac110: phy device not found!\n");
		goto exit;
	}

	/* 2. wait until link-up & auto-negotiation complete */
	chip->lnkup = 0;
	bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
	ts = get_timer(0);
	do {
		bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
		chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
		if (!chip->lnkup)
			continue;
		if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
			break;
	} while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
	if (!chip->lnkup) {
		puts("ftmac110: link down\n");
		goto exit;
	}
	if (!(bmcr & BMCR_ANENABLE))
		puts("ftmac110: auto negotiation disabled\n");
	else if (!(bmsr & BMSR_ANEGCOMPLETE))
		puts("ftmac110: auto negotiation timeout\n");

	/* 3. derive MACCR */
	if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
		tmp  = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
		tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
		if (tmp & LPA_100FULL)      /* 100Mbps full-duplex */
			maccr = MACCR_100M | MACCR_FD;
		else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
			maccr = MACCR_100M;
		else if (tmp & LPA_10FULL)  /* 10Mbps full-duplex */
			maccr = MACCR_FD;
		else if (tmp & LPA_10HALF)  /* 10Mbps half-duplex */
			maccr = 0;
	} else {
		if (bmcr & BMCR_SPEED100)
			maccr = MACCR_100M;
		else
			maccr = 0;
		if (bmcr & BMCR_FULLDPLX)
			maccr |= MACCR_FD;
	}

exit:
	printf("ftmac110: %d Mbps, %s\n",
	       (maccr & MACCR_100M) ? 100 : 10,
	       (maccr & MACCR_FD) ? "Full" : "half");
	return maccr;
}

static int ftmac110_reset(struct eth_device *dev)
{
	uint8_t *a;
	uint32_t i, maccr;
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs __iomem *regs = chip->regs;

	/* 1. MAC reset */
	writel(MACCR_RESET, &regs->maccr);
	for (i = get_timer(0); get_timer(i) < 1000; ) {
		if (readl(&regs->maccr) & MACCR_RESET)
			continue;
		break;
	}
	if (readl(&regs->maccr) & MACCR_RESET) {
		printf("ftmac110: reset failed\n");
		return -ENXIO;
	}

	/* 1-1. Init tx ring */
	for (i = 0; i < CFG_TXDES_NUM; ++i) {
		/* owned by SW */
		chip->txd[i].ct[0] = 0;
	}
	chip->txd_idx = 0;

	/* 1-2. Init rx ring */
	for (i = 0; i < CFG_RXDES_NUM; ++i) {
		/* owned by HW */
		chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
	}
	chip->rxd_idx = 0;

	/* 2. PHY status query */
	maccr = ftmac110_phyqry(dev);

	/* 3. Fix up the MACCR value */
	chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
		| MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;

	/* 4. MAC address setup */
	a = dev->enetaddr;
	writel(a[1] | (a[0] << 8), &regs->mac[0]);
	writel(a[5] | (a[4] << 8) | (a[3] << 16)
		| (a[2] << 24), &regs->mac[1]);

	/* 5. MAC registers setup */
	writel(chip->rxd_dma, &regs->rxba);
	writel(chip->txd_dma, &regs->txba);
	/* interrupt at each tx/rx */
	writel(ITC_DEFAULT, &regs->itc);
	/* no tx pool, rx poll = 1 normal cycle */
	writel(APTC_DEFAULT, &regs->aptc);
	/* rx threshold = [6/8 fifo, 2/8 fifo] */
	writel(DBLAC_DEFAULT, &regs->dblac);
	/* disable & clear all interrupt status */
	chip->imr = 0;
	writel(ISR_ALL, &regs->isr);
	writel(chip->imr, &regs->imr);
	/* enable mac */
	writel(chip->maccr, &regs->maccr);

	return 0;
}

static int ftmac110_probe(struct eth_device *dev, bd_t *bis)
{
	debug("ftmac110: probe\n");

	if (ftmac110_reset(dev))
		return -1;

	return 0;
}

static void ftmac110_halt(struct eth_device *dev)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs __iomem *regs = chip->regs;

	writel(0, &regs->imr);
	writel(0, &regs->maccr);

	debug("ftmac110: halt\n");
}

static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs __iomem *regs = chip->regs;
	struct ftmac110_txd *des;

	if (!chip->lnkup)
		return 0;

	if (len <= 0 || len > CFG_XBUF_SIZE) {
		printf("ftmac110: bad tx pkt len(%d)\n", len);
		return 0;
	}

	len = max(60, len);

	des = &chip->txd[chip->txd_idx];
	if (le32_to_cpu(des->ct[0]) & FTMAC110_TXCT0_OWNER) {
		/* kick-off Tx DMA */
		writel(0xffffffff, &regs->txpd);
		printf("ftmac110: out of txd\n");
		return 0;
	}

	memcpy(des->vbuf, (void *)pkt, len);
	dma_map_single(des->vbuf, len, DMA_TO_DEVICE);

	/* update len, fts and lts */
	des->ct[1] &= cpu_to_le32(FTMAC110_TXCT1_END);
	des->ct[1] |= cpu_to_le32(FTMAC110_TXCT1_LEN(len)
		| FTMAC110_TXCT1_FTS | FTMAC110_TXCT1_LTS);

	/* set owner bit and clear others */
	des->ct[0] = cpu_to_le32(FTMAC110_TXCT0_OWNER);

	/* kick-off Tx DMA */
	writel(0xffffffff, &regs->txpd);

	chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;

	return len;
}

static int ftmac110_recv(struct eth_device *dev)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_rxd *des;
	uint32_t ct0, len, rlen = 0;
	uint8_t *buf;

	if (!chip->lnkup)
		return 0;

	do {
		des = &chip->rxd[chip->rxd_idx];
		ct0 = le32_to_cpu(des->ct[0]);
		if (ct0 & FTMAC110_RXCT0_OWNER)
			break;

		len = FTMAC110_RXCT0_LEN(ct0);
		buf = des->vbuf;

		if (ct0 & FTMAC110_RXCT0_ERRMASK) {
			printf("ftmac110: rx error\n");
		} else {
			dma_map_single(buf, len, DMA_FROM_DEVICE);
			NetReceive(buf, len);
			rlen += len;
		}

		/* owned by hardware */
		des->ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);

		chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
	} while (0);

	return rlen;
}

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)

static int ftmac110_mdio_read(
	const char *devname, uint8_t addr, uint8_t reg, uint16_t *value)
{
	int ret = 0;
	struct eth_device *dev;

	dev = eth_get_dev_by_name(devname);
	if (dev == NULL) {
		printf("%s: no such device\n", devname);
		ret = -1;
	} else {
		*value = mdio_read(dev, addr, reg);
	}

	return ret;
}

static int ftmac110_mdio_write(
	const char *devname, uint8_t addr, uint8_t reg, uint16_t value)
{
	int ret = 0;
	struct eth_device *dev;

	dev = eth_get_dev_by_name(devname);
	if (dev == NULL) {
		printf("%s: no such device\n", devname);
		ret = -1;
	} else {
		mdio_write(dev, addr, reg, value);
	}

	return ret;
}

#endif    /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */

int ftmac110_initialize(bd_t *bis)
{
	int i, card_nr = 0;
	struct eth_device *dev;
	struct ftmac110_chip *chip;

	dev = malloc(sizeof(*dev) + sizeof(*chip));
	if (dev == NULL) {
		panic("ftmac110: out of memory 1\n");
		return -1;
	}
	chip = (struct ftmac110_chip *)(dev + 1);
	memset(dev, 0, sizeof(*dev) + sizeof(*chip));

	sprintf(dev->name, "FTMAC110#%d", card_nr);

	dev->iobase = CONFIG_FTMAC110_BASE;
	chip->regs = (void __iomem *)dev->iobase;
	dev->priv = chip;
	dev->init = ftmac110_probe;
	dev->halt = ftmac110_halt;
	dev->send = ftmac110_send;
	dev->recv = ftmac110_recv;

	if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr))
		eth_random_enetaddr(dev->enetaddr);

	/* allocate tx descriptors (it must be 16 bytes aligned) */
	chip->txd = dma_alloc_coherent(
		sizeof(struct ftmac110_txd) * CFG_TXDES_NUM, &chip->txd_dma);
	if (!chip->txd)
		panic("ftmac110: out of memory 3\n");
	memset(chip->txd, 0,
	       sizeof(struct ftmac110_txd) * CFG_TXDES_NUM);
	for (i = 0; i < CFG_TXDES_NUM; ++i) {
		void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
		if (!va)
			panic("ftmac110: out of memory 4\n");
		chip->txd[i].vbuf  = va;
		chip->txd[i].buf   = cpu_to_le32(virt_to_phys(va));
		chip->txd[i].ct[1] = 0;
		chip->txd[i].ct[0] = 0; /* owned by SW */
	}
	chip->txd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_TXCT1_END);
	chip->txd_idx = 0;

	/* allocate rx descriptors (it must be 16 bytes aligned) */
	chip->rxd = dma_alloc_coherent(
		sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM, &chip->rxd_dma);
	if (!chip->rxd)
		panic("ftmac110: out of memory 4\n");
	memset((void *)chip->rxd, 0,
	       sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM);
	for (i = 0; i < CFG_RXDES_NUM; ++i) {
		void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
		if (!va)
			panic("ftmac110: out of memory 5\n");
		/* it needs to be exactly 2 bytes aligned */
		va = ((uint8_t *)va + 2);
		chip->rxd[i].vbuf  = va;
		chip->rxd[i].buf   = cpu_to_le32(virt_to_phys(va));
		chip->rxd[i].ct[1] = cpu_to_le32(CFG_XBUF_SIZE);
		chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
	}
	chip->rxd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_RXCT1_END);
	chip->rxd_idx = 0;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write);
#endif

	card_nr++;

	return card_nr;
}
Commit	Line	Data
c4775476 KJS	1	/*
	2	* Faraday 10/100Mbps Ethernet Controller
	3	*
	4	* (C) Copyright 2010 Faraday Technology
	5	* Dante Su <dantesu@faraday-tech.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
c4775476 KJS	8	*/
	9
	10	#include <common.h>
	11	#include <command.h>
	12	#include <malloc.h>
	13	#include <net.h>
	14	#include <asm/errno.h>
	15	#include <asm/io.h>
	16	#include <asm/dma-mapping.h>
	17
	18	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	19	#include <miiphy.h>
	20	#endif
	21
	22	#include "ftmac110.h"
	23
	24	#define CFG_RXDES_NUM 8
	25	#define CFG_TXDES_NUM 2
	26	#define CFG_XBUF_SIZE 1536
	27
	28	#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
	29	#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
	30	#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
	31
	32	/*
	33	* FTMAC110 DMA design issue
	34	*
	35	* Its DMA engine has a weird restriction that its Rx DMA engine
	36	* accepts only 16-bits aligned address, 32-bits aligned is not
	37	* acceptable. However this restriction does not apply to Tx DMA.
	38	*
	39	* Conclusion:
	40	* (1) Tx DMA Buffer Address:
	41	* 1 bytes aligned: Invalid
	42	* 2 bytes aligned: O.K
	43	* 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
	44	* (2) Rx DMA Buffer Address:
	45	* 1 bytes aligned: Invalid
	46	* 2 bytes aligned: O.K
	47	* 4 bytes aligned: Invalid
	48	*/
	49
	50	struct ftmac110_chip {
	51	void __iomem *regs;
	52	uint32_t imr;
	53	uint32_t maccr;
	54	uint32_t lnkup;
	55	uint32_t phy_addr;
	56
	57	struct ftmac110_rxd *rxd;
	58	ulong rxd_dma;
	59	uint32_t rxd_idx;
	60
	61	struct ftmac110_txd *txd;
	62	ulong txd_dma;
	63	uint32_t txd_idx;
	64	};
	65
	66	static int ftmac110_reset(struct eth_device *dev);
	67
	68	static uint16_t mdio_read(struct eth_device *dev,
	69	uint8_t phyaddr, uint8_t phyreg)
	70	{
	71	struct ftmac110_chip *chip = dev->priv;
72	struct ftmac110_regs __iomem *regs = chip->regs;
73	uint32_t tmp, ts;
74	uint16_t ret = 0xffff;
75
76	tmp = PHYCR_READ
77	\| (phyaddr << PHYCR_ADDR_SHIFT)
78	\| (phyreg << PHYCR_REG_SHIFT);
79
80	writel(tmp, &regs->phycr);
81
82	for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
83	tmp = readl(&regs->phycr);
84	if (tmp & PHYCR_READ)
85	continue;
86	break;
87	}
88
89	if (tmp & PHYCR_READ)
90	printf("ftmac110: mdio read timeout\n");
91	else
92	ret = (uint16_t)(tmp & 0xffff);
93
94	return ret;
95	}
96
97	static void mdio_write(struct eth_device *dev,
98	uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
99	{
100	struct ftmac110_chip *chip = dev->priv;
101	struct ftmac110_regs __iomem *regs = chip->regs;
102	uint32_t tmp, ts;
103
104	tmp = PHYCR_WRITE
105	\| (phyaddr << PHYCR_ADDR_SHIFT)
106	\| (phyreg << PHYCR_REG_SHIFT);
107
108	writel(phydata, &regs->phydr);
109	writel(tmp, &regs->phycr);
110
111	for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
112	if (readl(&regs->phycr) & PHYCR_WRITE)
113	continue;
114	break;
115	}
116
117	if (readl(&regs->phycr) & PHYCR_WRITE)
118	printf("ftmac110: mdio write timeout\n");
119	}
120
121	static uint32_t ftmac110_phyqry(struct eth_device *dev)
122	{
123	ulong ts;
124	uint32_t maccr;
125	uint16_t pa, tmp, bmsr, bmcr;
126	struct ftmac110_chip *chip = dev->priv;
127
128	/* Default = 100Mbps Full */
129	maccr = MACCR_100M \| MACCR_FD;
130
131	/* 1. find the phy device */
132	for (pa = 0; pa < 32; ++pa) {
133	tmp = mdio_read(dev, pa, MII_PHYSID1);
134	if (tmp == 0xFFFF \|\| tmp == 0x0000)
135	continue;
136	chip->phy_addr = pa;
137	break;
138	}
139	if (pa >= 32) {
140	puts("ftmac110: phy device not found!\n");
141	goto exit;
142	}
143
144	/* 2. wait until link-up & auto-negotiation complete */
145	chip->lnkup = 0;
146	bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
147	ts = get_timer(0);
148	do {
149	bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
150	chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
151	if (!chip->lnkup)
152	continue;
153	if (!(bmcr & BMCR_ANENABLE) \|\| (bmsr & BMSR_ANEGCOMPLETE))
154	break;
155	} while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
156	if (!chip->lnkup) {
157	puts("ftmac110: link down\n");
158	goto exit;
159	}
160	if (!(bmcr & BMCR_ANENABLE))
161	puts("ftmac110: auto negotiation disabled\n");
162	else if (!(bmsr & BMSR_ANEGCOMPLETE))
163	puts("ftmac110: auto negotiation timeout\n");
164
165	/* 3. derive MACCR */
166	if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
167	tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
168	tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
169	if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
170	maccr = MACCR_100M \| MACCR_FD;
171	else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
172	maccr = MACCR_100M;
173	else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
174	maccr = MACCR_FD;
175	else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
176	maccr = 0;
177	} else {
178	if (bmcr & BMCR_SPEED100)
179	maccr = MACCR_100M;
180	else
181	maccr = 0;
182	if (bmcr & BMCR_FULLDPLX)
183	maccr \|= MACCR_FD;
184	}
185
186	exit:
187	printf("ftmac110: %d Mbps, %s\n",
188	(maccr & MACCR_100M) ? 100 : 10,
189	(maccr & MACCR_FD) ? "Full" : "half");
190	return maccr;
191	}
192
193	static int ftmac110_reset(struct eth_device *dev)
194	{
195	uint8_t *a;
196	uint32_t i, maccr;
197	struct ftmac110_chip *chip = dev->priv;
198	struct ftmac110_regs __iomem *regs = chip->regs;
199
200	/* 1. MAC reset */
201	writel(MACCR_RESET, &regs->maccr);
202	for (i = get_timer(0); get_timer(i) < 1000; ) {
203	if (readl(&regs->maccr) & MACCR_RESET)
204	continue;
205	break;
206	}
207	if (readl(&regs->maccr) & MACCR_RESET) {
208	printf("ftmac110: reset failed\n");
209	return -ENXIO;
210	}
211
212	/* 1-1. Init tx ring */
213	for (i = 0; i < CFG_TXDES_NUM; ++i) {
214	/* owned by SW */
215	chip->txd[i].ct[0] = 0;
216	}
217	chip->txd_idx = 0;
218
219	/* 1-2. Init rx ring */
220	for (i = 0; i < CFG_RXDES_NUM; ++i) {
221	/* owned by HW */
222	chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
223	}
224	chip->rxd_idx = 0;
225
226	/* 2. PHY status query */
227	maccr = ftmac110_phyqry(dev);
228
229	/* 3. Fix up the MACCR value */
230	chip->maccr = maccr \| MACCR_CRCAPD \| MACCR_RXALL \| MACCR_RXRUNT
231	\| MACCR_RXEN \| MACCR_TXEN \| MACCR_RXDMAEN \| MACCR_TXDMAEN;
232
233	/* 4. MAC address setup */
234	a = dev->enetaddr;
235	writel(a[1] \| (a[0] << 8), &regs->mac[0]);
236	writel(a[5] \| (a[4] << 8) \| (a[3] << 16)
237	\| (a[2] << 24), &regs->mac[1]);
238
239	/* 5. MAC registers setup */
240	writel(chip->rxd_dma, &regs->rxba);
241	writel(chip->txd_dma, &regs->txba);
242	/* interrupt at each tx/rx */
243	writel(ITC_DEFAULT, &regs->itc);
244	/* no tx pool, rx poll = 1 normal cycle */
245	writel(APTC_DEFAULT, &regs->aptc);
246	/* rx threshold = [6/8 fifo, 2/8 fifo] */
247	writel(DBLAC_DEFAULT, &regs->dblac);
248	/* disable & clear all interrupt status */
249	chip->imr = 0;
250	writel(ISR_ALL, &regs->isr);
251	writel(chip->imr, &regs->imr);
252	/* enable mac */
253	writel(chip->maccr, &regs->maccr);
254
255	return 0;
256	}
257
258	static int ftmac110_probe(struct eth_device dev, bd_t bis)
259	{
260	debug("ftmac110: probe\n");
261
262	if (ftmac110_reset(dev))
263	return -1;
264
265	return 0;
266	}
267
268	static void ftmac110_halt(struct eth_device *dev)
269	{
270	struct ftmac110_chip *chip = dev->priv;
271	struct ftmac110_regs __iomem *regs = chip->regs;
272
273	writel(0, &regs->imr);
274	writel(0, &regs->maccr);
275
276	debug("ftmac110: halt\n");
277	}
278
279	static int ftmac110_send(struct eth_device dev, void pkt, int len)
280	{
281	struct ftmac110_chip *chip = dev->priv;
282	struct ftmac110_regs __iomem *regs = chip->regs;
283	struct ftmac110_txd *des;
284
285	if (!chip->lnkup)
286	return 0;
287
288	if (len <= 0 \|\| len > CFG_XBUF_SIZE) {
289	printf("ftmac110: bad tx pkt len(%d)\n", len);
290	return 0;
291	}
292
293	len = max(60, len);
294
295	des = &chip->txd[chip->txd_idx];
296	if (le32_to_cpu(des->ct[0]) & FTMAC110_TXCT0_OWNER) {
297	/* kick-off Tx DMA */
298	writel(0xffffffff, &regs->txpd);
299	printf("ftmac110: out of txd\n");
300	return 0;
301	}
302
303	memcpy(des->vbuf, (void *)pkt, len);
304	dma_map_single(des->vbuf, len, DMA_TO_DEVICE);
305
306	/* update len, fts and lts */
307	des->ct[1] &= cpu_to_le32(FTMAC110_TXCT1_END);
308	des->ct[1] \|= cpu_to_le32(FTMAC110_TXCT1_LEN(len)
309	\| FTMAC110_TXCT1_FTS \| FTMAC110_TXCT1_LTS);
310
311	/* set owner bit and clear others */
312	des->ct[0] = cpu_to_le32(FTMAC110_TXCT0_OWNER);
313
314	/* kick-off Tx DMA */
315	writel(0xffffffff, &regs->txpd);
316
317	chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
318
319	return len;
320	}
321
322	static int ftmac110_recv(struct eth_device *dev)
323	{
324	struct ftmac110_chip *chip = dev->priv;
325	struct ftmac110_rxd *des;
326	uint32_t ct0, len, rlen = 0;
327	uint8_t *buf;
328
329	if (!chip->lnkup)
330	return 0;
331
332	do {
333	des = &chip->rxd[chip->rxd_idx];
334	ct0 = le32_to_cpu(des->ct[0]);
335	if (ct0 & FTMAC110_RXCT0_OWNER)
336	break;
337
338	len = FTMAC110_RXCT0_LEN(ct0);
339	buf = des->vbuf;
340
341	if (ct0 & FTMAC110_RXCT0_ERRMASK) {
342	printf("ftmac110: rx error\n");
343	} else {
344	dma_map_single(buf, len, DMA_FROM_DEVICE);
345	NetReceive(buf, len);
346	rlen += len;
347	}
348
349	/* owned by hardware */
350	des->ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
351
352	chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
353	} while (0);
354
355	return rlen;
356	}
357
358	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
359
360	static int ftmac110_mdio_read(
361	const char devname, uint8_t addr, uint8_t reg, uint16_t value)
362	{
363	int ret = 0;
364	struct eth_device *dev;
365
366	dev = eth_get_dev_by_name(devname);
367	if (dev == NULL) {
368	printf("%s: no such device\n", devname);
369	ret = -1;
370	} else {
371	*value = mdio_read(dev, addr, reg);
372	}
373
374	return ret;
375	}
376
377	static int ftmac110_mdio_write(
378	const char *devname, uint8_t addr, uint8_t reg, uint16_t value)
379	{
380	int ret = 0;
381	struct eth_device *dev;
382
383	dev = eth_get_dev_by_name(devname);
384	if (dev == NULL) {
385	printf("%s: no such device\n", devname);
386	ret = -1;
387	} else {
388	mdio_write(dev, addr, reg, value);
389	}
390
391	return ret;
392	}
393
394	#endif /* #if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) */
395
396	int ftmac110_initialize(bd_t *bis)
397	{
398	int i, card_nr = 0;
399	struct eth_device *dev;
400	struct ftmac110_chip *chip;
401
402	dev = malloc(sizeof(dev) + sizeof(chip));
403	if (dev == NULL) {
404	panic("ftmac110: out of memory 1\n");
405	return -1;
406	}
407	chip = (struct ftmac110_chip *)(dev + 1);
408	memset(dev, 0, sizeof(dev) + sizeof(chip));
409
410	sprintf(dev->name, "FTMAC110#%d", card_nr);
411
412	dev->iobase = CONFIG_FTMAC110_BASE;
413	chip->regs = (void __iomem *)dev->iobase;
414	dev->priv = chip;
415	dev->init = ftmac110_probe;
416	dev->halt = ftmac110_halt;
417	dev->send = ftmac110_send;
418	dev->recv = ftmac110_recv;
419
420	if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr))
421	eth_random_enetaddr(dev->enetaddr);
422
423	/* allocate tx descriptors (it must be 16 bytes aligned) */
424	chip->txd = dma_alloc_coherent(
425	sizeof(struct ftmac110_txd) * CFG_TXDES_NUM, &chip->txd_dma);
426	if (!chip->txd)
427	panic("ftmac110: out of memory 3\n");
428	memset(chip->txd, 0,
429	sizeof(struct ftmac110_txd) * CFG_TXDES_NUM);
430	for (i = 0; i < CFG_TXDES_NUM; ++i) {
431	void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
432	if (!va)
433	panic("ftmac110: out of memory 4\n");
434	chip->txd[i].vbuf = va;
435	chip->txd[i].buf = cpu_to_le32(virt_to_phys(va));
436	chip->txd[i].ct[1] = 0;
437	chip->txd[i].ct[0] = 0; /* owned by SW */
438	}
439	chip->txd[i - 1].ct[1] \|= cpu_to_le32(FTMAC110_TXCT1_END);
440	chip->txd_idx = 0;
441
442	/* allocate rx descriptors (it must be 16 bytes aligned) */
443	chip->rxd = dma_alloc_coherent(
444	sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM, &chip->rxd_dma);
445	if (!chip->rxd)
446	panic("ftmac110: out of memory 4\n");
447	memset((void *)chip->rxd, 0,
448	sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM);
449	for (i = 0; i < CFG_RXDES_NUM; ++i) {
450	void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
451	if (!va)
452	panic("ftmac110: out of memory 5\n");
453	/* it needs to be exactly 2 bytes aligned */
454	va = ((uint8_t *)va + 2);
455	chip->rxd[i].vbuf = va;
456	chip->rxd[i].buf = cpu_to_le32(virt_to_phys(va));
457	chip->rxd[i].ct[1] = cpu_to_le32(CFG_XBUF_SIZE);
458	chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
459	}
460	chip->rxd[i - 1].ct[1] \|= cpu_to_le32(FTMAC110_RXCT1_END);
461	chip->rxd_idx = 0;
462
463	eth_register(dev);
464
465	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
466	miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write);
467	#endif
468
469	card_nr++;
470
471	return card_nr;
472	}