[people/ms/u-boot.git] / drivers / net / gmac_rockchip.c

/*
 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Rockchip GMAC ethernet IP driver for U-Boot
 */

#include <common.h>
#include <dm.h>
#include <clk.h>
#include <phy.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/periph.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rk3288.h>
#include <asm/arch/grf_rk3368.h>
#include <asm/arch/grf_rk3399.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"

DECLARE_GLOBAL_DATA_PTR;

/*
 * Platform data for the gmac
 *
 * dw_eth_pdata: Required platform data for designware driver (must be first)
 */
struct gmac_rockchip_platdata {
	struct dw_eth_pdata dw_eth_pdata;
	int tx_delay;
	int rx_delay;
};

struct rk_gmac_ops {
	int (*fix_mac_speed)(struct dw_eth_dev *priv);
	void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
};


static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
{
	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);

	/* Check the new naming-style first... */
	pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
	pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);

	/* ... and fall back to the old naming style or default, if necessary */
	if (pdata->tx_delay == -ENOENT)
		pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
	if (pdata->rx_delay == -ENOENT)
		pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);

	return designware_eth_ofdata_to_platdata(dev);
}

static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
	struct rk3288_grf *grf;
	int clk;

	switch (priv->phydev->speed) {
	case 10:
		clk = RK3288_GMAC_CLK_SEL_2_5M;
		break;
	case 100:
		clk = RK3288_GMAC_CLK_SEL_25M;
		break;
	case 1000:
		clk = RK3288_GMAC_CLK_SEL_125M;
		break;
	default:
		debug("Unknown phy speed: %d\n", priv->phydev->speed);
		return -EINVAL;
	}

	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);

	return 0;
}

static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
	struct rk3368_grf *grf;
	int clk;
	enum {
		RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
		RK3368_GMAC_CLK_SEL_25M = 3 << 4,
		RK3368_GMAC_CLK_SEL_125M = 0 << 4,
		RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
	};

	switch (priv->phydev->speed) {
	case 10:
		clk = RK3368_GMAC_CLK_SEL_2_5M;
		break;
	case 100:
		clk = RK3368_GMAC_CLK_SEL_25M;
		break;
	case 1000:
		clk = RK3368_GMAC_CLK_SEL_125M;
		break;
	default:
		debug("Unknown phy speed: %d\n", priv->phydev->speed);
		return -EINVAL;
	}

	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);

	return 0;
}

static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
	struct rk3399_grf_regs *grf;
	int clk;

	switch (priv->phydev->speed) {
	case 10:
		clk = RK3399_GMAC_CLK_SEL_2_5M;
		break;
	case 100:
		clk = RK3399_GMAC_CLK_SEL_25M;
		break;
	case 1000:
		clk = RK3399_GMAC_CLK_SEL_125M;
		break;
	default:
		debug("Unknown phy speed: %d\n", priv->phydev->speed);
		return -EINVAL;
	}

	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);

	return 0;
}

static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
	struct rk3288_grf *grf;

	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	rk_clrsetreg(&grf->soc_con1,
		     RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,
		     RK3288_GMAC_PHY_INTF_SEL_RGMII);

	rk_clrsetreg(&grf->soc_con3,
		     RK3288_RXCLK_DLY_ENA_GMAC_MASK |
		     RK3288_TXCLK_DLY_ENA_GMAC_MASK |
		     RK3288_CLK_RX_DL_CFG_GMAC_MASK |
		     RK3288_CLK_TX_DL_CFG_GMAC_MASK,
		     RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
		     RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
		     pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}

static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
	struct rk3368_grf *grf;
	enum {
		RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
		RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
		RK3368_RMII_MODE_MASK  = BIT(6),
		RK3368_RMII_MODE       = BIT(6),
	};
	enum {
		RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
		RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
		RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
		RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
		RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
		RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
		RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
		RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
		RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
		RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
	};

	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	rk_clrsetreg(&grf->soc_con15,
		     RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
		     RK3368_GMAC_PHY_INTF_SEL_RGMII);

	rk_clrsetreg(&grf->soc_con16,
		     RK3368_RXCLK_DLY_ENA_GMAC_MASK |
		     RK3368_TXCLK_DLY_ENA_GMAC_MASK |
		     RK3368_CLK_RX_DL_CFG_GMAC_MASK |
		     RK3368_CLK_TX_DL_CFG_GMAC_MASK,
		     RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
		     RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
		     pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
		     pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
}

static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
	struct rk3399_grf_regs *grf;

	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);

	rk_clrsetreg(&grf->soc_con5,
		     RK3399_GMAC_PHY_INTF_SEL_MASK,
		     RK3399_GMAC_PHY_INTF_SEL_RGMII);

	rk_clrsetreg(&grf->soc_con6,
		     RK3399_RXCLK_DLY_ENA_GMAC_MASK |
		     RK3399_TXCLK_DLY_ENA_GMAC_MASK |
		     RK3399_CLK_RX_DL_CFG_GMAC_MASK |
		     RK3399_CLK_TX_DL_CFG_GMAC_MASK,
		     RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
		     RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
		     pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
		     pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}

static int gmac_rockchip_probe(struct udevice *dev)
{
	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
	struct rk_gmac_ops *ops =
		(struct rk_gmac_ops *)dev_get_driver_data(dev);
	struct clk clk;
	int ret;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret)
		return ret;

	/* Since mac_clk is fed by an external clock we can use 0 here */
	ret = clk_set_rate(&clk, 0);
	if (ret)
		return ret;

	/* Set to RGMII mode */
	ops->set_to_rgmii(pdata);

	return designware_eth_probe(dev);
}

static int gmac_rockchip_eth_start(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct dw_eth_dev *priv = dev_get_priv(dev);
	struct rk_gmac_ops *ops =
		(struct rk_gmac_ops *)dev_get_driver_data(dev);
	int ret;

	ret = designware_eth_init(priv, pdata->enetaddr);
	if (ret)
		return ret;
	ret = ops->fix_mac_speed(priv);
	if (ret)
		return ret;
	ret = designware_eth_enable(priv);
	if (ret)
		return ret;

	return 0;
}

const struct eth_ops gmac_rockchip_eth_ops = {
	.start			= gmac_rockchip_eth_start,
	.send			= designware_eth_send,
	.recv			= designware_eth_recv,
	.free_pkt		= designware_eth_free_pkt,
	.stop			= designware_eth_stop,
	.write_hwaddr		= designware_eth_write_hwaddr,
};

const struct rk_gmac_ops rk3288_gmac_ops = {
	.fix_mac_speed = rk3288_gmac_fix_mac_speed,
	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
};

const struct rk_gmac_ops rk3368_gmac_ops = {
	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
};

const struct rk_gmac_ops rk3399_gmac_ops = {
	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
};

static const struct udevice_id rockchip_gmac_ids[] = {
	{ .compatible = "rockchip,rk3288-gmac",
	  .data = (ulong)&rk3288_gmac_ops },
	{ .compatible = "rockchip,rk3368-gmac",
	  .data = (ulong)&rk3368_gmac_ops },
	{ .compatible = "rockchip,rk3399-gmac",
	  .data = (ulong)&rk3399_gmac_ops },
	{ }
};

U_BOOT_DRIVER(eth_gmac_rockchip) = {
	.name	= "gmac_rockchip",
	.id	= UCLASS_ETH,
	.of_match = rockchip_gmac_ids,
	.ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
	.probe	= gmac_rockchip_probe,
	.ops	= &gmac_rockchip_eth_ops,
	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
	.platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
0125bcf0 SS	1	/*
	2	* (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*
	6	* Rockchip GMAC ethernet IP driver for U-Boot
	7	*/
	8
	9	#include <common.h>
	10	#include <dm.h>
	11	#include <clk.h>
	12	#include <phy.h>
	13	#include <syscon.h>
	14	#include <asm/io.h>
	15	#include <asm/arch/periph.h>
	16	#include <asm/arch/clock.h>
1f08aa1c	17	#include <asm/arch/hardware.h>
0125bcf0	18	#include <asm/arch/grf_rk3288.h>
793f2fd2	19	#include <asm/arch/grf_rk3368.h>
1f08aa1c	20	#include <asm/arch/grf_rk3399.h>
0125bcf0 SS	21	#include <dm/pinctrl.h>
	22	#include <dt-bindings/clock/rk3288-cru.h>
	23	#include "designware.h"
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	/*
	28	* Platform data for the gmac
	29	*
	30	* dw_eth_pdata: Required platform data for designware driver (must be first)
	31	*/
	32	struct gmac_rockchip_platdata {
	33	struct dw_eth_pdata dw_eth_pdata;
	34	int tx_delay;
	35	int rx_delay;
	36	};
	37
1f08aa1c PT	38	struct rk_gmac_ops {
	39	int (fix_mac_speed)(struct dw_eth_dev priv);
	40	void (set_to_rgmii)(struct gmac_rockchip_platdata pdata);
	41	};
	42
	43
0125bcf0 SS	44	static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
	45	{
	46	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
1f08aa1c PT	47
1f08aa1c PT	48	/* Check the new naming-style first... */
7ad326a9 PT	49	pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
7ad326a9 PT	50	pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
0125bcf0	51
1f08aa1c PT	52	/* ... and fall back to the old naming style or default, if necessary */
1f08aa1c PT	53	if (pdata->tx_delay == -ENOENT)
7ad326a9	54	pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
1f08aa1c	55	if (pdata->rx_delay == -ENOENT)
7ad326a9	56	pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
0125bcf0 SS	57
	58	return designware_eth_ofdata_to_platdata(dev);
	59	}
	60
1f08aa1c	61	static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
0125bcf0 SS	62	{
	63	struct rk3288_grf *grf;
	64	int clk;
	65
	66	switch (priv->phydev->speed) {
	67	case 10:
1f08aa1c	68	clk = RK3288_GMAC_CLK_SEL_2_5M;
0125bcf0 SS	69	break;
0125bcf0 SS	70	case 100:
1f08aa1c	71	clk = RK3288_GMAC_CLK_SEL_25M;
0125bcf0 SS	72	break;
0125bcf0 SS	73	case 1000:
1f08aa1c	74	clk = RK3288_GMAC_CLK_SEL_125M;
0125bcf0 SS	75	break;
	76	default:
	77	debug("Unknown phy speed: %d\n", priv->phydev->speed);
	78	return -EINVAL;
	79	}
	80
	81	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1f08aa1c PT	82	rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);
	83
	84	return 0;
	85	}
	86
793f2fd2 PT	87	static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
	88	{
	89	struct rk3368_grf *grf;
	90	int clk;
	91	enum {
	92	RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
	93	RK3368_GMAC_CLK_SEL_25M = 3 << 4,
	94	RK3368_GMAC_CLK_SEL_125M = 0 << 4,
	95	RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
	96	};
	97
	98	switch (priv->phydev->speed) {
	99	case 10:
	100	clk = RK3368_GMAC_CLK_SEL_2_5M;
	101	break;
	102	case 100:
	103	clk = RK3368_GMAC_CLK_SEL_25M;
	104	break;
	105	case 1000:
	106	clk = RK3368_GMAC_CLK_SEL_125M;
	107	break;
	108	default:
	109	debug("Unknown phy speed: %d\n", priv->phydev->speed);
	110	return -EINVAL;
	111	}
	112
	113	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	114	rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
	115
	116	return 0;
	117	}
	118
1f08aa1c PT	119	static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
	120	{
	121	struct rk3399_grf_regs *grf;
	122	int clk;
	123
	124	switch (priv->phydev->speed) {
	125	case 10:
	126	clk = RK3399_GMAC_CLK_SEL_2_5M;
	127	break;
	128	case 100:
	129	clk = RK3399_GMAC_CLK_SEL_25M;
	130	break;
	131	case 1000:
	132	clk = RK3399_GMAC_CLK_SEL_125M;
	133	break;
	134	default:
	135	debug("Unknown phy speed: %d\n", priv->phydev->speed);
	136	return -EINVAL;
	137	}
	138
	139	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	140	rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
0125bcf0 SS	141
	142	return 0;
	143	}
	144
1f08aa1c PT	145	static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	146	{
	147	struct rk3288_grf *grf;
	148
	149	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	150	rk_clrsetreg(&grf->soc_con1,
	151	RK3288_RMII_MODE_MASK \| RK3288_GMAC_PHY_INTF_SEL_MASK,
	152	RK3288_GMAC_PHY_INTF_SEL_RGMII);
	153
	154	rk_clrsetreg(&grf->soc_con3,
	155	RK3288_RXCLK_DLY_ENA_GMAC_MASK \|
	156	RK3288_TXCLK_DLY_ENA_GMAC_MASK \|
	157	RK3288_CLK_RX_DL_CFG_GMAC_MASK \|
	158	RK3288_CLK_TX_DL_CFG_GMAC_MASK,
	159	RK3288_RXCLK_DLY_ENA_GMAC_ENABLE \|
	160	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE \|
	161	pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT \|
	162	pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
	163	}
	164
793f2fd2 PT	165	static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	166	{
	167	struct rk3368_grf *grf;
	168	enum {
	169	RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
	170	RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
	171	RK3368_RMII_MODE_MASK = BIT(6),
	172	RK3368_RMII_MODE = BIT(6),
	173	};
	174	enum {
	175	RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
	176	RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
	177	RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
	178	RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
	179	RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
	180	RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
	181	RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
	182	RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
	183	RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
	184	RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
	185	};
	186
	187	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	188	rk_clrsetreg(&grf->soc_con15,
	189	RK3368_RMII_MODE_MASK \| RK3368_GMAC_PHY_INTF_SEL_MASK,
	190	RK3368_GMAC_PHY_INTF_SEL_RGMII);
	191
	192	rk_clrsetreg(&grf->soc_con16,
	193	RK3368_RXCLK_DLY_ENA_GMAC_MASK \|
	194	RK3368_TXCLK_DLY_ENA_GMAC_MASK \|
	195	RK3368_CLK_RX_DL_CFG_GMAC_MASK \|
	196	RK3368_CLK_TX_DL_CFG_GMAC_MASK,
	197	RK3368_RXCLK_DLY_ENA_GMAC_ENABLE \|
	198	RK3368_TXCLK_DLY_ENA_GMAC_ENABLE \|
	199	pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT \|
	200	pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
	201	}
	202
1f08aa1c PT	203	static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	204	{
	205	struct rk3399_grf_regs *grf;
	206
	207	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	208
	209	rk_clrsetreg(&grf->soc_con5,
	210	RK3399_GMAC_PHY_INTF_SEL_MASK,
	211	RK3399_GMAC_PHY_INTF_SEL_RGMII);
	212
	213	rk_clrsetreg(&grf->soc_con6,
	214	RK3399_RXCLK_DLY_ENA_GMAC_MASK \|
	215	RK3399_TXCLK_DLY_ENA_GMAC_MASK \|
	216	RK3399_CLK_RX_DL_CFG_GMAC_MASK \|
	217	RK3399_CLK_TX_DL_CFG_GMAC_MASK,
	218	RK3399_RXCLK_DLY_ENA_GMAC_ENABLE \|
	219	RK3399_TXCLK_DLY_ENA_GMAC_ENABLE \|
	220	pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT \|
	221	pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
	222	}
	223
0125bcf0 SS	224	static int gmac_rockchip_probe(struct udevice *dev)
	225	{
	226	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
1f08aa1c PT	227	struct rk_gmac_ops *ops =
1f08aa1c PT	228	(struct rk_gmac_ops *)dev_get_driver_data(dev);
0125bcf0 SS	229	struct clk clk;
	230	int ret;
	231
	232	ret = clk_get_by_index(dev, 0, &clk);
	233	if (ret)
	234	return ret;
	235
	236	/* Since mac_clk is fed by an external clock we can use 0 here */
	237	ret = clk_set_rate(&clk, 0);
	238	if (ret)
	239	return ret;
	240
	241	/* Set to RGMII mode */
1f08aa1c	242	ops->set_to_rgmii(pdata);
0125bcf0 SS	243
	244	return designware_eth_probe(dev);
	245	}
	246
	247	static int gmac_rockchip_eth_start(struct udevice *dev)
	248	{
	249	struct eth_pdata *pdata = dev_get_platdata(dev);
	250	struct dw_eth_dev *priv = dev_get_priv(dev);
1f08aa1c PT	251	struct rk_gmac_ops *ops =
1f08aa1c PT	252	(struct rk_gmac_ops *)dev_get_driver_data(dev);
0125bcf0 SS	253	int ret;
	254
	255	ret = designware_eth_init(priv, pdata->enetaddr);
	256	if (ret)
	257	return ret;
1f08aa1c	258	ret = ops->fix_mac_speed(priv);
0125bcf0 SS	259	if (ret)
	260	return ret;
	261	ret = designware_eth_enable(priv);
	262	if (ret)
	263	return ret;
	264
	265	return 0;
	266	}
	267
	268	const struct eth_ops gmac_rockchip_eth_ops = {
	269	.start = gmac_rockchip_eth_start,
	270	.send = designware_eth_send,
	271	.recv = designware_eth_recv,
	272	.free_pkt = designware_eth_free_pkt,
	273	.stop = designware_eth_stop,
	274	.write_hwaddr = designware_eth_write_hwaddr,
	275	};
	276
1f08aa1c PT	277	const struct rk_gmac_ops rk3288_gmac_ops = {
	278	.fix_mac_speed = rk3288_gmac_fix_mac_speed,
	279	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
	280	};
	281
793f2fd2 PT	282	const struct rk_gmac_ops rk3368_gmac_ops = {
	283	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
	284	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
	285	};
	286
1f08aa1c PT	287	const struct rk_gmac_ops rk3399_gmac_ops = {
	288	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
	289	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
	290	};
	291
0125bcf0	292	static const struct udevice_id rockchip_gmac_ids[] = {
1f08aa1c PT	293	{ .compatible = "rockchip,rk3288-gmac",
1f08aa1c PT	294	.data = (ulong)&rk3288_gmac_ops },
793f2fd2 PT	295	{ .compatible = "rockchip,rk3368-gmac",
793f2fd2 PT	296	.data = (ulong)&rk3368_gmac_ops },
1f08aa1c PT	297	{ .compatible = "rockchip,rk3399-gmac",
1f08aa1c PT	298	.data = (ulong)&rk3399_gmac_ops },
0125bcf0 SS	299	{ }
	300	};
	301
	302	U_BOOT_DRIVER(eth_gmac_rockchip) = {
	303	.name = "gmac_rockchip",
	304	.id = UCLASS_ETH,
	305	.of_match = rockchip_gmac_ids,
	306	.ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata,
	307	.probe = gmac_rockchip_probe,
	308	.ops = &gmac_rockchip_eth_ops,
	309	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
	310	.platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata),
	311	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	312	};