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dm: core: Replace of_offset with accessor
[people/ms/u-boot.git] / drivers / net / keystone_net.c
CommitLineData
fc9a8e8d
KM		 1/*
2 * Ethernet driver for TI K2HK EVM.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#include <common.h>
10#include <command.h>
24b852a7 11#include <console.h>
fc9a8e8d 12
6599f369 13#include <dm.h>
a61f6a55 14#include <dm/lists.h>
6599f369 15
fc9a8e8d 16#include <net.h>
3fe93623 17#include <phy.h>
c05d05e7 18#include <errno.h>
fc9a8e8d
KM		 19#include <miiphy.h>
20#include <malloc.h>
ef454717 21#include <asm/ti-common/keystone_nav.h>
0935cac6 22#include <asm/ti-common/keystone_net.h>
a43febde 23#include <asm/ti-common/keystone_serdes.h>
6599f369
M		 24#include <asm/arch/psc_defs.h>
25
26DECLARE_GLOBAL_DATA_PTR;
fc9a8e8d 27
6599f369 28#ifndef CONFIG_DM_ETH
fc9a8e8d 29unsigned int emac_open;
550c5ce6 30static struct mii_dev *mdio_bus;
fc9a8e8d 31static unsigned int sys_has_mdio = 1;
6599f369 32#endif
fc9a8e8d
KM		 33
34#ifdef KEYSTONE2_EMAC_GIG_ENABLE
35#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
36#else
37#define emac_gigabit_enable(x) /* no gigabit to enable */
38#endif
39
40#define RX_BUFF_NUMS 24
41#define RX_BUFF_LEN 1520
42#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
c05d05e7 43#define SGMII_ANEG_TIMEOUT 4000
fc9a8e8d
KM		 44
45static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
46
6599f369 47#ifndef CONFIG_DM_ETH
fc9a8e8d
KM		 48struct rx_buff_desc net_rx_buffs = {
49 .buff_ptr = rx_buffs,
50 .num_buffs = RX_BUFF_NUMS,
51 .buff_len = RX_BUFF_LEN,
52 .rx_flow = 22,
53};
4657a2d4 54#endif
fc9a8e8d 55
6599f369 56#ifdef CONFIG_DM_ETH
fc9a8e8d 57
6599f369 58enum link_type {
1de40662
M		 59 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
60 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
61 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
62 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
63 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
64 LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
65 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
66 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
67 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
68 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
6599f369 69};
fc9a8e8d 70
6599f369
M		 71#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
72 ((mac)[2] << 16) | ((mac)[3] << 24))
73#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
fc9a8e8d 74
6599f369 75#ifdef CONFIG_KSNET_NETCP_V1_0
fc9a8e8d 76
6599f369
M		 77#define EMAC_EMACSW_BASE_OFS 0x90800
78#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
79
80/* CPSW Switch slave registers */
81#define CPGMACSL_REG_SA_LO 0x10
82#define CPGMACSL_REG_SA_HI 0x14
83
84#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
85 (x) * 0x30)
86
87#elif defined CONFIG_KSNET_NETCP_V1_5
88
89#define EMAC_EMACSW_PORT_BASE_OFS 0x222000
90
91/* CPSW Switch slave registers */
92#define CPGMACSL_REG_SA_LO 0x308
93#define CPGMACSL_REG_SA_HI 0x30c
94
95#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
96 (x) * 0x1000)
97
98#endif
99
100
101struct ks2_eth_priv {
102 struct udevice *dev;
103 struct phy_device *phydev;
104 struct mii_dev *mdio_bus;
105 int phy_addr;
106 phy_interface_t phy_if;
107 int sgmii_link_type;
108 void *mdio_base;
109 struct rx_buff_desc net_rx_buffs;
110 struct pktdma_cfg *netcp_pktdma;
111 void *hd;
112 int slave_port;
113 enum link_type link_type;
114 bool emac_open;
115 bool has_mdio;
116};
117#endif
fc9a8e8d 118
550c5ce6
KI		 119/* MDIO */
120
121static int keystone2_mdio_reset(struct mii_dev *bus)
fc9a8e8d 122{
550c5ce6
KI		 123 u_int32_t clkdiv;
124 struct mdio_regs *adap_mdio = bus->priv;
fc9a8e8d
KM		 125
126 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
127
550c5ce6
KI		 128 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
129 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
fc9a8e8d
KM		 130 &adap_mdio->control);
131
132 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
133 ;
550c5ce6
KI		 134
135 return 0;
fc9a8e8d
KM		 136}
137
550c5ce6
KI		 138/**
139 * keystone2_mdio_read - read a PHY register via MDIO interface.
140 * Blocks until operation is complete.
141 */
142static int keystone2_mdio_read(struct mii_dev *bus,
143 int addr, int devad, int reg)
fc9a8e8d 144{
550c5ce6
KI		 145 int tmp;
146 struct mdio_regs *adap_mdio = bus->priv;
fc9a8e8d
KM		 147
148 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
149 ;
150
550c5ce6
KI		 151 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
152 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
fc9a8e8d
KM		 153 &adap_mdio->useraccess0);
154
155 /* Wait for command to complete */
156 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
157 ;
158
550c5ce6
KI		 159 if (tmp & MDIO_USERACCESS0_ACK)
160 return tmp & 0xffff;
fc9a8e8d 161
fc9a8e8d
KM		 162 return -1;
163}
164
550c5ce6
KI		 165/**
166 * keystone2_mdio_write - write to a PHY register via MDIO interface.
fc9a8e8d
KM		 167 * Blocks until operation is complete.
168 */
550c5ce6
KI		 169static int keystone2_mdio_write(struct mii_dev *bus,
170 int addr, int devad, int reg, u16 val)
fc9a8e8d 171{
550c5ce6
KI		 172 struct mdio_regs *adap_mdio = bus->priv;
173
fc9a8e8d
KM		 174 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
175 ;
176
550c5ce6
KI		 177 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
178 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
179 (val & 0xffff), &adap_mdio->useraccess0);
fc9a8e8d
KM		 180
181 /* Wait for command to complete */
182 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
183 ;
184
185 return 0;
186}
187
6599f369 188#ifndef CONFIG_DM_ETH
fc9a8e8d
KM		 189static void __attribute__((unused))
190 keystone2_eth_gigabit_enable(struct eth_device *dev)
191{
192 u_int16_t data;
193 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
194
195 if (sys_has_mdio) {
550c5ce6
KI		 196 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
197 MDIO_DEVAD_NONE, 0);
198 /* speed selection MSB */
199 if (!(data & (1 << 6)))
fc9a8e8d
KM		 200 return;
201 }
202
203 /*
204 * Check if link detected is giga-bit
205 * If Gigabit mode detected, enable gigbit in MAC
206 */
b2cfe322
HZ		 207 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
208 CPGMACSL_REG_CTL) |
fc9a8e8d 209 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
b2cfe322 210 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
fc9a8e8d 211}
6599f369
M		 212#else
213static void __attribute__((unused))
214 keystone2_eth_gigabit_enable(struct udevice *dev)
215{
216 struct ks2_eth_priv *priv = dev_get_priv(dev);
217 u_int16_t data;
218
219 if (priv->has_mdio) {
220 data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr,
221 MDIO_DEVAD_NONE, 0);
222 /* speed selection MSB */
223 if (!(data & (1 << 6)))
224 return;
225 }
226
227 /*
228 * Check if link detected is giga-bit
229 * If Gigabit mode detected, enable gigbit in MAC
230 */
231 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
232 CPGMACSL_REG_CTL) |
233 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
234 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
235}
236#endif
fc9a8e8d 237
4657a2d4
VA		 238#ifdef CONFIG_SOC_K2G
239int keystone_rgmii_config(struct phy_device *phy_dev)
240{
241 unsigned int i, status;
242
243 i = 0;
244 do {
245 if (i > SGMII_ANEG_TIMEOUT) {
246 puts(" TIMEOUT !\n");
247 phy_dev->link = 0;
248 return 0;
249 }
250
251 if (ctrlc()) {
252 puts("user interrupt!\n");
253 phy_dev->link = 0;
254 return -EINTR;
255 }
256
257 if ((i++ % 500) == 0)
258 printf(".");
259
260 udelay(1000); /* 1 ms */
261 status = readl(RGMII_STATUS_REG);
262 } while (!(status & RGMII_REG_STATUS_LINK));
263
264 puts(" done\n");
265
266 return 0;
267}
268#else
c05d05e7 269int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
fc9a8e8d
KM		 270{
271 unsigned int i, status, mask;
272 unsigned int mr_adv_ability, control;
273
274 switch (interface) {
275 case SGMII_LINK_MAC_MAC_AUTONEG:
276 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
277 SGMII_REG_MR_ADV_LINK |
278 SGMII_REG_MR_ADV_FULL_DUPLEX |
279 SGMII_REG_MR_ADV_GIG_MODE);
280 control = (SGMII_REG_CONTROL_MASTER |
281 SGMII_REG_CONTROL_AUTONEG);
282
283 break;
284 case SGMII_LINK_MAC_PHY:
285 case SGMII_LINK_MAC_PHY_FORCED:
286 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
287 control = SGMII_REG_CONTROL_AUTONEG;
288
289 break;
290 case SGMII_LINK_MAC_MAC_FORCED:
291 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
292 SGMII_REG_MR_ADV_LINK |
293 SGMII_REG_MR_ADV_FULL_DUPLEX |
294 SGMII_REG_MR_ADV_GIG_MODE);
295 control = SGMII_REG_CONTROL_MASTER;
296
297 break;
298 case SGMII_LINK_MAC_FIBER:
299 mr_adv_ability = 0x20;
300 control = SGMII_REG_CONTROL_AUTONEG;
301
302 break;
303 default:
304 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
305 control = SGMII_REG_CONTROL_AUTONEG;
306 }
307
308 __raw_writel(0, SGMII_CTL_REG(port));
309
310 /*
311 * Wait for the SerDes pll to lock,
312 * but don't trap if lock is never read
313 */
314 for (i = 0; i < 1000; i++) {
315 udelay(2000);
316 status = __raw_readl(SGMII_STATUS_REG(port));
317 if ((status & SGMII_REG_STATUS_LOCK) != 0)
318 break;
319 }
320
321 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
322 __raw_writel(control, SGMII_CTL_REG(port));
323
324
325 mask = SGMII_REG_STATUS_LINK;
326
327 if (control & SGMII_REG_CONTROL_AUTONEG)
328 mask |= SGMII_REG_STATUS_AUTONEG;
329
c05d05e7
KI		 330 status = __raw_readl(SGMII_STATUS_REG(port));
331 if ((status & mask) == mask)
332 return 0;
333
334 printf("\n%s Waiting for SGMII auto negotiation to complete",
335 phy_dev->dev->name);
336 while ((status & mask) != mask) {
337 /*
338 * Timeout reached ?
339 */
340 if (i > SGMII_ANEG_TIMEOUT) {
341 puts(" TIMEOUT !\n");
342 phy_dev->link = 0;
343 return 0;
344 }
345
346 if (ctrlc()) {
347 puts("user interrupt!\n");
348 phy_dev->link = 0;
349 return -EINTR;
350 }
351
352 if ((i++ % 500) == 0)
353 printf(".");
354
355 udelay(1000); /* 1 ms */
fc9a8e8d 356 status = __raw_readl(SGMII_STATUS_REG(port));
fc9a8e8d 357 }
c05d05e7 358 puts(" done\n");
fc9a8e8d
KM		 359
360 return 0;
361}
4657a2d4 362#endif
fc9a8e8d
KM		 363
364int mac_sl_reset(u32 port)
365{
366 u32 i, v;
367
368 if (port >= DEVICE_N_GMACSL_PORTS)
369 return GMACSL_RET_INVALID_PORT;
370
371 /* Set the soft reset bit */
e6c9428a
KI		 372 writel(CPGMAC_REG_RESET_VAL_RESET,
373 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d
KM		 374
375 /* Wait for the bit to clear */
376 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
e6c9428a 377 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d
KM		 378 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
379 CPGMAC_REG_RESET_VAL_RESET)
380 return GMACSL_RET_OK;
381 }
382
383 /* Timeout on the reset */
384 return GMACSL_RET_WARN_RESET_INCOMPLETE;
385}
386
387int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
388{
389 u32 v, i;
390 int ret = GMACSL_RET_OK;
391
392 if (port >= DEVICE_N_GMACSL_PORTS)
393 return GMACSL_RET_INVALID_PORT;
394
395 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
396 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
397 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
398 }
399
400 /* Must wait if the device is undergoing reset */
401 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
e6c9428a 402 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d
KM		 403 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
404 CPGMAC_REG_RESET_VAL_RESET)
405 break;
406 }
407
408 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
409 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
410
e6c9428a
KI		 411 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
412 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
fc9a8e8d 413
4657a2d4 414#ifndef CONFIG_SOC_K2HK
ff11c769
KI		 415 /* Map RX packet flow priority to 0 */
416 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
417#endif
418
fc9a8e8d
KM		 419 return ret;
420}
421
422int ethss_config(u32 ctl, u32 max_pkt_size)
423{
424 u32 i;
425
426 /* Max length register */
e6c9428a 427 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
fc9a8e8d
KM		 428
429 /* Control register */
e6c9428a 430 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
fc9a8e8d
KM		 431
432 /* All statistics enabled by default */
e6c9428a
KI		 433 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
434 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
fc9a8e8d
KM		 435
436 /* Reset and enable the ALE */
e6c9428a
KI		 437 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
438 CPSW_REG_VAL_ALE_CTL_BYPASS,
439 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
fc9a8e8d
KM		 440
441 /* All ports put into forward mode */
442 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
e6c9428a
KI		 443 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
444 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
fc9a8e8d
KM		 445
446 return 0;
447}
448
449int ethss_start(void)
450{
451 int i;
452 struct mac_sl_cfg cfg;
453
454 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
455 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
456
457 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
458 mac_sl_reset(i);
459 mac_sl_config(i, &cfg);
460 }
461
462 return 0;
463}
464
465int ethss_stop(void)
466{
467 int i;
468
469 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
470 mac_sl_reset(i);
471
472 return 0;
473}
474
6599f369
M		 475struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
476 .clk = SERDES_CLOCK_156P25M,
477 .rate = SERDES_RATE_5G,
478 .rate_mode = SERDES_QUARTER_RATE,
479 .intf = SERDES_PHY_SGMII,
480 .loopback = 0,
481};
482
483#ifndef CONFIG_SOC_K2G
484static void keystone2_net_serdes_setup(void)
485{
486 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
487 &ks2_serdes_sgmii_156p25mhz,
488 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
489
490#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
491 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
492 &ks2_serdes_sgmii_156p25mhz,
493 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
494#endif
495
496 /* wait till setup */
497 udelay(5000);
498}
499#endif
500
501#ifndef CONFIG_DM_ETH
502
503int keystone2_eth_read_mac_addr(struct eth_device *dev)
504{
505 struct eth_priv_t *eth_priv;
506 u32 maca = 0;
507 u32 macb = 0;
508
509 eth_priv = (struct eth_priv_t *)dev->priv;
510
511 /* Read the e-fuse mac address */
512 if (eth_priv->slave_port == 1) {
513 maca = __raw_readl(MAC_ID_BASE_ADDR);
514 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
515 }
516
517 dev->enetaddr[0] = (macb >> 8) & 0xff;
518 dev->enetaddr[1] = (macb >> 0) & 0xff;
519 dev->enetaddr[2] = (maca >> 24) & 0xff;
520 dev->enetaddr[3] = (maca >> 16) & 0xff;
521 dev->enetaddr[4] = (maca >> 8) & 0xff;
522 dev->enetaddr[5] = (maca >> 0) & 0xff;
523
524 return 0;
525}
526
fc9a8e8d
KM		 527int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
528{
529 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
530 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
531
9ea9021a
KI		 532 return ksnav_send(&netcp_pktdma, buffer,
533 num_bytes, (slave_port_num) << 16);
fc9a8e8d
KM		 534}
535
536/* Eth device open */
537static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
538{
fc9a8e8d 539 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
3fe93623 540 struct phy_device *phy_dev = eth_priv->phy_dev;
fc9a8e8d
KM		 541
542 debug("+ emac_open\n");
543
544 net_rx_buffs.rx_flow = eth_priv->rx_flow;
545
546 sys_has_mdio =
547 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
548
6c0fb41a
KI		 549 if (sys_has_mdio)
550 keystone2_mdio_reset(mdio_bus);
551
4657a2d4
VA		 552#ifdef CONFIG_SOC_K2G
553 keystone_rgmii_config(phy_dev);
554#else
c05d05e7 555 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
fc9a8e8d 556 eth_priv->sgmii_link_type);
4657a2d4 557#endif
fc9a8e8d
KM		 558
559 udelay(10000);
560
561 /* On chip switch configuration */
562 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
563
564 /* TODO: add error handling code */
565 if (qm_init()) {
566 printf("ERROR: qm_init()\n");
567 return -1;
568 }
9ea9021a 569 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
fc9a8e8d
KM		 570 qm_close();
571 printf("ERROR: netcp_init()\n");
572 return -1;
573 }
574
575 /*
576 * Streaming switch configuration. If not present this
577 * statement is defined to void in target.h.
578 * If present this is usually defined to a series of register writes
579 */
580 hw_config_streaming_switch();
581
582 if (sys_has_mdio) {
550c5ce6 583 keystone2_mdio_reset(mdio_bus);
fc9a8e8d 584
3fe93623
KI		 585 phy_startup(phy_dev);
586 if (phy_dev->link == 0) {
9ea9021a 587 ksnav_close(&netcp_pktdma);
fc9a8e8d
KM		 588 qm_close();
589 return -1;
590 }
591 }
592
593 emac_gigabit_enable(dev);
594
595 ethss_start();
596
597 debug("- emac_open\n");
598
599 emac_open = 1;
600
601 return 0;
602}
603
604/* Eth device close */
605void keystone2_eth_close(struct eth_device *dev)
606{
3fe93623
KI		 607 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
608 struct phy_device *phy_dev = eth_priv->phy_dev;
609
fc9a8e8d
KM		 610 debug("+ emac_close\n");
611
612 if (!emac_open)
613 return;
614
615 ethss_stop();
616
9ea9021a 617 ksnav_close(&netcp_pktdma);
fc9a8e8d 618 qm_close();
3fe93623 619 phy_shutdown(phy_dev);
fc9a8e8d
KM		 620
621 emac_open = 0;
622
623 debug("- emac_close\n");
624}
625
fc9a8e8d
KM		 626/*
627 * This function sends a single packet on the network and returns
628 * positive number (number of bytes transmitted) or negative for error
629 */
630static int keystone2_eth_send_packet(struct eth_device *dev,
631 void *packet, int length)
632{
633 int ret_status = -1;
634 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
a4d2adee 635 struct phy_device *phy_dev = eth_priv->phy_dev;
fc9a8e8d 636
a4d2adee
KI		 637 genphy_update_link(phy_dev);
638 if (phy_dev->link == 0)
fc9a8e8d
KM		 639 return -1;
640
fc9a8e8d
KM		 641 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
642 return ret_status;
643
fc9a8e8d
KM		 644 return length;
645}
646
647/*
648 * This function handles receipt of a packet from the network
649 */
650static int keystone2_eth_rcv_packet(struct eth_device *dev)
651{
652 void *hd;
653 int pkt_size;
654 u32 *pkt;
655
9ea9021a 656 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
fc9a8e8d
KM		 657 if (hd == NULL)
658 return 0;
659
1fd92db8 660 net_process_received_packet((uchar *)pkt, pkt_size);
fc9a8e8d 661
9ea9021a 662 ksnav_release_rxhd(&netcp_pktdma, hd);
fc9a8e8d
KM		 663
664 return pkt_size;
665}
666
5031ca59
VA		 667#ifdef CONFIG_MCAST_TFTP
668static int keystone2_eth_bcast_addr(struct eth_device *dev, u32 ip, u8 set)
669{
670 return 0;
671}
672#endif
673
fc9a8e8d
KM		 674/*
675 * This function initializes the EMAC hardware.
676 */
677int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
678{
550c5ce6 679 int res;
fc9a8e8d 680 struct eth_device *dev;
3fe93623 681 struct phy_device *phy_dev;
6599f369 682 struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
fc9a8e8d
KM		 683
684 dev = malloc(sizeof(struct eth_device));
685 if (dev == NULL)
686 return -1;
687
688 memset(dev, 0, sizeof(struct eth_device));
689
690 strcpy(dev->name, eth_priv->int_name);
691 dev->priv = eth_priv;
692
693 keystone2_eth_read_mac_addr(dev);
694
695 dev->iobase = 0;
696 dev->init = keystone2_eth_open;
697 dev->halt = keystone2_eth_close;
698 dev->send = keystone2_eth_send_packet;
699 dev->recv = keystone2_eth_rcv_packet;
5031ca59
VA		 700#ifdef CONFIG_MCAST_TFTP
701 dev->mcast = keystone2_eth_bcast_addr;
702#endif
fc9a8e8d
KM		 703
704 eth_register(dev);
705
550c5ce6
KI		 706 /* Register MDIO bus if it's not registered yet */
707 if (!mdio_bus) {
708 mdio_bus = mdio_alloc();
709 mdio_bus->read = keystone2_mdio_read;
710 mdio_bus->write = keystone2_mdio_write;
711 mdio_bus->reset = keystone2_mdio_reset;
712 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
192bc694 713 strcpy(mdio_bus->name, "ethernet-mdio");
550c5ce6
KI		 714
715 res = mdio_register(mdio_bus);
716 if (res)
717 return res;
718 }
719
4657a2d4 720#ifndef CONFIG_SOC_K2G
312aca4e 721 keystone2_net_serdes_setup();
4657a2d4 722#endif
312aca4e 723
3fe93623
KI		 724 /* Create phy device and bind it with driver */
725#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
726 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
bf7bd4e7 727 dev, eth_priv->phy_if);
3fe93623
KI		 728 phy_config(phy_dev);
729#else
730 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
bf7bd4e7 731 eth_priv->phy_if);
3fe93623
KI		 732 phy_dev->dev = dev;
733#endif
734 eth_priv->phy_dev = phy_dev;
735
fc9a8e8d
KM		 736 return 0;
737}
738
6599f369 739#else
92a16c81 740
6599f369 741static int ks2_eth_start(struct udevice *dev)
fc9a8e8d 742{
6599f369 743 struct ks2_eth_priv *priv = dev_get_priv(dev);
92a16c81 744
6599f369
M		 745#ifdef CONFIG_SOC_K2G
746 keystone_rgmii_config(priv->phydev);
747#else
748 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
749 priv->sgmii_link_type);
3c61502a
KI		 750#endif
751
6599f369
M		 752 udelay(10000);
753
754 /* On chip switch configuration */
755 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
756
757 qm_init();
758
759 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
760 error("ksnav_init failed\n");
761 goto err_knav_init;
762 }
763
764 /*
765 * Streaming switch configuration. If not present this
766 * statement is defined to void in target.h.
767 * If present this is usually defined to a series of register writes
768 */
769 hw_config_streaming_switch();
770
771 if (priv->has_mdio) {
a61f6a55
M		 772 keystone2_mdio_reset(priv->mdio_bus);
773
6599f369
M		 774 phy_startup(priv->phydev);
775 if (priv->phydev->link == 0) {
776 error("phy startup failed\n");
777 goto err_phy_start;
778 }
779 }
780
781 emac_gigabit_enable(dev);
782
783 ethss_start();
784
785 priv->emac_open = true;
786
787 return 0;
788
789err_phy_start:
790 ksnav_close(priv->netcp_pktdma);
791err_knav_init:
792 qm_close();
793
794 return -EFAULT;
795}
796
797static int ks2_eth_send(struct udevice *dev, void *packet, int length)
798{
799 struct ks2_eth_priv *priv = dev_get_priv(dev);
800
801 genphy_update_link(priv->phydev);
802 if (priv->phydev->link == 0)
803 return -1;
804
805 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
806 length = EMAC_MIN_ETHERNET_PKT_SIZE;
807
808 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
809 length, (priv->slave_port) << 16);
810}
811
812static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
813{
814 struct ks2_eth_priv *priv = dev_get_priv(dev);
815 int pkt_size;
816 u32 *pkt = NULL;
817
818 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
819 if (priv->hd == NULL)
820 return -EAGAIN;
821
822 *packetp = (uchar *)pkt;
823
824 return pkt_size;
825}
826
827static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
828 int length)
829{
830 struct ks2_eth_priv *priv = dev_get_priv(dev);
831
832 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
833
834 return 0;
835}
836
837static void ks2_eth_stop(struct udevice *dev)
838{
839 struct ks2_eth_priv *priv = dev_get_priv(dev);
840
841 if (!priv->emac_open)
842 return;
843 ethss_stop();
844
845 ksnav_close(priv->netcp_pktdma);
846 qm_close();
847 phy_shutdown(priv->phydev);
848 priv->emac_open = false;
849}
850
851int ks2_eth_read_rom_hwaddr(struct udevice *dev)
852{
853 struct ks2_eth_priv *priv = dev_get_priv(dev);
854 struct eth_pdata *pdata = dev_get_platdata(dev);
855 u32 maca = 0;
856 u32 macb = 0;
857
858 /* Read the e-fuse mac address */
859 if (priv->slave_port == 1) {
860 maca = __raw_readl(MAC_ID_BASE_ADDR);
861 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
862 }
863
864 pdata->enetaddr[0] = (macb >> 8) & 0xff;
865 pdata->enetaddr[1] = (macb >> 0) & 0xff;
866 pdata->enetaddr[2] = (maca >> 24) & 0xff;
867 pdata->enetaddr[3] = (maca >> 16) & 0xff;
868 pdata->enetaddr[4] = (maca >> 8) & 0xff;
869 pdata->enetaddr[5] = (maca >> 0) & 0xff;
870
871 return 0;
872}
873
874int ks2_eth_write_hwaddr(struct udevice *dev)
875{
876 struct ks2_eth_priv *priv = dev_get_priv(dev);
877 struct eth_pdata *pdata = dev_get_platdata(dev);
878
879 writel(mac_hi(pdata->enetaddr),
880 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
881 CPGMACSL_REG_SA_HI);
882 writel(mac_lo(pdata->enetaddr),
883 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
884 CPGMACSL_REG_SA_LO);
885
886 return 0;
887}
888
889static int ks2_eth_probe(struct udevice *dev)
890{
891 struct ks2_eth_priv *priv = dev_get_priv(dev);
892 struct mii_dev *mdio_bus;
893 int ret;
894
895 priv->dev = dev;
896
897 /* These clock enables has to be moved to common location */
898 if (cpu_is_k2g())
899 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
900
901 /* By default, select PA PLL clock as PA clock source */
902#ifndef CONFIG_SOC_K2G
903 if (psc_enable_module(KS2_LPSC_PA))
904 return -EACCES;
905#endif
906 if (psc_enable_module(KS2_LPSC_CPGMAC))
907 return -EACCES;
908 if (psc_enable_module(KS2_LPSC_CRYPTO))
909 return -EACCES;
910
911 if (cpu_is_k2e() || cpu_is_k2l())
912 pll_pa_clk_sel();
913
914
1610a921
M		 915 priv->net_rx_buffs.buff_ptr = rx_buffs;
916 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
917 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
6599f369 918
a61f6a55
M		 919 if (priv->slave_port == 1) {
920 /*
921 * Register MDIO bus for slave 0 only, other slave have
922 * to re-use the same
923 */
924 mdio_bus = mdio_alloc();
925 if (!mdio_bus) {
926 error("MDIO alloc failed\n");
927 return -ENOMEM;
928 }
929 priv->mdio_bus = mdio_bus;
930 mdio_bus->read = keystone2_mdio_read;
931 mdio_bus->write = keystone2_mdio_write;
932 mdio_bus->reset = keystone2_mdio_reset;
933 mdio_bus->priv = priv->mdio_base;
934 sprintf(mdio_bus->name, "ethernet-mdio");
935
936 ret = mdio_register(mdio_bus);
937 if (ret) {
938 error("MDIO bus register failed\n");
939 return ret;
940 }
941 } else {
942 /* Get the MDIO bus from slave 0 device */
943 struct ks2_eth_priv *parent_priv;
944
945 parent_priv = dev_get_priv(dev->parent);
946 priv->mdio_bus = parent_priv->mdio_bus;
6599f369
M		 947 }
948
949#ifndef CONFIG_SOC_K2G
950 keystone2_net_serdes_setup();
951#endif
952
953 priv->netcp_pktdma = &netcp_pktdma;
954
a61f6a55
M		 955 if (priv->has_mdio) {
956 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
957 dev, priv->phy_if);
958 phy_config(priv->phydev);
959 }
6599f369
M		 960
961 return 0;
fc9a8e8d 962}
6599f369
M		 963
964int ks2_eth_remove(struct udevice *dev)
965{
966 struct ks2_eth_priv *priv = dev_get_priv(dev);
967
968 free(priv->phydev);
969 mdio_unregister(priv->mdio_bus);
970 mdio_free(priv->mdio_bus);
971
972 return 0;
973}
974
975static const struct eth_ops ks2_eth_ops = {
976 .start = ks2_eth_start,
977 .send = ks2_eth_send,
978 .recv = ks2_eth_recv,
979 .free_pkt = ks2_eth_free_pkt,
980 .stop = ks2_eth_stop,
981 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
982 .write_hwaddr = ks2_eth_write_hwaddr,
983};
984
a61f6a55 985static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
6599f369 986{
6599f369 987 const void *fdt = gd->fdt_blob;
a61f6a55 988 struct udevice *sl_dev;
6599f369 989 int interfaces;
a61f6a55
M		 990 int sec_slave;
991 int slave;
992 int ret;
993 char *slave_name;
994
995 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
df87e6b1 996 fdt_for_each_subnode(slave, fdt, interfaces) {
a61f6a55
M		 997 int slave_no;
998
999 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
1000 if (slave_no == -ENOENT)
1001 continue;
1002
1003 if (slave_no == 0) {
1004 /* This is the current eth device */
1005 *gbe_0 = slave;
1006 } else {
1007 /* Slave devices to be registered */
1008 slave_name = malloc(20);
1009 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
1010 ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
1011 slave_name, slave,
1012 &sl_dev);
1013 if (ret) {
1014 error("ks2_net - not able to bind slave interfaces\n");
1015 return ret;
1016 }
1017 }
1018 }
1019
1020 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
df87e6b1 1021 fdt_for_each_subnode(slave, fdt, sec_slave) {
a61f6a55
M		 1022 int slave_no;
1023
1024 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
1025 if (slave_no == -ENOENT)
1026 continue;
1027
1028 /* Slave devices to be registered */
1029 slave_name = malloc(20);
1030 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
1031 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
1032 slave, &sl_dev);
1033 if (ret) {
1034 error("ks2_net - not able to bind slave interfaces\n");
1035 return ret;
1036 }
1037 }
1038
1039 return 0;
1040}
1041
1042static int ks2_eth_parse_slave_interface(int netcp, int slave,
1043 struct ks2_eth_priv *priv,
1044 struct eth_pdata *pdata)
1045{
1046 const void *fdt = gd->fdt_blob;
6599f369 1047 int mdio;
a61f6a55
M		 1048 int phy;
1049 int dma_count;
1050 u32 dma_channel[8];
6599f369 1051
a61f6a55
M		 1052 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
1053 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
6599f369 1054
6599f369
M		 1055 /* U-Boot slave port number starts with 1 instead of 0 */
1056 priv->slave_port += 1;
1057
a61f6a55
M		 1058 dma_count = fdtdec_get_int_array_count(fdt, netcp,
1059 "ti,navigator-dmas",
1060 dma_channel, 8);
6599f369 1061
a61f6a55
M		 1062 if (dma_count > (2 * priv->slave_port)) {
1063 int dma_idx;
1064
1065 dma_idx = priv->slave_port * 2 - 1;
1066 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
1067 }
1068
1069 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
1070
1071 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
1072 if (phy >= 0) {
1073 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
1074
1075 mdio = fdt_parent_offset(fdt, phy);
1076 if (mdio < 0) {
1077 error("mdio dt not found\n");
1078 return -ENODEV;
1079 }
1080 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
6599f369 1081 }
6599f369 1082
1de40662 1083 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
6599f369
M		 1084 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
1085 pdata->phy_interface = priv->phy_if;
1086 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
1087 priv->has_mdio = true;
1de40662
M		 1088 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
1089 priv->phy_if = PHY_INTERFACE_MODE_RGMII;
1090 pdata->phy_interface = priv->phy_if;
1091 priv->has_mdio = true;
6599f369 1092 }
6599f369 1093
a61f6a55
M		 1094 return 0;
1095}
1096
1097static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
1098{
1099 struct ks2_eth_priv *priv = dev_get_priv(dev);
1100 struct eth_pdata *pdata = dev_get_platdata(dev);
1101 const void *fdt = gd->fdt_blob;
e160f7d4 1102 int slave = dev_of_offset(dev);
a61f6a55
M		 1103 int interfaces;
1104 int gbe;
1105 int netcp_devices;
1106 int netcp;
1107
1108 interfaces = fdt_parent_offset(fdt, slave);
1109 gbe = fdt_parent_offset(fdt, interfaces);
1110 netcp_devices = fdt_parent_offset(fdt, gbe);
1111 netcp = fdt_parent_offset(fdt, netcp_devices);
1112
1113 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
1114
1115 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
1116
1117 return 0;
1118}
1119
1120static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
1121{
1122 struct ks2_eth_priv *priv = dev_get_priv(dev);
1123 struct eth_pdata *pdata = dev_get_platdata(dev);
1124 const void *fdt = gd->fdt_blob;
1125 int gbe_0 = -ENODEV;
1126 int netcp_devices;
1127 int gbe;
1128
e160f7d4 1129 netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
a61f6a55
M		 1130 "netcp-devices");
1131 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
1132
1133 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
1134
e160f7d4 1135 ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
a61f6a55
M		 1136
1137 pdata->iobase = dev_get_addr(dev);
6599f369
M		 1138
1139 return 0;
1140}
1141
1142static const struct udevice_id ks2_eth_ids[] = {
1143 { .compatible = "ti,netcp-1.0" },
1144 { }
1145};
1146
a61f6a55
M		 1147U_BOOT_DRIVER(eth_ks2_slave) = {
1148 .name = "eth_ks2_sl",
1149 .id = UCLASS_ETH,
1150 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
1151 .probe = ks2_eth_probe,
1152 .remove = ks2_eth_remove,
1153 .ops = &ks2_eth_ops,
1154 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1155 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1156 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1157};
6599f369
M		 1158
1159U_BOOT_DRIVER(eth_ks2) = {
1160 .name = "eth_ks2",
1161 .id = UCLASS_ETH,
1162 .of_match = ks2_eth_ids,
1163 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
1164 .probe = ks2_eth_probe,
1165 .remove = ks2_eth_remove,
1166 .ops = &ks2_eth_ops,
1167 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
1168 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1169 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1170};
4657a2d4 1171#endif
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