[people/ms/u-boot.git] / drivers / net / mpc512x_fec.h

/*
 * (C) Copyright 2003 - 2009
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Derived from the MPC8xx driver's header file.
 */

#ifndef __MPC512X_FEC_H
#define __MPC512X_FEC_H

#include <common.h>

/* Receive & Transmit Buffer Descriptor definitions */
typedef struct BufferDescriptor {
	u16 status;
	u16 dataLength;
	u32 dataPointer;
} FEC_RBD;

typedef struct {
	u16 status;
	u16 dataLength;
	u32 dataPointer;
} FEC_TBD;

/* private structure */
typedef enum {
	SEVENWIRE,			/* 7-wire       */
	MII10,				/* MII 10Mbps   */
	MII100				/* MII 100Mbps  */
} xceiver_type;

/* BD Numer definitions */
#define FEC_TBD_NUM		48	/* The user can adjust this value */
#define FEC_RBD_NUM		32	/* The user can adjust this value */

/* packet size limit */
#define FEC_MAX_FRAME_LEN	1522	/* recommended default value */

/* Buffer size must be evenly divisible by 16 */
#define FEC_BUFFER_SIZE		((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))

typedef struct {
	u8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;

typedef struct {
	FEC_RBD rbd[FEC_RBD_NUM];			/* RBD ring */
	FEC_TBD tbd[FEC_TBD_NUM];			/* TBD ring */
	mpc512x_frame recv_frames[FEC_RBD_NUM];		/* receive buff */
} mpc512x_buff_descs;

typedef struct {
	volatile fec512x_t *eth;
	xceiver_type xcv_type;		/* transceiver type */
	mpc512x_buff_descs *bdBase;	/* BD rings and recv buffer */
	u16 rbdIndex;			/* next receive BD to read */
	u16 tbdIndex;			/* next transmit BD to send */
	u16 usedTbdIndex;		/* next transmit BD to clean */
	u16 cleanTbdNum;		/* the number of available transmit BDs */
} mpc512x_fec_priv;

/* RBD bits definitions */
#define FEC_RBD_EMPTY		0x8000	/* Buffer is empty */
#define FEC_RBD_WRAP		0x2000	/* Last BD in ring */
#define FEC_RBD_LAST		0x0800	/* Buffer is last in frame(useless) */
#define FEC_RBD_MISS		0x0100	/* Miss bit for prom mode */
#define FEC_RBD_BC		0x0080	/* The received frame is broadcast frame */
#define FEC_RBD_MC		0x0040	/* The received frame is multicast frame */
#define FEC_RBD_LG		0x0020	/* Frame length violation */
#define FEC_RBD_NO		0x0010	/* Nonoctet align frame */
#define FEC_RBD_SH		0x0008	/* Short frame */
#define FEC_RBD_CR		0x0004	/* CRC error */
#define FEC_RBD_OV		0x0002	/* Receive FIFO overrun */
#define FEC_RBD_TR		0x0001	/* Frame is truncated */
#define FEC_RBD_ERR		(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
				FEC_RBD_OV | FEC_RBD_TR)

/* TBD bits definitions */
#define FEC_TBD_READY		0x8000	/* Buffer is ready */
#define FEC_TBD_WRAP		0x2000	/* Last BD in ring */
#define FEC_TBD_LAST		0x0800	/* Buffer is last in frame */
#define FEC_TBD_TC		0x0400	/* Transmit the CRC */
#define FEC_TBD_ABC		0x0200	/* Append bad CRC */

/* MII-related definitios */
#define FEC_MII_DATA_ST		0x40000000	/* Start of frame delimiter */
#define FEC_MII_DATA_OP_RD	0x20000000	/* Perform a read operation */
#define FEC_MII_DATA_OP_WR	0x10000000	/* Perform a write operation */
#define FEC_MII_DATA_PA_MSK	0x0f800000	/* PHY Address field mask */
#define FEC_MII_DATA_RA_MSK	0x007c0000	/* PHY Register field mask */
#define FEC_MII_DATA_TA		0x00020000	/* Turnaround */
#define FEC_MII_DATA_DATAMSK	0x0000ffff	/* PHY data field */

#define FEC_MII_DATA_RA_SHIFT	18	/* MII Register address bits */
#define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */

#endif	/* __MPC512X_FEC_H */
Commit	Line	Data
8993e54b	1	/*
a927e491	2	* (C) Copyright 2003 - 2009
8993e54b RJ	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Derived from the MPC8xx driver's header file.
	6	*/
	7
	8	#ifndef __MPC512X_FEC_H
	9	#define __MPC512X_FEC_H
	10
	11	#include <common.h>
8993e54b	12
8993e54b RJ	13	/* Receive & Transmit Buffer Descriptor definitions */
8993e54b RJ	14	typedef struct BufferDescriptor {
3b74e7ec WD	15	u16 status;
	16	u16 dataLength;
	17	u32 dataPointer;
8993e54b RJ	18	} FEC_RBD;
	19
	20	typedef struct {
3b74e7ec WD	21	u16 status;
	22	u16 dataLength;
	23	u32 dataPointer;
8993e54b RJ	24	} FEC_TBD;
	25
	26	/* private structure */
	27	typedef enum {
	28	SEVENWIRE, /* 7-wire */
	29	MII10, /* MII 10Mbps */
	30	MII100 /* MII 100Mbps */
	31	} xceiver_type;
	32
	33	/* BD Numer definitions */
	34	#define FEC_TBD_NUM 48 /* The user can adjust this value */
	35	#define FEC_RBD_NUM 32 /* The user can adjust this value */
	36
	37	/* packet size limit */
7a888d6b GB	38	#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
	39
	40	/* Buffer size must be evenly divisible by 16 */
	41	#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
8993e54b RJ	42
8993e54b RJ	43	typedef struct {
3b74e7ec	44	u8 frame[FEC_BUFFER_SIZE];
8993e54b RJ	45	} mpc512x_frame;
	46
	47	typedef struct {
	48	FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
	49	FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
	50	mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
	51	} mpc512x_buff_descs;
	52
	53	typedef struct {
a927e491	54	volatile fec512x_t *eth;
8993e54b RJ	55	xceiver_type xcv_type; /* transceiver type */
8993e54b RJ	56	mpc512x_buff_descs bdBase; / BD rings and recv buffer */
3b74e7ec WD	57	u16 rbdIndex; /* next receive BD to read */
	58	u16 tbdIndex; /* next transmit BD to send */
	59	u16 usedTbdIndex; /* next transmit BD to clean */
	60	u16 cleanTbdNum; /* the number of available transmit BDs */
8993e54b RJ	61	} mpc512x_fec_priv;
	62
	63	/* RBD bits definitions */
	64	#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
	65	#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
	66	#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
	67	#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
	68	#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
	69	#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
	70	#define FEC_RBD_LG 0x0020 /* Frame length violation */
	71	#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
	72	#define FEC_RBD_SH 0x0008 /* Short frame */
	73	#define FEC_RBD_CR 0x0004 /* CRC error */
	74	#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
	75	#define FEC_RBD_TR 0x0001 /* Frame is truncated */
	76	#define FEC_RBD_ERR (FEC_RBD_LG \| FEC_RBD_NO \| FEC_RBD_CR \| \
	77	FEC_RBD_OV \| FEC_RBD_TR)
	78
	79	/* TBD bits definitions */
	80	#define FEC_TBD_READY 0x8000 /* Buffer is ready */
	81	#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
	82	#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
	83	#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
	84	#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
	85
	86	/* MII-related definitios */
	87	#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
	88	#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
	89	#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
	90	#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
	91	#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
	92	#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
	93	#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
	94
	95	#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
	96	#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
	97
	98	#endif /* __MPC512X_FEC_H */