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video: Fix console display when splashscreen is used
[people/ms/u-boot.git] / drivers / net / mpc5xxx_fec.c
CommitLineData
945af8d7 1/*
5e5f9ed2 2 * (C) Copyright 2003-2005
945af8d7
WD		 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
80b00af0 11#include <mpc5xxx_sdma.h>
945af8d7
WD		 12#include <malloc.h>
13#include <net.h>
e1d7480b 14#include <netdev.h>
945af8d7 15#include <miiphy.h>
80b00af0 16#include "mpc5xxx_fec.h"
945af8d7 17
d87080b7
WD		 18DECLARE_GLOBAL_DATA_PTR;
19
77846748 20/* #define DEBUG 0x28 */
945af8d7 21
4431283c 22#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
63ff004c
MB		 23#error "CONFIG_MII has to be defined!"
24#endif
25
945af8d7 26#if (DEBUG & 0x60)
63ff004c
MB		 27static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
945af8d7
WD		 29#endif /* DEBUG */
30
31#if (DEBUG & 0x40)
32static uint32 local_crc32(char *string, unsigned int crc_value, int len);
33#endif
34
77846748
WD		 35typedef struct {
36 uint8 data[1500]; /* actual data */
37 int length; /* actual length */
38 int used; /* buffer in use or not */
39 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
40} NBUF;
41
63ff004c
MB		 42int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
43int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
44
f5cf2ef2
SH		 45static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
46
d4ca31c4
WD		 47/********************************************************************/
48#if (DEBUG & 0x2)
63ff004c 49static void mpc5xxx_fec_phydump (char *devname)
d4ca31c4
WD		 50{
51 uint16 phyStatus, i;
52 uint8 phyAddr = CONFIG_PHY_ADDR;
53 uint8 reg_mask[] = {
54#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
55 /* regs to print: 0...7, 16...19, 21, 23, 24 */
56 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
58#else
59 /* regs to print: 0...8, 16...20 */
60 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
61 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
62#endif
63 };
64
65 for (i = 0; i < 32; i++) {
66 if (reg_mask[i]) {
63ff004c 67 miiphy_read(devname, phyAddr, i, &phyStatus);
d4ca31c4
WD		 68 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
69 }
70 }
71}
72#endif
73
945af8d7
WD		 74/********************************************************************/
75static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
76{
77 int ix;
78 char *data;
77846748 79 static int once = 0;
945af8d7 80
945af8d7 81 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
77846748
WD		 82 if (!once) {
83 data = (char *)malloc(FEC_MAX_PKT_SIZE);
84 if (data == NULL) {
85 printf ("RBD INIT FAILED\n");
86 return -1;
87 }
88 fec->rbdBase[ix].dataPointer = (uint32)data;
945af8d7
WD		 89 }
90 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
91 fec->rbdBase[ix].dataLength = 0;
945af8d7 92 }
77846748 93 once ++;
945af8d7
WD		 94
95 /*
96 * have the last RBD to close the ring
97 */
98 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
99 fec->rbdIndex = 0;
100
101 return 0;
102}
103
104/********************************************************************/
105static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
106{
107 int ix;
108
109 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
110 fec->tbdBase[ix].status = 0;
111 }
112
113 /*
114 * Have the last TBD to close the ring
115 */
116 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
117
118 /*
119 * Initialize some indices
120 */
121 fec->tbdIndex = 0;
122 fec->usedTbdIndex = 0;
123 fec->cleanTbdNum = FEC_TBD_NUM;
124}
125
126/********************************************************************/
151ab83a 127static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
945af8d7
WD		 128{
129 /*
130 * Reset buffer descriptor as empty
131 */
132 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
133 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
134 else
135 pRbd->status = FEC_RBD_EMPTY;
136
137 pRbd->dataLength = 0;
138
139 /*
140 * Now, we have an empty RxBD, restart the SmartDMA receive task
141 */
142 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
143
144 /*
145 * Increment BD count
146 */
147 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
148}
149
150/********************************************************************/
151static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
152{
151ab83a 153 volatile FEC_TBD *pUsedTbd;
945af8d7
WD		 154
155#if (DEBUG & 0x1)
156 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
157 fec->cleanTbdNum, fec->usedTbdIndex);
158#endif
159
160 /*
161 * process all the consumed TBDs
162 */
163 while (fec->cleanTbdNum < FEC_TBD_NUM) {
164 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
165 if (pUsedTbd->status & FEC_TBD_READY) {
166#if (DEBUG & 0x20)
167 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
168#endif
169 return;
170 }
171
172 /*
173 * clean this buffer descriptor
174 */
175 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
176 pUsedTbd->status = FEC_TBD_WRAP;
177 else
178 pUsedTbd->status = 0;
179
180 /*
181 * update some indeces for a correct handling of the TBD ring
182 */
183 fec->cleanTbdNum++;
184 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
185 }
186}
187
188/********************************************************************/
189static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
190{
191 uint8 currByte; /* byte for which to compute the CRC */
192 int byte; /* loop - counter */
193 int bit; /* loop - counter */
194 uint32 crc = 0xffffffff; /* initial value */
195
196 /*
197 * The algorithm used is the following:
198 * we loop on each of the six bytes of the provided address,
199 * and we compute the CRC by left-shifting the previous
200 * value by one position, so that each bit in the current
201 * byte of the address may contribute the calculation. If
202 * the latter and the MSB in the CRC are different, then
203 * the CRC value so computed is also ex-ored with the
204 * "polynomium generator". The current byte of the address
205 * is also shifted right by one bit at each iteration.
206 * This is because the CRC generatore in hardware is implemented
207 * as a shift-register with as many ex-ores as the radixes
208 * in the polynomium. This suggests that we represent the
209 * polynomiumm itself as a 32-bit constant.
210 */
211 for (byte = 0; byte < 6; byte++) {
212 currByte = mac[byte];
213 for (bit = 0; bit < 8; bit++) {
214 if ((currByte & 0x01) ^ (crc & 0x01)) {
215 crc >>= 1;
216 crc = crc ^ 0xedb88320;
217 } else {
218 crc >>= 1;
219 }
220 currByte >>= 1;
221 }
222 }
223
224 crc = crc >> 26;
225
226 /*
227 * Set individual hash table register
228 */
229 if (crc >= 32) {
230 fec->eth->iaddr1 = (1 << (crc - 32));
231 fec->eth->iaddr2 = 0;
232 } else {
233 fec->eth->iaddr1 = 0;
234 fec->eth->iaddr2 = (1 << crc);
235 }
236
237 /*
238 * Set physical address
239 */
240 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
241 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
242}
243
244/********************************************************************/
245static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
246{
247 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
248 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
945af8d7
WD		 249
250#if (DEBUG & 0x1)
251 printf ("mpc5xxx_fec_init... Begin\n");
252#endif
253
f5cf2ef2
SH		 254 mpc5xxx_fec_init_phy(dev, bis);
255
945af8d7
WD		 256 /*
257 * Initialize RxBD/TxBD rings
258 */
259 mpc5xxx_fec_rbd_init(fec);
260 mpc5xxx_fec_tbd_init(fec);
261
945af8d7
WD		 262 /*
263 * Clear FEC-Lite interrupt event register(IEVENT)
264 */
265 fec->eth->ievent = 0xffffffff;
266
267 /*
268 * Set interrupt mask register
269 */
270 fec->eth->imask = 0x00000000;
271
272 /*
273 * Set FEC-Lite receive control register(R_CNTRL):
274 */
275 if (fec->xcv_type == SEVENWIRE) {
276 /*
277 * Frame length=1518; 7-wire mode
278 */
279 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
280 } else {
281 /*
282 * Frame length=1518; MII mode;
283 */
284 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
285 }
286
7e780369 287 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
945af8d7
WD		 288
289 /*
290 * Set Opcode/Pause Duration Register
291 */
6341d9d7 292 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
945af8d7
WD		 293
294 /*
295 * Set Rx FIFO alarm and granularity value
296 */
c44ffb9e
WD		 297 fec->eth->rfifo_cntrl = 0x0c000000
298 | (fec->eth->rfifo_cntrl & ~0x0f000000);
945af8d7
WD		 299 fec->eth->rfifo_alarm = 0x0000030c;
300#if (DEBUG & 0x22)
301 if (fec->eth->rfifo_status & 0x00700000 ) {
302 printf("mpc5xxx_fec_init() RFIFO error\n");
303 }
304#endif
305
306 /*
307 * Set Tx FIFO granularity value
308 */
c44ffb9e
WD		 309 fec->eth->tfifo_cntrl = 0x0c000000
310 | (fec->eth->tfifo_cntrl & ~0x0f000000);
945af8d7
WD		 311#if (DEBUG & 0x2)
312 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
313 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
314#endif
315
316 /*
317 * Set transmit fifo watermark register(X_WMRK), default = 64
318 */
319 fec->eth->tfifo_alarm = 0x00000080;
320 fec->eth->x_wmrk = 0x2;
321
322 /*
323 * Set individual address filter for unicast address
324 * and set physical address registers.
325 */
77ddac94 326 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
945af8d7
WD		 327
328 /*
329 * Set multicast address filter
330 */
331 fec->eth->gaddr1 = 0x00000000;
332 fec->eth->gaddr2 = 0x00000000;
333
334 /*
335 * Turn ON cheater FSM: ????
336 */
337 fec->eth->xmit_fsm = 0x03000000;
338
339#if defined(CONFIG_MPC5200)
340 /*
341 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
342 * work w/ the current receive task.
343 */
344 sdma->PtdCntrl |= 0x00000001;
345#endif
346
347 /*
348 * Set priority of different initiators
349 */
350 sdma->IPR0 = 7; /* always */
351 sdma->IPR3 = 6; /* Eth RX */
352 sdma->IPR4 = 5; /* Eth Tx */
353
354 /*
355 * Clear SmartDMA task interrupt pending bits
356 */
357 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
358
945af8d7
WD		 359 /*
360 * Initialize SmartDMA parameters stored in SRAM
361 */
151ab83a
WD		 362 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
363 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
364 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
365 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
945af8d7 366
6c1362cf
WD		 367 /*
368 * Enable FEC-Lite controller
369 */
370 fec->eth->ecntrl |= 0x00000006;
371
372#if (DEBUG & 0x2)
373 if (fec->xcv_type != SEVENWIRE)
6dedf3d4 374 mpc5xxx_fec_phydump (dev->name);
6c1362cf
WD		 375#endif
376
377 /*
378 * Enable SmartDMA receive task
379 */
380 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
381
382#if (DEBUG & 0x1)
383 printf("mpc5xxx_fec_init... Done \n");
384#endif
385
386 return 1;
387}
388
389/********************************************************************/
390static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
391{
6c1362cf
WD		 392 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
393 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
f5cf2ef2
SH		 394 static int initialized = 0;
395
396 if(initialized)
397 return 0;
398 initialized = 1;
6c1362cf
WD		 399
400#if (DEBUG & 0x1)
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
402#endif
403
404 /*
405 * Initialize GPIO pins
406 */
407 if (fec->xcv_type == SEVENWIRE) {
408 /* 10MBit with 7-wire operation */
6c7a1408
WD		 409#if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
412#else /* !CONFIG_TOTAL5200 */
413 /* 7-wire only */
6c1362cf 414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
6c7a1408 415#endif /* CONFIG_TOTAL5200 */
6c1362cf
WD		 416 } else {
417 /* 100MBit with MD operation */
418 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
419 }
420
421 /*
422 * Clear FEC-Lite interrupt event register(IEVENT)
423 */
424 fec->eth->ievent = 0xffffffff;
425
426 /*
427 * Set interrupt mask register
428 */
429 fec->eth->imask = 0x00000000;
430
008861a2
BS		 431/*
432 * In original Promess-provided code PHY initialization is disabled with the
433 * following comment: "Phy initialization is DISABLED for now. There was a
434 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
435 * PHY initialization for the Motion-PRO board, until a proper fix is found.
436 */
437
6c1362cf
WD		 438 if (fec->xcv_type != SEVENWIRE) {
439 /*
440 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
441 * and do not drop the Preamble.
442 */
443 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
444 }
445
945af8d7
WD		 446 if (fec->xcv_type != SEVENWIRE) {
447 /*
448 * Initialize PHY(LXT971A):
449 *
450 * Generally, on power up, the LXT971A reads its configuration
451 * pins to check for forced operation, If not cofigured for
452 * forced operation, it uses auto-negotiation/parallel detection
453 * to automatically determine line operating conditions.
454 * If the PHY device on the other side of the link supports
455 * auto-negotiation, the LXT971A auto-negotiates with it
456 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
457 * support auto-negotiation, the LXT971A automatically detects
458 * the presence of either link pulses(10Mbps PHY) or Idle
459 * symbols(100Mbps) and sets its operating conditions accordingly.
460 *
461 * When auto-negotiation is controlled by software, the following
462 * steps are recommended.
463 *
464 * Note:
465 * The physical address is dependent on hardware configuration.
466 *
467 */
468 int timeout = 1;
469 uint16 phyStatus;
470
471 /*
472 * Reset PHY, then delay 300ns
473 */
63ff004c 474 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
945af8d7
WD		 475 udelay(1000);
476
258c37b1
HS		 477#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
478 /* Set the LED configuration Register for the UC101
479 and MUCMC52 Board */
37403005
HS		 480 miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
481#endif
945af8d7
WD		 482 if (fec->xcv_type == MII10) {
483 /*
484 * Force 10Base-T, FDX operation
485 */
a57106fc 486#if (DEBUG & 0x2)
945af8d7 487 printf("Forcing 10 Mbps ethernet link... ");
a57106fc 488#endif
63ff004c 489 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7 490 /*
63ff004c 491 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
945af8d7 492 */
63ff004c 493 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
945af8d7
WD		 494
495 timeout = 20;
496 do { /* wait for link status to go down */
497 udelay(10000);
498 if ((timeout--) == 0) {
499#if (DEBUG & 0x2)
500 printf("hmmm, should not have waited...");
501#endif
502 break;
503 }
63ff004c 504 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 505#if (DEBUG & 0x2)
506 printf("=");
507#endif
508 } while ((phyStatus & 0x0004)); /* !link up */
509
510 timeout = 1000;
511 do { /* wait for link status to come back up */
512 udelay(10000);
513 if ((timeout--) == 0) {
514 printf("failed. Link is down.\n");
515 break;
516 }
63ff004c 517 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 518#if (DEBUG & 0x2)
519 printf("+");
520#endif
521 } while (!(phyStatus & 0x0004)); /* !link up */
522
ab209d51 523#if (DEBUG & 0x2)
945af8d7 524 printf ("done.\n");
ab209d51 525#endif
945af8d7
WD		 526 } else { /* MII100 */
527 /*
528 * Set the auto-negotiation advertisement register bits
529 */
63ff004c 530 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
945af8d7
WD		 531
532 /*
533 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
534 */
63ff004c 535 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
945af8d7
WD		 536
537 /*
538 * Wait for AN completion
539 */
540 timeout = 5000;
541 do {
542 udelay(1000);
543
544 if ((timeout--) == 0) {
545#if (DEBUG & 0x2)
546 printf("PHY auto neg 0 failed...\n");
547#endif
548 return -1;
549 }
550
63ff004c 551 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
945af8d7
WD		 552#if (DEBUG & 0x2)
553 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
554#endif
555 return -1;
556 }
7e780369 557 } while (!(phyStatus & 0x0004));
945af8d7
WD		 558
559#if (DEBUG & 0x2)
560 printf("PHY auto neg complete! \n");
561#endif
562 }
563
564 }
565
945af8d7 566#if (DEBUG & 0x2)
d4ca31c4 567 if (fec->xcv_type != SEVENWIRE)
63ff004c 568 mpc5xxx_fec_phydump (dev->name);
945af8d7 569#endif
d4ca31c4 570
945af8d7
WD		 571
572#if (DEBUG & 0x1)
6c1362cf 573 printf("mpc5xxx_fec_init_phy... Done \n");
945af8d7
WD		 574#endif
575
013dc8d9 576 return 1;
945af8d7
WD		 577}
578
579/********************************************************************/
580static void mpc5xxx_fec_halt(struct eth_device *dev)
581{
77846748 582#if defined(CONFIG_MPC5200)
945af8d7 583 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
77846748
WD		 584#endif
585 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
945af8d7
WD		 586 int counter = 0xffff;
587
588#if (DEBUG & 0x2)
d4ca31c4 589 if (fec->xcv_type != SEVENWIRE)
6dedf3d4 590 mpc5xxx_fec_phydump (dev->name);
945af8d7
WD		 591#endif
592
945af8d7
WD		 593 /*
594 * mask FEC chip interrupts
595 */
596 fec->eth->imask = 0;
597
598 /*
599 * issue graceful stop command to the FEC transmitter if necessary
600 */
601 fec->eth->x_cntrl |= 0x00000001;
602
603 /*
604 * wait for graceful stop to register
605 */
606 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
607
945af8d7
WD		 608 /*
609 * Disable SmartDMA tasks
610 */
611 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
612 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
613
614#if defined(CONFIG_MPC5200)
615 /*
616 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
617 * done. It doesn't work w/ the current receive task.
618 */
619 sdma->PtdCntrl &= ~0x00000001;
620#endif
621
622 /*
623 * Disable the Ethernet Controller
624 */
625 fec->eth->ecntrl &= 0xfffffffd;
626
627 /*
628 * Clear FIFO status registers
629 */
630 fec->eth->rfifo_status &= 0x00700000;
631 fec->eth->tfifo_status &= 0x00700000;
632
633 fec->eth->reset_cntrl = 0x01000000;
634
635 /*
636 * Issue a reset command to the FEC chip
637 */
638 fec->eth->ecntrl |= 0x1;
639
640 /*
641 * wait at least 16 clock cycles
642 */
643 udelay(10);
644
f949bd8d
JS		 645 /* don't leave the MII speed set to zero */
646 if (fec->xcv_type != SEVENWIRE) {
647 /*
648 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
649 * and do not drop the Preamble.
650 */
651 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
652 }
653
945af8d7
WD		 654#if (DEBUG & 0x3)
655 printf("Ethernet task stopped\n");
656#endif
657}
658
659#if (DEBUG & 0x60)
660/********************************************************************/
661
63ff004c 662static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
945af8d7 663{
d4ca31c4 664 uint16 phyAddr = CONFIG_PHY_ADDR;
945af8d7
WD		 665 uint16 phyStatus;
666
667 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
668 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
669
63ff004c 670 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 671 printf("\nphyStatus: 0x%04x\n", phyStatus);
672 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
673 printf("ievent: 0x%08x\n", fec->eth->ievent);
674 printf("x_status: 0x%08x\n", fec->eth->x_status);
675 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
676
677 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
678 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
679 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
680 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
681 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
682 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
683 }
684}
685
63ff004c 686static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
945af8d7 687{
d4ca31c4 688 uint16 phyAddr = CONFIG_PHY_ADDR;
945af8d7
WD		 689 uint16 phyStatus;
690
691 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
692 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
693
63ff004c 694 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 695 printf("\nphyStatus: 0x%04x\n", phyStatus);
696 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
697 printf("ievent: 0x%08x\n", fec->eth->ievent);
698 printf("x_status: 0x%08x\n", fec->eth->x_status);
699 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
700
701 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
702 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
703 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
704 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
705 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
706 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
707 }
708}
709#endif /* DEBUG */
710
711/********************************************************************/
712
713static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
714 int data_length)
715{
716 /*
717 * This routine transmits one frame. This routine only accepts
718 * 6-byte Ethernet addresses.
719 */
720 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
151ab83a 721 volatile FEC_TBD *pTbd;
945af8d7
WD		 722
723#if (DEBUG & 0x20)
724 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
63ff004c 725 tfifo_print(dev->name, fec);
945af8d7
WD		 726#endif
727
728 /*
729 * Clear Tx BD ring at first
730 */
731 mpc5xxx_fec_tbd_scrub(fec);
732
733 /*
734 * Check for valid length of data.
735 */
736 if ((data_length > 1500) || (data_length <= 0)) {
737 return -1;
738 }
739
740 /*
741 * Check the number of vacant TxBDs.
742 */
743 if (fec->cleanTbdNum < 1) {
744#if (DEBUG & 0x20)
745 printf("No available TxBDs ...\n");
746#endif
747 return -1;
748 }
749
750 /*
751 * Get the first TxBD to send the mac header
752 */
753 pTbd = &fec->tbdBase[fec->tbdIndex];
754 pTbd->dataLength = data_length;
755 pTbd->dataPointer = (uint32)eth_data;
77846748 756 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
945af8d7
WD		 757 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
758
759#if (DEBUG & 0x100)
760 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
761#endif
762
763 /*
764 * Kick the MII i/f
765 */
766 if (fec->xcv_type != SEVENWIRE) {
767 uint16 phyStatus;
63ff004c 768 miiphy_read(dev->name, 0, 0x1, &phyStatus);
945af8d7
WD		 769 }
770
771 /*
772 * Enable SmartDMA transmit task
773 */
774
775#if (DEBUG & 0x20)
63ff004c 776 tfifo_print(dev->name, fec);
945af8d7
WD		 777#endif
778 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
779#if (DEBUG & 0x20)
63ff004c 780 tfifo_print(dev->name, fec);
945af8d7
WD		 781#endif
782#if (DEBUG & 0x8)
783 printf( "+" );
784#endif
785
786 fec->cleanTbdNum -= 1;
787
788#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
789 printf ("smartDMA ethernet Tx task enabled\n");
790#endif
791 /*
792 * wait until frame is sent .
793 */
794 while (pTbd->status & FEC_TBD_READY) {
795 udelay(10);
796#if (DEBUG & 0x8)
797 printf ("TDB status = %04x\n", pTbd->status);
798#endif
799 }
800
801 return 0;
802}
803
804
805/********************************************************************/
806static int mpc5xxx_fec_recv(struct eth_device *dev)
807{
808 /*
809 * This command pulls one frame from the card
810 */
811 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
151ab83a 812 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
945af8d7 813 unsigned long ievent;
77846748
WD		 814 int frame_length, len = 0;
815 NBUF *frame;
77ddac94 816 uchar buff[FEC_MAX_PKT_SIZE];
945af8d7
WD		 817
818#if (DEBUG & 0x1)
819 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
820#endif
821#if (DEBUG & 0x8)
822 printf( "-" );
823#endif
824
825 /*
826 * Check if any critical events have happened
827 */
828 ievent = fec->eth->ievent;
829 fec->eth->ievent = ievent;
830 if (ievent & 0x20060000) {
831 /* BABT, Rx/Tx FIFO errors */
832 mpc5xxx_fec_halt(dev);
833 mpc5xxx_fec_init(dev, NULL);
834 return 0;
835 }
836 if (ievent & 0x80000000) {
837 /* Heartbeat error */
838 fec->eth->x_cntrl |= 0x00000001;
839 }
840 if (ievent & 0x10000000) {
841 /* Graceful stop complete */
842 if (fec->eth->x_cntrl & 0x00000001) {
843 mpc5xxx_fec_halt(dev);
844 fec->eth->x_cntrl &= ~0x00000001;
845 mpc5xxx_fec_init(dev, NULL);
846 }
847 }
848
77846748
WD		 849 if (!(pRbd->status & FEC_RBD_EMPTY)) {
850 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
851 ((pRbd->dataLength - 4) > 14)) {
945af8d7 852
77846748
WD		 853 /*
854 * Get buffer address and size
855 */
856 frame = (NBUF *)pRbd->dataPointer;
857 frame_length = pRbd->dataLength - 4;
858
859#if (DEBUG & 0x20)
860 {
861 int i;
862 printf("recv data hdr:");
863 for (i = 0; i < 14; i++)
864 printf("%x ", *(frame->head + i));
865 printf("\n");
866 }
945af8d7 867#endif
77846748
WD		 868 /*
869 * Fill the buffer and pass it to upper layers
870 */
871 memcpy(buff, frame->head, 14);
872 memcpy(buff + 14, frame->data, frame_length);
873 NetReceive(buff, frame_length);
874 len = frame_length;
875 }
876 /*
877 * Reset buffer descriptor as empty
878 */
879 mpc5xxx_fec_rbd_clean(fec, pRbd);
945af8d7 880 }
77846748
WD		 881 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
882 return len;
945af8d7
WD		 883}
884
885
886/********************************************************************/
887int mpc5xxx_fec_initialize(bd_t * bis)
888{
889 mpc5xxx_fec_priv *fec;
890 struct eth_device *dev;
12f34241
WD		 891 char *tmp, *end;
892 char env_enetaddr[6];
893 int i;
945af8d7
WD		 894
895 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
896 dev = (struct eth_device *)malloc(sizeof(*dev));
53677ef1 897 memset(dev, 0, sizeof *dev);
945af8d7
WD		 898
899 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
900 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
901 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
86321fc1 902#if defined(CONFIG_MPC5xxx_FEC_MII100)
945af8d7 903 fec->xcv_type = MII100;
86321fc1 904#elif defined(CONFIG_MPC5xxx_FEC_MII10)
a57106fc 905 fec->xcv_type = MII10;
86321fc1 906#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
6c7a1408 907 fec->xcv_type = SEVENWIRE;
a57106fc
WD		 908#else
909#error fec->xcv_type not initialized.
945af8d7 910#endif
f949bd8d
JS		 911 if (fec->xcv_type != SEVENWIRE) {
912 /*
913 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
914 * and do not drop the Preamble.
915 */
916 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
917 }
945af8d7
WD		 918
919 dev->priv = (void *)fec;
920 dev->iobase = MPC5XXX_FEC;
921 dev->init = mpc5xxx_fec_init;
922 dev->halt = mpc5xxx_fec_halt;
923 dev->send = mpc5xxx_fec_send;
924 dev->recv = mpc5xxx_fec_recv;
925
77846748 926 sprintf(dev->name, "FEC ETHERNET");
945af8d7
WD		 927 eth_register(dev);
928
4431283c 929#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
63ff004c
MB		 930 miiphy_register (dev->name,
931 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
932#endif
933
12f34241
WD		 934 /*
935 * Try to set the mac address now. The fec mac address is
42d1f039 936 * a garbage after reset. When not using fec for booting
12f34241
WD		 937 * the Linux fec driver will try to work with this garbage.
938 */
939 tmp = getenv("ethaddr");
940 if (tmp) {
941 for (i=0; i<6; i++) {
942 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
943 if (tmp)
944 tmp = (*end) ? end+1 : end;
945 }
946 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
947 }
948
945af8d7
WD		 949 return 1;
950}
951
952/* MII-interface related functions */
953/********************************************************************/
63ff004c 954int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
945af8d7
WD		 955{
956 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
957 uint32 reg; /* convenient holder for the PHY register */
958 uint32 phy; /* convenient holder for the PHY */
959 int timeout = 0xffff;
960
961 /*
962 * reading from any PHY's register is done by properly
963 * programming the FEC's MII data register.
964 */
965 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
966 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
967
968 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
969
970 /*
971 * wait for the related interrupt
972 */
973 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
974
975 if (timeout == 0) {
976#if (DEBUG & 0x2)
977 printf ("Read MDIO failed...\n");
978#endif
979 return -1;
980 }
981
982 /*
983 * clear mii interrupt bit
984 */
985 eth->ievent = 0x00800000;
986
987 /*
988 * it's now safe to read the PHY's register
989 */
990 *retVal = (uint16) eth->mii_data;
991
992 return 0;
993}
994
995/********************************************************************/
63ff004c 996int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
945af8d7
WD		 997{
998 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
999 uint32 reg; /* convenient holder for the PHY register */
1000 uint32 phy; /* convenient holder for the PHY */
1001 int timeout = 0xffff;
1002
1003 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
1004 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
1005
1006 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
1007 FEC_MII_DATA_TA | phy | reg | data);
1008
1009 /*
1010 * wait for the MII interrupt
1011 */
1012 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1013
1014 if (timeout == 0) {
1015#if (DEBUG & 0x2)
1016 printf ("Write MDIO failed...\n");
1017#endif
1018 return -1;
1019 }
1020
1021 /*
1022 * clear MII interrupt bit
1023 */
1024 eth->ievent = 0x00800000;
1025
1026 return 0;
1027}
1028
1029#if (DEBUG & 0x40)
1030static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1031{
1032 int i;
1033 char c;
1034 unsigned int crc, count;
1035
1036 /*
1037 * crc32 algorithm
1038 */
1039 /*
1040 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1041 */
1042 crc = crc_value;
1043
1044 for (i = len; --i >= 0;) {
1045 c = *string++;
1046 for (count = 0; count < 8; count++) {
1047 if ((c & 0x01) ^ (crc & 0x01)) {
1048 crc >>= 1;
1049 crc = crc ^ 0xedb88320;
1050 } else {
1051 crc >>= 1;
1052 }
1053 c >>= 1;
1054 }
1055 }
1056
1057 /*
1058 * In big endian system, do byte swaping for crc value
1059 */
1060 /**/ return crc;
1061}
1062#endif /* DEBUG */
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