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1 | /** |
2 | * @file IxParityENAcc.h | |
3 | * | |
4 | * @author Intel Corporation | |
5 | * @date 24 Mar 2004 | |
6 | * | |
7 | * @brief This file contains the public API for the IXP400 Parity Error | |
8 | * Notifier access component. | |
9 | * | |
10 | * @par | |
11 | * IXP400 SW Release version 2.0 | |
12 | * | |
13 | * -- Copyright Notice -- | |
14 | * | |
15 | * @par | |
16 | * Copyright 2001-2005, Intel Corporation. | |
17 | * All rights reserved. | |
18 | * | |
19 | * @par | |
cb3761ea | 20 | * SPDX-License-Identifier: BSD-3-Clause |
ba94a1bb WD |
21 | * @par |
22 | * -- End of Copyright Notice -- | |
23 | */ | |
24 | ||
25 | /** | |
26 | * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API | |
27 | * | |
28 | * @brief The public API for the Parity Error Notifier | |
29 | * | |
30 | * @{ | |
31 | */ | |
32 | ||
33 | #ifndef IXPARITYENACC_H | |
34 | #define IXPARITYENACC_H | |
35 | ||
36 | #ifdef __ixp46X | |
37 | ||
38 | #include "IxOsal.h" | |
39 | ||
40 | /* | |
41 | * #defines for function return types, etc. | |
42 | */ | |
43 | ||
44 | /** | |
45 | * @ingroup IxParityENAcc | |
46 | * | |
47 | * @enum IxParityENAccStatus | |
48 | * | |
49 | * @brief The status as returend from the API | |
50 | */ | |
51 | typedef enum /**< IxParityENAccStatus */ | |
52 | { | |
53 | IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */ | |
54 | IX_PARITYENACC_INVALID_PARAMETERS, /**< Invalid or NULL parameters passed */ | |
55 | IX_PARITYENACC_NOT_INITIALISED, /**< Access layer has not been initialised before accessing the APIs */ | |
56 | IX_PARITYENACC_ALREADY_INITIALISED, /**< Access layer has already been initialised */ | |
57 | IX_PARITYENACC_OPERATION_FAILED, /**< Operation did not succeed due to hardware failure */ | |
58 | IX_PARITYENACC_NO_PARITY /**< No parity condition exits or has already been cleared */ | |
59 | } IxParityENAccStatus; | |
60 | ||
61 | /** | |
62 | * @ingroup IxParityENAcc | |
63 | * | |
64 | * @enum IxParityENAccParityType | |
65 | * | |
66 | * @brief Odd or Even Parity Type | |
67 | */ | |
68 | typedef enum /**< IxParityENAccParityType */ | |
69 | { | |
70 | IX_PARITYENACC_EVEN_PARITY, /**< Even Parity */ | |
71 | IX_PARITYENACC_ODD_PARITY /**< Odd Parity */ | |
72 | } IxParityENAccParityType; | |
73 | ||
74 | /** | |
75 | * @ingroup IxParityENAcc | |
76 | * | |
77 | * @enum IxParityENAccConfigOption | |
78 | * | |
79 | * @brief The parity error enable/disable configuration option | |
80 | */ | |
81 | typedef enum /**< IxParityENAccConfigOption */ | |
82 | { | |
83 | IX_PARITYENACC_DISABLE, /**< Disable parity error detection */ | |
84 | IX_PARITYENACC_ENABLE /**< Enable parity error detection */ | |
85 | } IxParityENAccConfigOption; | |
86 | ||
87 | /** | |
88 | * @ingroup IxParityENAcc | |
89 | * | |
90 | * @struct IxParityENAccNpeConfig | |
91 | * | |
92 | * @brief NPE parity detection is to be enabled/disabled | |
93 | */ | |
94 | typedef struct /**< IxParityENAccNpeConfig */ | |
95 | { | |
96 | IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */ | |
97 | IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */ | |
98 | } IxParityENAccNpeConfig ; | |
99 | ||
100 | ||
101 | /** | |
102 | * @ingroup IxParityENAcc | |
103 | * | |
104 | * @struct IxParityENAccMcuConfig | |
105 | * | |
106 | * @brief MCU pairty detection is to be enabled/disabled | |
107 | */ | |
108 | typedef struct /**< IxParityENAccMcuConfig */ | |
109 | { | |
110 | IxParityENAccConfigOption singlebitDetectEnabled; /**< Single-bit parity error detection */ | |
111 | IxParityENAccConfigOption singlebitCorrectionEnabled; /**< Single-bit parity error correction */ | |
112 | IxParityENAccConfigOption multibitDetectionEnabled; /**< Multi-bit parity error detection */ | |
113 | } IxParityENAccMcuConfig ; | |
114 | ||
115 | ||
116 | /** | |
117 | * @ingroup IxParityENAcc | |
118 | * | |
119 | * @struct IxParityENAccEbcConfig | |
120 | * | |
121 | * @brief Expansion Bus Controller parity detection is to be enabled or disabled | |
122 | * | |
123 | * Note: All the Chip Select(s) and External Masters will have the same parity | |
124 | */ | |
125 | typedef struct /**< IxParityENAccEbcConfig */ | |
126 | { | |
127 | IxParityENAccConfigOption ebcCs0Enabled; /**< Expansion Bus Controller - Chip Select 0 */ | |
128 | IxParityENAccConfigOption ebcCs1Enabled; /**< Expansion Bus Controller - Chip Select 1 */ | |
129 | IxParityENAccConfigOption ebcCs2Enabled; /**< Expansion Bus Controller - Chip Select 2 */ | |
130 | IxParityENAccConfigOption ebcCs3Enabled; /**< Expansion Bus Controller - Chip Select 3 */ | |
131 | IxParityENAccConfigOption ebcCs4Enabled; /**< Expansion Bus Controller - Chip Select 4 */ | |
132 | IxParityENAccConfigOption ebcCs5Enabled; /**< Expansion Bus Controller - Chip Select 5 */ | |
133 | IxParityENAccConfigOption ebcCs6Enabled; /**< Expansion Bus Controller - Chip Select 6 */ | |
134 | IxParityENAccConfigOption ebcCs7Enabled; /**< Expansion Bus Controller - Chip Select 7 */ | |
135 | IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */ | |
136 | IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */ | |
137 | } IxParityENAccEbcConfig ; | |
138 | ||
139 | /** | |
140 | * @ingroup IxParityENAcc | |
141 | * | |
142 | * @struct IxParityENAccHWParityConfig | |
143 | * | |
144 | * @brief Parity error configuration of the Hardware Blocks | |
145 | */ | |
146 | typedef struct /**< IxParityENAccHWParityConfig */ | |
147 | { | |
148 | IxParityENAccNpeConfig npeAConfig; /**< NPE A parity detection is to be enabled/disabled */ | |
149 | IxParityENAccNpeConfig npeBConfig; /**< NPE B parity detection is to be enabled/disabled */ | |
150 | IxParityENAccNpeConfig npeCConfig; /**< NPE C parity detection is to be enabled/disabled */ | |
151 | IxParityENAccMcuConfig mcuConfig; /**< MCU pairty detection is to be enabled/disabled */ | |
152 | IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */ | |
153 | IxParityENAccConfigOption aqmEnabled; /**< AQM parity detection is to be enabled */ | |
154 | IxParityENAccEbcConfig ebcConfig; /**< Expansion Bus Controller parity detection is to be enabled/disabled */ | |
155 | } IxParityENAccHWParityConfig; | |
156 | ||
157 | ||
158 | /** | |
159 | * @ingroup IxParityENAcc | |
160 | * | |
161 | * @struct IxParityENAccNpeParityErrorStats | |
162 | * | |
163 | * @brief NPE parity error statistics | |
164 | */ | |
165 | typedef struct /* IxParityENAccNpeParityErrorStats */ | |
166 | { | |
167 | UINT32 parityErrorsIMem; /**< Parity errors in Instruction Memory */ | |
168 | UINT32 parityErrorsDMem; /**< Parity errors in Data Memory */ | |
169 | UINT32 parityErrorsExternal; /**< Parity errors in NPE External Entities */ | |
170 | } IxParityENAccNpeParityErrorStats; | |
171 | ||
172 | /** | |
173 | * @ingroup IxParityENAcc | |
174 | * | |
175 | * @struct IxParityENAccMcuParityErrorStats | |
176 | * | |
177 | * @brief DDR Memory Control Unit parity error statistics | |
178 | * | |
179 | * Note: There could be two outstanding parity errors at any given time whose address | |
180 | * details captured. If there is no room for the new interrupt then it would be treated | |
181 | * as overflow parity condition. | |
182 | */ | |
183 | typedef struct /* IxParityENAccMcuParityErrorStats */ | |
184 | { | |
185 | UINT32 parityErrorsSingleBit; /**< Parity errors of the type Single-Bit */ | |
186 | UINT32 parityErrorsMultiBit; /**< Parity errors of the type Multi-Bit */ | |
187 | UINT32 parityErrorsOverflow; /**< Parity errors when more than two parity errors occured */ | |
188 | } IxParityENAccMcuParityErrorStats; | |
189 | ||
190 | /** | |
191 | * @ingroup IxParityENAcc | |
192 | * | |
193 | * @struct IxParityENAccEbcParityErrorStats | |
194 | * | |
195 | * @brief Expansion Bus Controller parity error statistics | |
196 | */ | |
197 | typedef struct /* IxParityENAccEbcParityErrorStats */ | |
198 | { | |
199 | UINT32 parityErrorsInbound; /**< Odd bit parity errors on inbound transfers */ | |
200 | UINT32 parityErrorsOutbound; /**< Odd bit parity errors on outbound transfers */ | |
201 | } IxParityENAccEbcParityErrorStats; | |
202 | ||
203 | ||
204 | /** | |
205 | * @ingroup IxParityENAcc | |
206 | * | |
207 | * @struct IxParityENAccParityErrorStats | |
208 | * | |
209 | * @brief Parity Error Statistics for the all the hardware blocks | |
210 | */ | |
211 | typedef struct /**< IxParityENAccParityErrorStats */ | |
212 | { | |
213 | IxParityENAccNpeParityErrorStats npeStats; /**< NPE parity error statistics */ | |
214 | IxParityENAccMcuParityErrorStats mcuStats; /**< MCU parity error statistics */ | |
215 | IxParityENAccEbcParityErrorStats ebcStats; /**< EBC parity error statistics */ | |
216 | UINT32 swcpStats; /**< SWCP parity error statistics */ | |
217 | UINT32 aqmStats; /**< AQM parity error statistics */ | |
218 | } IxParityENAccParityErrorStats; | |
219 | ||
220 | ||
221 | /** | |
222 | * @ingroup IxParityENAcc | |
223 | * | |
224 | * @enum IxParityENAccParityErrorSource | |
225 | * | |
226 | * @brief The source of the parity error notification | |
227 | */ | |
228 | typedef enum /**< IxParityENAccParityErrorSource */ | |
229 | { | |
230 | IX_PARITYENACC_NPE_A_IMEM, /**< NPE A - Instruction memory */ | |
231 | IX_PARITYENACC_NPE_A_DMEM, /**< NPE A - Data memory */ | |
232 | IX_PARITYENACC_NPE_A_EXT, /**< NPE A - External Entity*/ | |
233 | IX_PARITYENACC_NPE_B_IMEM, /**< NPE B - Instruction memory */ | |
234 | IX_PARITYENACC_NPE_B_DMEM, /**< NPE B - Data memory */ | |
235 | IX_PARITYENACC_NPE_B_EXT, /**< NPE B - External Entity*/ | |
236 | IX_PARITYENACC_NPE_C_IMEM, /**< NPE C - Instruction memory */ | |
237 | IX_PARITYENACC_NPE_C_DMEM, /**< NPE C - Data memory */ | |
238 | IX_PARITYENACC_NPE_C_EXT, /**< NPE C - External Entity*/ | |
239 | IX_PARITYENACC_SWCP, /**< SWCP */ | |
240 | IX_PARITYENACC_AQM, /**< AQM */ | |
241 | IX_PARITYENACC_MCU_SBIT, /**< DDR Memory Controller Unit - Single bit parity */ | |
242 | IX_PARITYENACC_MCU_MBIT, /**< DDR Memory Controller Unit - Multi bit parity */ | |
243 | IX_PARITYENACC_MCU_OVERFLOW, /**< DDR Memory Controller Unit - Parity errors in excess of two */ | |
244 | IX_PARITYENACC_EBC_CS, /**< Expansion Bus Controller - Chip Select */ | |
245 | IX_PARITYENACC_EBC_EXTMST /**< Expansion Bus Controller - External Master */ | |
246 | } IxParityENAccParityErrorSource; | |
247 | ||
248 | /** | |
249 | * @ingroup IxParityENAcc | |
250 | * | |
251 | * @enum IxParityENAccParityErrorAccess | |
252 | * | |
253 | * @brief The type of access resulting in parity error | |
254 | */ | |
255 | typedef enum /**< IxParityENAccParityErrorAccess */ | |
256 | { | |
257 | IX_PARITYENACC_READ, /**< Read Access */ | |
258 | IX_PARITYENACC_WRITE /**< Write Access */ | |
259 | } IxParityENAccParityErrorAccess; | |
260 | ||
261 | /** | |
262 | * @ingroup IxParityENAcc | |
263 | * | |
264 | * @typedef IxParityENAccParityErrorAddress | |
265 | * | |
266 | * @brief The memory location which has parity error | |
267 | */ | |
268 | typedef UINT32 IxParityENAccParityErrorAddress; | |
269 | ||
270 | /** | |
271 | * @ingroup IxParityENAcc | |
272 | * | |
273 | * @typedef IxParityENAccParityErrorData | |
274 | * | |
275 | * @brief The data read from the memory location which has parity error | |
276 | */ | |
277 | typedef UINT32 IxParityENAccParityErrorData; | |
278 | ||
279 | /** | |
280 | * @ingroup IxParityENAcc | |
281 | * | |
282 | * @enum IxParityENAccParityErrorRequester | |
283 | * | |
284 | * @brief The requester interface through which the SDRAM memory access | |
285 | * resulted in the parity error. | |
286 | */ | |
287 | typedef enum /**< IxParityENAccParityErrorRequester */ | |
288 | { | |
289 | IX_PARITYENACC_MPI, /**< Direct Memory Port Interface */ | |
290 | IX_PARITYENACC_AHB_BUS /**< South or North AHB Bus */ | |
291 | } IxParityENAccParityErrorRequester; | |
292 | ||
293 | /** | |
294 | * @ingroup IxParityENAcc | |
295 | * | |
296 | * @enum IxParityENAccAHBErrorMaster | |
297 | * | |
298 | * @brief The Master on the AHB bus interface whose transaction might have | |
299 | * resulted in the parity error notification to XScale. | |
300 | */ | |
301 | typedef enum /**< IxParityENAccAHBErrorMaster */ | |
302 | { | |
303 | IX_PARITYENACC_AHBN_MST_NPE_A, /**< NPE - A */ | |
304 | IX_PARITYENACC_AHBN_MST_NPE_B, /**< NPE - B */ | |
305 | IX_PARITYENACC_AHBN_MST_NPE_C, /**< NPE - C */ | |
306 | IX_PARITYENACC_AHBS_MST_XSCALE, /**< XScale Bus Interface Unit */ | |
307 | IX_PARITYENACC_AHBS_MST_PBC, /**< PCI Bus Controller */ | |
308 | IX_PARITYENACC_AHBS_MST_EBC, /**< Expansion Bus Controller */ | |
309 | IX_PARITYENACC_AHBS_MST_AHB_BRIDGE, /**< AHB Bridge */ | |
310 | IX_PARITYENACC_AHBS_MST_USBH /**< USB Host Controller */ | |
311 | } IxParityENAccAHBErrorMaster; | |
312 | ||
313 | /** | |
314 | * @ingroup IxParityENAcc | |
315 | * | |
316 | * @enum IxParityENAccAHBErrorSlave | |
317 | * | |
318 | * @brief The Slave on the AHB bus interface whose transaction might have | |
319 | * resulted in the parity error notification to XScale. | |
320 | */ | |
321 | typedef enum /**< IxParityENAccAHBErrorSlave */ | |
322 | { | |
323 | IX_PARITYENACC_AHBN_SLV_MCU, /**< Memory Control Unit */ | |
324 | IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE, /**< AHB Bridge */ | |
325 | IX_PARITYENACC_AHBS_SLV_MCU, /**< XScale Bus Interface Unit */ | |
326 | IX_PARITYENACC_AHBS_SLV_APB_BRIDGE, /**< APB Bridge */ | |
327 | IX_PARITYENACC_AHBS_SLV_AQM, /**< AQM */ | |
328 | IX_PARITYENACC_AHBS_SLV_RSA, /**< RSA (Crypto Bus) */ | |
329 | IX_PARITYENACC_AHBS_SLV_PBC, /**< PCI Bus Controller */ | |
330 | IX_PARITYENACC_AHBS_SLV_EBC, /**< Expansion Bus Controller */ | |
331 | IX_PARITYENACC_AHBS_SLV_USBH /**< USB Host Controller */ | |
332 | } IxParityENAccAHBErrorSlave; | |
333 | ||
334 | /** | |
335 | * @ingroup IxParityENAcc | |
336 | * | |
337 | * @struct IxParityENAccAHBErrorTransaction | |
338 | * | |
339 | * @brief The Master and Slave on the AHB bus interface whose transaction might | |
340 | * have resulted in the parity error notification to XScale. | |
341 | * | |
342 | * NOTE: This information may be used in the data abort exception handler | |
343 | * to differentiate between the XScale and non-XScale access to the SDRAM | |
344 | * memory. | |
345 | */ | |
346 | typedef struct /**< IxParityENAccAHBErrorTransaction */ | |
347 | { | |
348 | IxParityENAccAHBErrorMaster ahbErrorMaster; /**< Master on AHB bus */ | |
349 | IxParityENAccAHBErrorSlave ahbErrorSlave; /**< Slave on AHB bus */ | |
350 | } IxParityENAccAHBErrorTransaction; | |
351 | ||
352 | /** | |
353 | * @ingroup IxParityENAcc | |
354 | * | |
355 | * @struct IxParityENAccParityErrorContextMessage | |
356 | * | |
357 | * @brief Parity Error Context Message | |
358 | */ | |
359 | typedef struct /**< IxParityENAccParityErrorContextMessage */ | |
360 | { | |
361 | IxParityENAccParityErrorSource pecParitySource; /**< Source info of parity error */ | |
362 | IxParityENAccParityErrorAccess pecAccessType; /**< Read or Write Access | |
363 | Read - NPE, SWCP, AQM, DDR MCU, | |
364 | Exp Bus Ctrlr (Outbound) | |
365 | Write - DDR MCU, | |
366 | Exp Bus Ctrlr (Inbound | |
367 | i.e., External Master) */ | |
368 | IxParityENAccParityErrorAddress pecAddress; /**< Address faulty location | |
369 | Valid only for AQM, DDR MCU, | |
370 | Exp Bus Ctrlr */ | |
371 | IxParityENAccParityErrorData pecData; /**< Data read from the faulty location | |
372 | Valid only for AQM and DDR MCU | |
373 | For DDR MCU it is the bit location | |
374 | of the Single-bit parity */ | |
375 | IxParityENAccParityErrorRequester pecRequester; /**< Requester of SDRAM memory access | |
376 | Valid only for the DDR MCU */ | |
377 | IxParityENAccAHBErrorTransaction ahbErrorTran; /**< Master and Slave information on the | |
378 | last AHB Error Transaction */ | |
379 | } IxParityENAccParityErrorContextMessage; | |
380 | ||
381 | /** | |
382 | * @ingroup IxParityENAcc | |
383 | * | |
384 | * @typedef IxParityENAccCallback | |
385 | * | |
386 | * @brief This prototype shows the format of a callback function. | |
387 | * | |
388 | * The callback will be used to notify the parity error to the client application. | |
389 | * The callback will be registered by @ref ixParityENAccCallbackRegister. | |
390 | * | |
391 | * It will be called from an ISR when a parity error is detected and thus | |
392 | * needs to follow the interrupt callable function conventions. | |
393 | * | |
394 | */ | |
395 | typedef void (*IxParityENAccCallback) (void); | |
396 | ||
397 | ||
398 | /* | |
399 | * Prototypes for interface functions. | |
400 | */ | |
401 | ||
402 | /** | |
403 | * @ingroup IxParityENAcc | |
404 | * | |
405 | * @fn IxParityENAccStatus ixParityENAccInit(void) | |
406 | * | |
407 | * @brief This function will initialise the IxParityENAcc component. | |
408 | * | |
409 | * This function will initialise the IxParityENAcc component. It should only be | |
410 | * called once, prior to using the IxParityENAcc component. | |
411 | * | |
412 | * <OL><LI>It initialises the internal data structures, registers the ISR that | |
413 | * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL> | |
414 | * | |
415 | * @li Re-entrant : No | |
416 | * @li ISR Callable : No | |
417 | * | |
418 | * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful | |
419 | * @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already | |
420 | * been initialized | |
421 | * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the | |
422 | * operation didn't succeed on the hardware. Refer to error trace/log | |
423 | * for details. | |
424 | */ | |
425 | ||
426 | PUBLIC IxParityENAccStatus ixParityENAccInit(void); | |
427 | ||
428 | /** | |
429 | * @ingroup IxParityENAcc | |
430 | * | |
431 | * @fn IxParityENAccStatus ixParityENAccCallbackRegister ( | |
432 | IxParityENAccCallback parityErrNfyCallBack) | |
433 | * | |
434 | * @brief This function will register a new callback with IxParityENAcc component. | |
435 | * It can also reregister a new callback replacing the old callback. | |
436 | * | |
437 | * @param parityErrNfyCallBack [in] - This parameter will specify the call-back | |
438 | * function supplied by the client application. | |
439 | * | |
440 | * This interface registers the user application supplied call-back handler with | |
441 | * the parity error handling access component after the init. | |
442 | * | |
443 | * The callback function will be called from an ISR that will be triggered by the | |
444 | * parity error in the IXP400 silicon. | |
445 | * | |
446 | * The following actions will be performed by this function: | |
447 | * <OL><LI>Check for the prior initialisation of the module before registering or | |
448 | * re-registering of the callback. | |
449 | * Check for parity error detection disabled before re-registration of the callback. | |
450 | * </LI></OL> | |
451 | * | |
452 | * @li Re-entrant : No | |
453 | * @li ISR Callable : No | |
454 | * | |
455 | * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the | |
456 | * registration is successful. | |
457 | * @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL | |
458 | * parameter passed. | |
459 | * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the | |
460 | * parity error detection not yet disabled. | |
461 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to | |
462 | * the initialisation of the access layer. | |
463 | */ | |
464 | ||
465 | PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister ( | |
466 | IxParityENAccCallback parityErrNfyCallBack); | |
467 | ||
468 | /** | |
469 | * @ingroup IxParityENAcc | |
470 | * | |
471 | * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure ( | |
472 | const IxParityENAccHWParityConfig *hwParityConfig) | |
473 | * | |
474 | * @brief This interface allows the client application to enable the parity | |
475 | * error detection on the underlying hardware block. | |
476 | * | |
477 | * @param hwParityConfig [in] - Hardware blocks for which the parity error | |
478 | * detection is to be enabled or disabled. | |
479 | * | |
480 | * The client application allocates and provides the reference to the buffer. | |
481 | * | |
482 | * It will also verify whether the specific hardware block is functional or not. | |
483 | * | |
484 | * NOTE: Failure in enabling or disabling of one or more components result in | |
485 | * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function | |
486 | * @ref ixParityENAccParityDetectionQuery on how to verify the failures while | |
487 | * enabling/disabling paritys error detection. | |
488 | * | |
489 | * It shall be invoked after the Init and CallbackRegister functions but before | |
490 | * any other function of the IxParityENAcc layer. | |
491 | * | |
492 | * @li Re-entrant : No | |
493 | * @li ISR Callable : No | |
494 | * | |
495 | * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the | |
496 | * request to enable/disable is successful. | |
497 | * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to | |
498 | * NULL parameter supplied. | |
499 | * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the | |
500 | * operation didn't succeed on the hardware. | |
501 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to | |
502 | * the initialisation of the access layer. | |
503 | */ | |
504 | ||
505 | PUBLIC IxParityENAccStatus ixParityENAccParityDetectionConfigure ( | |
506 | const IxParityENAccHWParityConfig *hwParityConfig); | |
507 | ||
508 | /** | |
509 | * @ingroup IxParityENAcc | |
510 | * | |
511 | * @fn IxParityENAccStatus ixParityENAccParityDetectionQuery ( | |
512 | IxParityENAccHWParityConfig * const hwParityConfig) | |
513 | * | |
514 | * @brief This interface allows the client application to determine the | |
515 | * status of the parity error detection on the specified hardware blocks | |
516 | * | |
517 | * @param hwParityConfig [out] - Hardware blocks whose parity error detection | |
518 | * has been enabled or disabled. | |
519 | * | |
520 | * The client application allocates and provides the reference to the buffer. | |
521 | * | |
522 | * This interface can be used immediately after the interface @ref | |
523 | * ixParityENAccParityDetectionConfigure to see on which of the hardware blocks | |
524 | * the parity error detection has either been enabled or disabled based on the | |
525 | * client application request. | |
526 | * | |
527 | * @li Re-entrant : No | |
528 | * @li ISR Callable : No | |
529 | * | |
530 | * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the | |
531 | * request to query on whether the hardware parity error detection | |
532 | * is enabled or disabled is successful. | |
533 | * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to | |
534 | * NULL parameter or invalid values supplied. | |
535 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior | |
536 | * to the initialisation of the access layer. | |
537 | */ | |
538 | ||
539 | PUBLIC IxParityENAccStatus ixParityENAccParityDetectionQuery( | |
540 | IxParityENAccHWParityConfig * const hwParityConfig); | |
541 | ||
542 | /** | |
543 | * @ingroup IxParityENAcc | |
544 | * | |
545 | * @fn IxParityENAccStatus ixParityENAccParityErrorContextGet( | |
546 | IxParityENAccParityErrorContextMessage * const pecMessage) | |
547 | * | |
548 | * @brief This interface allows the client application to determine the | |
549 | * status of the parity error context on hardware block for which the | |
550 | * current parity error interrupt triggered. | |
551 | * | |
552 | * @param pecMessage [out] - The parity error context information of the | |
553 | * parity interrupt currently being process. | |
554 | * | |
555 | * The client application allocates and provides the reference to the buffer. | |
556 | * | |
557 | * Refer to the data structure @ref IxParityENAccParityErrorContextMessage | |
558 | * for details. | |
559 | * | |
560 | * The routine will will fetch the parity error context in the following | |
561 | * priority, if multiple parity errors observed. | |
562 | * | |
563 | * <pre> | |
564 | * 0 - MCU (Multi-bit and single-bit in that order) | |
565 | * 1 - NPE-A | |
566 | * 2 - NPE-B | |
567 | * 3 - NPE-C | |
568 | * 4 - SWCP | |
569 | * 5 - QM | |
570 | * 6 - EXP | |
571 | * | |
572 | * NOTE: The information provided in the @ref IxParityENAccAHBErrorTransaction | |
573 | * may be of help for the client application to decide on the course of action | |
574 | * to take. This info is taken from the Performance Monitoring Unit register | |
575 | * which records most recent error observed on the AHB bus. This information | |
576 | * might have been overwritten by some other error by the time it is retrieved. | |
577 | * </pre> | |
578 | * | |
579 | * @li Re-entrant : No | |
580 | * @li ISR Callable : Yes | |
581 | * | |
582 | * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the | |
583 | * request to get the parity error context information is successful. | |
584 | * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to | |
585 | * NULL parameter is passed | |
586 | * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because | |
587 | * the operation didn't succeed on the hardware. | |
588 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior | |
589 | * to the initialisation of the access layer. | |
590 | * @li IX_PARITYENACC_NO_PARITY - No parity condition exits or has | |
591 | * already been cleared | |
592 | */ | |
593 | ||
594 | PUBLIC IxParityENAccStatus ixParityENAccParityErrorContextGet( | |
595 | IxParityENAccParityErrorContextMessage * const pecMessage); | |
596 | ||
597 | /** | |
598 | * @ingroup IxParityENAcc | |
599 | * | |
600 | * @fn IxParityENAccStatus ixParityENAccParityErrorInterruptClear ( | |
601 | const IxParityENAccParityErrorContextMessage *pecMessage) | |
602 | * | |
603 | * @brief This interface helps the client application to clear off the | |
604 | * interrupt condition on the hardware block identified in the parity | |
605 | * error context message. Please refer to the table below as the operation | |
606 | * varies depending on the interrupt source. | |
607 | * | |
608 | * @param pecMessage [in] - The parity error context information of the | |
609 | * hardware block whose parity error interrupt condition is to disabled. | |
610 | * | |
611 | * The client application allocates and provides the reference to the buffer. | |
612 | * | |
613 | * <pre> | |
614 | * **************************************************************************** | |
615 | * Following actions will be taken during the interrupt clear for respective | |
616 | * hardware blocks. | |
617 | * | |
618 | * Parity Source Actions taken during Interrupt clear | |
619 | * ------------- ------------------------------------------------------- | |
620 | * NPE-A Interrupt will be masked off at the interrupt controller | |
621 | * so that it will not trigger continuously. | |
622 | * Client application has to take appropriate action and | |
623 | * re-configure the parity error detection subsequently. | |
624 | * The client application will not be notified of further | |
625 | * interrupts, until the re-configuration is done using | |
626 | * @ref ixParityENAccParityDetectionConfigure. | |
627 | * | |
628 | * NPE-B Interrupt will be masked off at the interrupt controller | |
629 | * so that it will not trigger continuously. | |
630 | * Client application has to take appropriate action and | |
631 | * re-configure the parity error detection subsequently. | |
632 | * The client application will not be notified of further | |
633 | * interrupts, until the re-configuration is done using | |
634 | * @ref ixParityENAccParityDetectionConfigure. | |
635 | * | |
636 | * NPE-C Interrupt will be masked off at the interrupt controller | |
637 | * Client application has to take appropriate action and | |
638 | * re-configure the parity error detection subsequently. | |
639 | * The client application will not be notified of further | |
640 | * interrupts, until the re-configuration is done using | |
641 | * @ref ixParityENAccParityDetectionConfigure. | |
642 | * | |
643 | * SWCP Interrupt will be masked off at the interrupt controller. | |
644 | * Client application has to take appropriate action and | |
645 | * re-configure the parity error detection subsequently. | |
646 | * The client application will not be notified of further | |
647 | * interrupts, until the re-configuration is done using | |
648 | * @ref ixParityENAccParityDetectionConfigure. | |
649 | * | |
650 | * AQM Interrupt will be masked off at the interrupt controller. | |
651 | * Client application has to take appropriate action and | |
652 | * re-configure the parity error detection subsequently. | |
653 | * The client application will not be notified of further | |
654 | * interrupts, until the re-configuration is done using | |
655 | * @ref ixParityENAccParityDetectionConfigure. | |
656 | * | |
657 | * MCU Parity interrupt condition is cleared at the SDRAM MCU for | |
658 | * the following: | |
659 | * 1. Single-bit | |
660 | * 2. Multi-bit | |
661 | * 3. Overflow condition i.e., more than two parity conditions | |
662 | * occurred | |
663 | * Note that single-parity errors do not result in data abort | |
664 | * and not all data aborts caused by multi-bit parity error. | |
665 | * | |
666 | * EXP Parity interrupt condition is cleared at the expansion bus | |
667 | * controller for the following: | |
668 | * 1. External master initiated Inbound write | |
669 | * 2. Internal master (IXP400) initiated Outbound read | |
670 | * **************************************************************************** | |
671 | * </pre> | |
672 | * @li Re-entrant : No | |
673 | * @li ISR Callable : No | |
674 | * | |
675 | * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the request | |
676 | * to clear the parity error interrupt condition is successful. | |
677 | * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to | |
678 | * NULL parameters have been passed or contents have been | |
679 | * supplied with invalid values. | |
680 | * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because | |
681 | * the operation didn't succeed on the hardware. | |
682 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior | |
683 | * to the initialisation of the access layer. | |
684 | */ | |
685 | ||
686 | PUBLIC IxParityENAccStatus ixParityENAccParityErrorInterruptClear ( | |
687 | const IxParityENAccParityErrorContextMessage *pecMessage); | |
688 | ||
689 | /** | |
690 | * @ingroup IxParityENAcc | |
691 | * | |
692 | * @fn IxParityENAccStatus ixParityENAccStatsGet ( | |
693 | IxParityENAccParityErrorStats * const ixParityErrorStats) | |
694 | * | |
695 | * @brief This interface allows the client application to retrieve parity | |
696 | * error statistics for all the hardware blocks | |
697 | * | |
698 | * @param ixParityErrorStats - [out] The statistics for all the hardware blocks. | |
699 | * | |
700 | * The client application allocates and provides the reference to the buffer. | |
701 | * | |
702 | * @li Re-entrant : No | |
703 | * @li ISR Callable : Yes | |
704 | * | |
705 | * @return @li IX_PARITYENACC_SUCCESS-The parameters check passed and the | |
706 | * request to retrieve parity error statistics for the hardware | |
707 | * block is successful. | |
708 | * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to a | |
709 | * NULL parameter passed. | |
710 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior | |
711 | * to the initialisation of the access layer. | |
712 | */ | |
713 | ||
714 | PUBLIC IxParityENAccStatus ixParityENAccStatsGet ( | |
715 | IxParityENAccParityErrorStats * const ixParityErrorStats); | |
716 | ||
717 | /** | |
718 | * @ingroup IxParityENAcc | |
719 | * | |
720 | * @fn IxParityENAccStatus ixParityENAccStatsShow (void) | |
721 | * | |
722 | * @brief This interface allows the client application to print all the | |
723 | * parity error statistics. | |
724 | * | |
725 | * @li Re-entrant : No | |
726 | * @li ISR Callable : No | |
727 | * | |
728 | * @return @li IX_PARITYENACC_SUCCESS - The request to show the pairty | |
729 | * error statistics is successful. | |
730 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested | |
731 | * prior to the initialisation of the access layer. | |
732 | */ | |
733 | ||
734 | PUBLIC IxParityENAccStatus ixParityENAccStatsShow (void); | |
735 | ||
736 | /** | |
737 | * @ingroup IxParityENAcc | |
738 | * | |
739 | * @fn IxParityENAccStatus ixParityENAccStatsReset (void) | |
740 | * | |
741 | * @brief This interface allows the client application to reset all the | |
742 | * parity error statistics. | |
743 | * | |
744 | * @li Re-entrant : No | |
745 | * @li ISR Callable : No | |
746 | * | |
747 | * @return @li IX_PARITYENACC_SUCCESS - The request to reset the parity | |
748 | * error statistics is successful. | |
749 | * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested | |
750 | * prior to the initialisation of the access layer. | |
751 | */ | |
752 | ||
753 | PUBLIC IxParityENAccStatus ixParityENAccStatsReset (void); | |
754 | ||
755 | #endif /* IXPARITYENACC_H */ | |
756 | #endif /* __ixp46X */ | |
757 | ||
758 | /** | |
759 | * @} defgroup IxParityENAcc | |
760 | */ | |
761 |