projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
| 2 | . smc91111.h - macros for the LAN91C111 Ethernet Driver | |
| 3 | . | |
| 4 | . (C) Copyright 2002 | |
| 5 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| 6 | . Rolf Offermanns <rof@sysgo.de> | |
| 7 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
| 8 | . Developed by Simple Network Magic Corporation (SNMC) | |
| 9 | . Copyright (C) 1996 by Erik Stahlman (ES) | |
| 10 | . | |
| 11 | . This program is free software; you can redistribute it and/or modify | |
| 12 | . it under the terms of the GNU General Public License as published by | |
| 13 | . the Free Software Foundation; either version 2 of the License, or | |
| 14 | . (at your option) any later version. | |
| 15 | . | |
| 16 | . This program is distributed in the hope that it will be useful, | |
| 17 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | . GNU General Public License for more details. | |
| 20 | . | |
| 21 | . You should have received a copy of the GNU General Public License | |
| 22 | . along with this program; if not, write to the Free Software | |
| 23 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 24 | . | |
| 25 | . This file contains register information and access macros for | |
| 26 | . the LAN91C111 single chip ethernet controller. It is a modified | |
| 27 | . version of the smc9194.h file. | |
| 28 | . | |
| 29 | . Information contained in this file was obtained from the LAN91C111 | |
| 30 | . manual from SMC. To get a copy, if you really want one, you can find | |
| 31 | . information under www.smsc.com. | |
| 32 | . | |
| 33 | . Authors | |
| 53677ef1 | 34 | . Erik Stahlman ( erik@vt.edu ) |
| fe8c2806 WD |
35 | . Daris A Nevil ( dnevil@snmc.com ) |
| 36 | . | |
| 37 | . History | |
| 38 | . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device | |
| 39 | . | |
| 40 | ---------------------------------------------------------------------------*/ | |
| 41 | #ifndef _SMC91111_H_ | |
| 42 | #define _SMC91111_H_ | |
| 43 | ||
| 44 | #include <asm/types.h> | |
| 45 | #include <config.h> | |
| 46 | ||
| 47 | /* | |
| 48 | * This function may be called by the board specific initialisation code | |
| 49 | * in order to override the default mac address. | |
| 50 | */ | |
| 51 | ||
| d52fb7e3 | 52 | void smc_set_mac_addr (const unsigned char *addr); |
| fe8c2806 WD |
53 | |
| 54 | ||
| 55 | /* I want some simple types */ | |
| 56 | ||
| 57 | typedef unsigned char byte; | |
| 58 | typedef unsigned short word; | |
| 53677ef1 | 59 | typedef unsigned long int dword; |
| fe8c2806 WD |
60 | |
| 61 | /* | |
| 62 | . DEBUGGING LEVELS | |
| 63 | . | |
| 64 | . 0 for normal operation | |
| 65 | . 1 for slightly more details | |
| 66 | . >2 for various levels of increasingly useless information | |
| 67 | . 2 for interrupt tracking, status flags | |
| 68 | . 3 for packet info | |
| 69 | . 4 for complete packet dumps | |
| 70 | */ | |
| 71 | /*#define SMC_DEBUG 0 */ | |
| 72 | ||
| 73 | /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ | |
| 74 | ||
| 75 | #define SMC_IO_EXTENT 16 | |
| 76 | ||
| 77 | #ifdef CONFIG_PXA250 | |
| 78 | ||
| ca0e7748 | 79 | #ifdef CONFIG_XSENGINE |
| 53677ef1 WD |
80 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) |
| 81 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) | |
| 3eac6402 | 82 | #define SMC_inb(p) ({ \ |
| ca0e7748 WD |
83 | unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ |
| 84 | unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ | |
| 85 | if (__p & 2) __v >>= 8; \ | |
| 86 | else __v &= 0xff; \ | |
| 87 | __v; }) | |
| 1f6d4258 WD |
88 | #elif defined(CONFIG_XAENIAX) |
| 89 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) | |
| 90 | #define SMC_inw(z) ({ \ | |
| 91 | unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ | |
| 92 | unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ | |
| 93 | if (__p & 3) __v >>= 16; \ | |
| 94 | else __v &= 0xffff; \ | |
| 95 | __v; }) | |
| 96 | #define SMC_inb(p) ({ \ | |
| 97 | unsigned int ___v = SMC_inw((p) & ~1); \ | |
| 98 | if (p & 1) ___v >>= 8; \ | |
| 99 | else ___v &= 0xff; \ | |
| 100 | ___v; }) | |
| ca0e7748 | 101 | #else |
| 53677ef1 WD |
102 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) |
| 103 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) | |
| fe8c2806 WD |
104 | #define SMC_inb(p) ({ \ |
| 105 | unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ | |
| 487778b7 | 106 | unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ |
| fe8c2806 WD |
107 | if (__p & 1) __v >>= 8; \ |
| 108 | else __v &= 0xff; \ | |
| 109 | __v; }) | |
| ca0e7748 | 110 | #endif |
| fe8c2806 | 111 | |
| ca0e7748 WD |
112 | #ifdef CONFIG_XSENGINE |
| 113 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) | |
| 114 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) | |
| 1f6d4258 WD |
115 | #elif defined (CONFIG_XAENIAX) |
| 116 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) | |
| 117 | #define SMC_outw(d,p) ({ \ | |
| 118 | dword __dwo = SMC_inl((p) & ~3); \ | |
| 119 | dword __dwn = (word)(d); \ | |
| 120 | __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ | |
| 121 | __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ | |
| 122 | SMC_outl(__dwo, (p) & ~3); \ | |
| 123 | }) | |
| ca0e7748 | 124 | #else |
| fe8c2806 WD |
125 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) |
| 126 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) | |
| ca0e7748 WD |
127 | #endif |
| 128 | ||
| fe8c2806 WD |
129 | #define SMC_outb(d,r) ({ word __d = (byte)(d); \ |
| 130 | word __w = SMC_inw((r)&~1); \ | |
| 131 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ | |
| 132 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
| 133 | SMC_outw(__w,(r)&~1); \ | |
| 134 | }) | |
| 135 | ||
| 136 | #define SMC_outsl(r,b,l) ({ int __i; \ | |
| 137 | dword *__b2; \ | |
| 138 | __b2 = (dword *) b; \ | |
| 139 | for (__i = 0; __i < l; __i++) { \ | |
| 140 | SMC_outl( *(__b2 + __i), r); \ | |
| 141 | } \ | |
| 142 | }) | |
| 143 | ||
| 144 | #define SMC_outsw(r,b,l) ({ int __i; \ | |
| 145 | word *__b2; \ | |
| 146 | __b2 = (word *) b; \ | |
| 147 | for (__i = 0; __i < l; __i++) { \ | |
| 148 | SMC_outw( *(__b2 + __i), r); \ | |
| 149 | } \ | |
| 150 | }) | |
| 151 | ||
| 53677ef1 | 152 | #define SMC_insl(r,b,l) ({ int __i ; \ |
| fe8c2806 | 153 | dword *__b2; \ |
| 53677ef1 WD |
154 | __b2 = (dword *) b; \ |
| 155 | for (__i = 0; __i < l; __i++) { \ | |
| fe8c2806 WD |
156 | *(__b2 + __i) = SMC_inl(r); \ |
| 157 | SMC_inl(0); \ | |
| 158 | }; \ | |
| 159 | }) | |
| 160 | ||
| 53677ef1 | 161 | #define SMC_insw(r,b,l) ({ int __i ; \ |
| fe8c2806 | 162 | word *__b2; \ |
| 53677ef1 WD |
163 | __b2 = (word *) b; \ |
| 164 | for (__i = 0; __i < l; __i++) { \ | |
| fe8c2806 WD |
165 | *(__b2 + __i) = SMC_inw(r); \ |
| 166 | SMC_inw(0); \ | |
| 167 | }; \ | |
| 168 | }) | |
| 169 | ||
| 53677ef1 | 170 | #define SMC_insb(r,b,l) ({ int __i ; \ |
| fe8c2806 | 171 | byte *__b2; \ |
| 53677ef1 WD |
172 | __b2 = (byte *) b; \ |
| 173 | for (__i = 0; __i < l; __i++) { \ | |
| fe8c2806 WD |
174 | *(__b2 + __i) = SMC_inb(r); \ |
| 175 | SMC_inb(0); \ | |
| 176 | }; \ | |
| 177 | }) | |
| 178 | ||
| 3eac6402 DH |
179 | #elif defined(CONFIG_LEON) /* if not CONFIG_PXA250 */ |
| 180 | ||
| 181 | #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) | |
| 182 | ||
| 183 | #define SMC_LEON_SWAP32(_x_) \ | |
| 184 | ({ dword _x = (_x_); \ | |
| 185 | ((_x << 24) | \ | |
| 186 | ((0x0000FF00UL & _x) << 8) | \ | |
| 187 | ((0x00FF0000UL & _x) >> 8) | \ | |
| 188 | (_x >> 24)); }) | |
| 189 | ||
| 53677ef1 WD |
190 | #define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))) |
| 191 | #define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))) | |
| 192 | #define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))) | |
| 193 | #define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))) | |
| 3eac6402 DH |
194 | #define SMC_inb(p) ({ \ |
| 195 | word ___v = SMC_inw((p) & ~1); \ | |
| 196 | if ((p) & 1) ___v >>= 8; \ | |
| 197 | else ___v &= 0xff; \ | |
| 198 | ___v; }) | |
| 199 | ||
| 200 | #define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d)) | |
| 201 | #define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) | |
| 202 | #define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d)) | |
| 203 | #define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) | |
| 204 | #define SMC_outb(d,r) do{ word __d = (byte)(d); \ | |
| 205 | word __w = SMC_inw((r)&~1); \ | |
| 206 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ | |
| 207 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
| 208 | SMC_outw(__w,(r)&~1); \ | |
| 209 | }while(0) | |
| 210 | #define SMC_outsl(r,b,l) do{ int __i; \ | |
| 211 | dword *__b2; \ | |
| 212 | __b2 = (dword *) b; \ | |
| 213 | for (__i = 0; __i < l; __i++) { \ | |
| 214 | SMC_outl_nosw( *(__b2 + __i), r); \ | |
| 215 | } \ | |
| 216 | }while(0) | |
| 217 | #define SMC_outsw(r,b,l) do{ int __i; \ | |
| 218 | word *__b2; \ | |
| 219 | __b2 = (word *) b; \ | |
| 220 | for (__i = 0; __i < l; __i++) { \ | |
| 221 | SMC_outw_nosw( *(__b2 + __i), r); \ | |
| 222 | } \ | |
| 223 | }while(0) | |
| 53677ef1 | 224 | #define SMC_insl(r,b,l) do{ int __i ; \ |
| 3eac6402 DH |
225 | dword *__b2; \ |
| 226 | __b2 = (dword *) b; \ | |
| 227 | for (__i = 0; __i < l; __i++) { \ | |
| 228 | *(__b2 + __i) = SMC_inl_nosw(r); \ | |
| 229 | }; \ | |
| 230 | }while(0) | |
| 231 | ||
| 53677ef1 | 232 | #define SMC_insw(r,b,l) do{ int __i ; \ |
| 3eac6402 DH |
233 | word *__b2; \ |
| 234 | __b2 = (word *) b; \ | |
| 235 | for (__i = 0; __i < l; __i++) { \ | |
| 236 | *(__b2 + __i) = SMC_inw_nosw(r); \ | |
| 237 | }; \ | |
| 238 | }while(0) | |
| 239 | ||
| 53677ef1 | 240 | #define SMC_insb(r,b,l) do{ int __i ; \ |
| 3eac6402 DH |
241 | byte *__b2; \ |
| 242 | __b2 = (byte *) b; \ | |
| 243 | for (__i = 0; __i < l; __i++) { \ | |
| 244 | *(__b2 + __i) = SMC_inb(r); \ | |
| 245 | }; \ | |
| 246 | }while(0) | |
| 247 | ||
| 248 | #else /* if not CONFIG_PXA250 and not CONFIG_LEON */ | |
| fe8c2806 | 249 | |
| c3c7f861 | 250 | #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ |
| fe8c2806 WD |
251 | /* |
| 252 | * We have only 16 Bit PCMCIA access on Socket 0 | |
| 253 | */ | |
| 254 | ||
| aaf224ab | 255 | #ifdef CONFIG_ADNPESC1 |
| 53677ef1 | 256 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) |
| 0afe519a | 257 | #elif CONFIG_BLACKFIN |
| 53677ef1 | 258 | #define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;}) |
| aaf224ab | 259 | #else |
| 53677ef1 | 260 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) |
| aaf224ab | 261 | #endif |
| fe8c2806 WD |
262 | #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) |
| 263 | ||
| aaf224ab WD |
264 | #ifdef CONFIG_ADNPESC1 |
| 265 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) | |
| 0afe519a | 266 | #elif CONFIG_BLACKFIN |
| 8a30b470 | 267 | #define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();} |
| aaf224ab | 268 | #else |
| fe8c2806 | 269 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) |
| aaf224ab | 270 | #endif |
| fe8c2806 WD |
271 | #define SMC_outb(d,r) ({ word __d = (byte)(d); \ |
| 272 | word __w = SMC_inw((r)&~1); \ | |
| 273 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ | |
| 274 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
| 275 | SMC_outw(__w,(r)&~1); \ | |
| 276 | }) | |
| 277 | #if 0 | |
| 278 | #define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) | |
| 279 | #else | |
| 280 | #define SMC_outsw(r,b,l) ({ int __i; \ | |
| 281 | word *__b2; \ | |
| 282 | __b2 = (word *) b; \ | |
| 283 | for (__i = 0; __i < l; __i++) { \ | |
| 284 | SMC_outw( *(__b2 + __i), r); \ | |
| 285 | } \ | |
| 286 | }) | |
| 287 | #endif | |
| 288 | ||
| 289 | #if 0 | |
| 53677ef1 | 290 | #define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) |
| fe8c2806 | 291 | #else |
| 53677ef1 | 292 | #define SMC_insw(r,b,l) ({ int __i ; \ |
| fe8c2806 | 293 | word *__b2; \ |
| 53677ef1 WD |
294 | __b2 = (word *) b; \ |
| 295 | for (__i = 0; __i < l; __i++) { \ | |
| fe8c2806 WD |
296 | *(__b2 + __i) = SMC_inw(r); \ |
| 297 | SMC_inw(0); \ | |
| 298 | }; \ | |
| 299 | }) | |
| 300 | #endif | |
| 301 | ||
| c3c7f861 WD |
302 | #endif /* CONFIG_SMC_USE_IOFUNCS */ |
| 303 | ||
| a3ad8e26 WD |
304 | #if defined(CONFIG_SMC_USE_32_BIT) |
| 305 | ||
| ca0e7748 | 306 | #ifdef CONFIG_XSENGINE |
| 53677ef1 | 307 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) |
| ca0e7748 | 308 | #else |
| 53677ef1 | 309 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) |
| ca0e7748 | 310 | #endif |
| a3ad8e26 | 311 | |
| 53677ef1 | 312 | #define SMC_insl(r,b,l) ({ int __i ; \ |
| a3ad8e26 | 313 | dword *__b2; \ |
| 53677ef1 WD |
314 | __b2 = (dword *) b; \ |
| 315 | for (__i = 0; __i < l; __i++) { \ | |
| a3ad8e26 WD |
316 | *(__b2 + __i) = SMC_inl(r); \ |
| 317 | SMC_inl(0); \ | |
| 318 | }; \ | |
| 319 | }) | |
| 320 | ||
| ca0e7748 WD |
321 | #ifdef CONFIG_XSENGINE |
| 322 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) | |
| 323 | #else | |
| a3ad8e26 | 324 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) |
| ca0e7748 | 325 | #endif |
| a3ad8e26 WD |
326 | #define SMC_outsl(r,b,l) ({ int __i; \ |
| 327 | dword *__b2; \ | |
| 328 | __b2 = (dword *) b; \ | |
| 329 | for (__i = 0; __i < l; __i++) { \ | |
| 330 | SMC_outl( *(__b2 + __i), r); \ | |
| 331 | } \ | |
| 332 | }) | |
| 333 | ||
| 334 | #endif /* CONFIG_SMC_USE_32_BIT */ | |
| 335 | ||
| fe8c2806 WD |
336 | #endif |
| 337 | ||
| 338 | /*--------------------------------------------------------------- | |
| 339 | . | |
| 340 | . A description of the SMSC registers is probably in order here, | |
| 341 | . although for details, the SMC datasheet is invaluable. | |
| 342 | . | |
| 343 | . Basically, the chip has 4 banks of registers ( 0 to 3 ), which | |
| 344 | . are accessed by writing a number into the BANK_SELECT register | |
| 345 | . ( I also use a SMC_SELECT_BANK macro for this ). | |
| 346 | . | |
| 347 | . The banks are configured so that for most purposes, bank 2 is all | |
| 348 | . that is needed for simple run time tasks. | |
| 349 | -----------------------------------------------------------------------*/ | |
| 350 | ||
| 351 | /* | |
| 352 | . Bank Select Register: | |
| 353 | . | |
| 354 | . yyyy yyyy 0000 00xx | |
| 53677ef1 | 355 | . xx = bank number |
| fe8c2806 WD |
356 | . yyyy yyyy = 0x33, for identification purposes. |
| 357 | */ | |
| 358 | #define BANK_SELECT 14 | |
| 359 | ||
| 360 | /* Transmit Control Register */ | |
| 361 | /* BANK 0 */ | |
| 53677ef1 | 362 | #define TCR_REG 0x0000 /* transmit control register */ |
| fe8c2806 WD |
363 | #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ |
| 364 | #define TCR_LOOP 0x0002 /* Controls output pin LBK */ | |
| 365 | #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ | |
| 366 | #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ | |
| 367 | #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ | |
| 368 | #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ | |
| 53677ef1 | 369 | #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ |
| fe8c2806 WD |
370 | #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ |
| 371 | #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ | |
| 372 | #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ | |
| 373 | ||
| 374 | #define TCR_CLEAR 0 /* do NOTHING */ | |
| 375 | /* the default settings for the TCR register : */ | |
| 376 | /* QUESTION: do I want to enable padding of short packets ? */ | |
| 53677ef1 | 377 | #define TCR_DEFAULT TCR_ENABLE |
| fe8c2806 WD |
378 | |
| 379 | ||
| 380 | /* EPH Status Register */ | |
| 381 | /* BANK 0 */ | |
| 382 | #define EPH_STATUS_REG 0x0002 | |
| 383 | #define ES_TX_SUC 0x0001 /* Last TX was successful */ | |
| 384 | #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ | |
| 385 | #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ | |
| 386 | #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ | |
| 387 | #define ES_16COL 0x0010 /* 16 Collisions Reached */ | |
| 388 | #define ES_SQET 0x0020 /* Signal Quality Error Test */ | |
| 389 | #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ | |
| 390 | #define ES_TXDEFR 0x0080 /* Transmit Deferred */ | |
| 391 | #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ | |
| 392 | #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ | |
| 393 | #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ | |
| 394 | #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ | |
| 395 | #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ | |
| 396 | #define ES_TXUNRN 0x8000 /* Tx Underrun */ | |
| 397 | ||
| 398 | ||
| 399 | /* Receive Control Register */ | |
| 400 | /* BANK 0 */ | |
| 401 | #define RCR_REG 0x0004 | |
| 402 | #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ | |
| 403 | #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ | |
| 404 | #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ | |
| 405 | #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ | |
| 406 | #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ | |
| 407 | #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ | |
| 408 | #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ | |
| 53677ef1 | 409 | #define RCR_SOFTRST 0x8000 /* resets the chip */ |
| fe8c2806 WD |
410 | |
| 411 | /* the normal settings for the RCR register : */ | |
| 412 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
| 413 | #define RCR_CLEAR 0x0 /* set it to a base state */ | |
| 414 | ||
| 415 | /* Counter Register */ | |
| 416 | /* BANK 0 */ | |
| 417 | #define COUNTER_REG 0x0006 | |
| 418 | ||
| 419 | /* Memory Information Register */ | |
| 420 | /* BANK 0 */ | |
| 421 | #define MIR_REG 0x0008 | |
| 422 | ||
| 423 | /* Receive/Phy Control Register */ | |
| 424 | /* BANK 0 */ | |
| 425 | #define RPC_REG 0x000A | |
| 426 | #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ | |
| 427 | #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ | |
| 428 | #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ | |
| 429 | #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ | |
| 430 | #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ | |
| 431 | #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ | |
| 432 | #define RPC_LED_RES (0x01) /* LED = Reserved */ | |
| 433 | #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ | |
| 434 | #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ | |
| 435 | #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ | |
| 436 | #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ | |
| 437 | #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ | |
| 438 | #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ | |
| c935d3bd | 439 | #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) |
| 8bf3b005 | 440 | /* buggy schematic: LEDa -> yellow, LEDb --> green */ |
| aaf224ab WD |
441 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ |
| 442 | | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | |
| 443 | | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) | |
| 444 | #elif defined(CONFIG_ADNPESC1) | |
| 445 | /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ | |
| 8bf3b005 WD |
446 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ |
| 447 | | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | |
| 448 | | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) | |
| 449 | #else | |
| 450 | /* SMSC reference design: LEDa --> green, LEDb --> yellow */ | |
| 451 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ | |
| 452 | | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ | |
| 453 | | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) | |
| 454 | #endif | |
| fe8c2806 WD |
455 | |
| 456 | /* Bank 0 0x000C is reserved */ | |
| 457 | ||
| 458 | /* Bank Select Register */ | |
| 459 | /* All Banks */ | |
| 460 | #define BSR_REG 0x000E | |
| 461 | ||
| 462 | ||
| 463 | /* Configuration Reg */ | |
| 464 | /* BANK 1 */ | |
| 465 | #define CONFIG_REG 0x0000 | |
| 466 | #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ | |
| 467 | #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ | |
| 468 | #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ | |
| 469 | #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ | |
| 470 | ||
| 471 | /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ | |
| 472 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
| 473 | ||
| 474 | ||
| 475 | /* Base Address Register */ | |
| 476 | /* BANK 1 */ | |
| 477 | #define BASE_REG 0x0002 | |
| 478 | ||
| 479 | ||
| 480 | /* Individual Address Registers */ | |
| 481 | /* BANK 1 */ | |
| 482 | #define ADDR0_REG 0x0004 | |
| 483 | #define ADDR1_REG 0x0006 | |
| 484 | #define ADDR2_REG 0x0008 | |
| 485 | ||
| 486 | ||
| 487 | /* General Purpose Register */ | |
| 488 | /* BANK 1 */ | |
| 489 | #define GP_REG 0x000A | |
| 490 | ||
| 491 | ||
| 492 | /* Control Register */ | |
| 493 | /* BANK 1 */ | |
| 494 | #define CTL_REG 0x000C | |
| 495 | #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ | |
| 496 | #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ | |
| 497 | #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ | |
| 498 | #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ | |
| 499 | #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ | |
| 500 | #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ | |
| 501 | #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ | |
| 502 | #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ | |
| 518e2e1a | 503 | #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ |
| fe8c2806 WD |
504 | |
| 505 | /* MMU Command Register */ | |
| 506 | /* BANK 2 */ | |
| 507 | #define MMU_CMD_REG 0x0000 | |
| 508 | #define MC_BUSY 1 /* When 1 the last release has not completed */ | |
| 509 | #define MC_NOP (0<<5) /* No Op */ | |
| 53677ef1 | 510 | #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ |
| fe8c2806 | 511 | #define MC_RESET (2<<5) /* Reset MMU to initial state */ |
| 53677ef1 WD |
512 | #define MC_REMOVE (3<<5) /* Remove the current rx packet */ |
| 513 | #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ | |
| 514 | #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ | |
| fe8c2806 WD |
515 | #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ |
| 516 | #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ | |
| 517 | ||
| 518 | ||
| 519 | /* Packet Number Register */ | |
| 520 | /* BANK 2 */ | |
| 521 | #define PN_REG 0x0002 | |
| 522 | ||
| 523 | ||
| 524 | /* Allocation Result Register */ | |
| 525 | /* BANK 2 */ | |
| 526 | #define AR_REG 0x0003 | |
| 527 | #define AR_FAILED 0x80 /* Alocation Failed */ | |
| 528 | ||
| 529 | ||
| 530 | /* RX FIFO Ports Register */ | |
| 531 | /* BANK 2 */ | |
| 532 | #define RXFIFO_REG 0x0004 /* Must be read as a word */ | |
| 533 | #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ | |
| 534 | ||
| 535 | ||
| 536 | /* TX FIFO Ports Register */ | |
| 537 | /* BANK 2 */ | |
| 538 | #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ | |
| 539 | #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ | |
| 540 | ||
| 541 | ||
| 542 | /* Pointer Register */ | |
| 543 | /* BANK 2 */ | |
| 544 | #define PTR_REG 0x0006 | |
| 545 | #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ | |
| 53677ef1 | 546 | #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ |
| fe8c2806 | 547 | #define PTR_READ 0x2000 /* When 1 the operation is a read */ |
| 518e2e1a | 548 | #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ |
| fe8c2806 WD |
549 | |
| 550 | ||
| 551 | /* Data Register */ | |
| 552 | /* BANK 2 */ | |
| 553 | #define SMC91111_DATA_REG 0x0008 | |
| 554 | ||
| 555 | ||
| 556 | /* Interrupt Status/Acknowledge Register */ | |
| 557 | /* BANK 2 */ | |
| 558 | #define SMC91111_INT_REG 0x000C | |
| 559 | ||
| 560 | ||
| 561 | /* Interrupt Mask Register */ | |
| 562 | /* BANK 2 */ | |
| 563 | #define IM_REG 0x000D | |
| 564 | #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ | |
| 565 | #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ | |
| 566 | #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ | |
| 567 | #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ | |
| 568 | #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ | |
| 569 | #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ | |
| 570 | #define IM_TX_INT 0x02 /* Transmit Interrrupt */ | |
| 571 | #define IM_RCV_INT 0x01 /* Receive Interrupt */ | |
| 572 | ||
| 573 | ||
| 574 | /* Multicast Table Registers */ | |
| 575 | /* BANK 3 */ | |
| 576 | #define MCAST_REG1 0x0000 | |
| 577 | #define MCAST_REG2 0x0002 | |
| 578 | #define MCAST_REG3 0x0004 | |
| 579 | #define MCAST_REG4 0x0006 | |
| 580 | ||
| 581 | ||
| 582 | /* Management Interface Register (MII) */ | |
| 583 | /* BANK 3 */ | |
| 584 | #define MII_REG 0x0008 | |
| 585 | #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ | |
| 586 | #define MII_MDOE 0x0008 /* MII Output Enable */ | |
| 587 | #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ | |
| 588 | #define MII_MDI 0x0002 /* MII Input, pin MDI */ | |
| 589 | #define MII_MDO 0x0001 /* MII Output, pin MDO */ | |
| 590 | ||
| 591 | ||
| 592 | /* Revision Register */ | |
| 593 | /* BANK 3 */ | |
| 594 | #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ | |
| 595 | ||
| 596 | ||
| 597 | /* Early RCV Register */ | |
| 598 | /* BANK 3 */ | |
| 599 | /* this is NOT on SMC9192 */ | |
| 600 | #define ERCV_REG 0x000C | |
| 601 | #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ | |
| 602 | #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ | |
| 603 | ||
| 604 | /* External Register */ | |
| 605 | /* BANK 7 */ | |
| 606 | #define EXT_REG 0x0000 | |
| 607 | ||
| 608 | ||
| 609 | #define CHIP_9192 3 | |
| 610 | #define CHIP_9194 4 | |
| 611 | #define CHIP_9195 5 | |
| 612 | #define CHIP_9196 6 | |
| 613 | #define CHIP_91100 7 | |
| 614 | #define CHIP_91100FD 8 | |
| 615 | #define CHIP_91111FD 9 | |
| 616 | ||
| 617 | #if 0 | |
| 618 | static const char * chip_ids[ 15 ] = { | |
| 619 | NULL, NULL, NULL, | |
| 620 | /* 3 */ "SMC91C90/91C92", | |
| 621 | /* 4 */ "SMC91C94", | |
| 622 | /* 5 */ "SMC91C95", | |
| 623 | /* 6 */ "SMC91C96", | |
| 624 | /* 7 */ "SMC91C100", | |
| 625 | /* 8 */ "SMC91C100FD", | |
| 626 | /* 9 */ "SMC91C111", | |
| 627 | NULL, NULL, | |
| 628 | NULL, NULL, NULL}; | |
| 629 | #endif | |
| 630 | ||
| 631 | /* | |
| 632 | . Transmit status bits | |
| 633 | */ | |
| 634 | #define TS_SUCCESS 0x0001 | |
| 635 | #define TS_LOSTCAR 0x0400 | |
| 636 | #define TS_LATCOL 0x0200 | |
| 637 | #define TS_16COL 0x0010 | |
| 638 | ||
| 639 | /* | |
| 640 | . Receive status bits | |
| 641 | */ | |
| 642 | #define RS_ALGNERR 0x8000 | |
| 643 | #define RS_BRODCAST 0x4000 | |
| 644 | #define RS_BADCRC 0x2000 | |
| 645 | #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ | |
| 646 | #define RS_TOOLONG 0x0800 | |
| 647 | #define RS_TOOSHORT 0x0400 | |
| 648 | #define RS_MULTICAST 0x0001 | |
| 649 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
| 650 | ||
| 651 | ||
| 652 | /* PHY Types */ | |
| 653 | enum { | |
| 654 | PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ | |
| 655 | PHY_LAN83C180 | |
| 656 | }; | |
| 657 | ||
| 658 | ||
| 659 | /* PHY Register Addresses (LAN91C111 Internal PHY) */ | |
| 660 | ||
| 661 | /* PHY Control Register */ | |
| 662 | #define PHY_CNTL_REG 0x00 | |
| 663 | #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ | |
| 664 | #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ | |
| 665 | #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ | |
| 666 | #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ | |
| 667 | #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ | |
| 668 | #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ | |
| 669 | #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ | |
| 670 | #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ | |
| 671 | #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ | |
| 672 | ||
| 673 | /* PHY Status Register */ | |
| 674 | #define PHY_STAT_REG 0x01 | |
| 675 | #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ | |
| 676 | #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ | |
| 677 | #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ | |
| 678 | #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ | |
| 679 | #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ | |
| 680 | #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ | |
| 681 | #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ | |
| 682 | #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ | |
| 683 | #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ | |
| 684 | #define PHY_STAT_LINK 0x0004 /* 1=valid link */ | |
| 685 | #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ | |
| 686 | #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ | |
| 687 | ||
| 688 | /* PHY Identifier Registers */ | |
| 689 | #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ | |
| 690 | #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ | |
| 691 | ||
| 692 | /* PHY Auto-Negotiation Advertisement Register */ | |
| 693 | #define PHY_AD_REG 0x04 | |
| 694 | #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ | |
| 695 | #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ | |
| 696 | #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ | |
| 697 | #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ | |
| 698 | #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ | |
| 699 | #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ | |
| 700 | #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ | |
| 701 | #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ | |
| 702 | #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ | |
| 703 | ||
| 704 | /* PHY Auto-negotiation Remote End Capability Register */ | |
| 705 | #define PHY_RMT_REG 0x05 | |
| 706 | /* Uses same bit definitions as PHY_AD_REG */ | |
| 707 | ||
| 708 | /* PHY Configuration Register 1 */ | |
| 709 | #define PHY_CFG1_REG 0x10 | |
| 710 | #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ | |
| 711 | #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ | |
| 712 | #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ | |
| 713 | #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ | |
| 714 | #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ | |
| 715 | #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ | |
| 716 | #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ | |
| 717 | #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ | |
| 718 | #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ | |
| 719 | #define PHY_CFG1_TLVL_MASK 0x003C | |
| 720 | #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ | |
| 721 | ||
| 722 | ||
| 723 | /* PHY Configuration Register 2 */ | |
| 724 | #define PHY_CFG2_REG 0x11 | |
| 725 | #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ | |
| 726 | #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ | |
| 727 | #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ | |
| 728 | #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ | |
| 729 | ||
| 730 | /* PHY Status Output (and Interrupt status) Register */ | |
| 731 | #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ | |
| 732 | #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ | |
| 733 | #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ | |
| 734 | #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ | |
| 735 | #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ | |
| 736 | #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ | |
| 737 | #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ | |
| 738 | #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ | |
| 739 | #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ | |
| 740 | #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ | |
| 741 | #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ | |
| 742 | ||
| 743 | /* PHY Interrupt/Status Mask Register */ | |
| 744 | #define PHY_MASK_REG 0x13 /* Interrupt Mask */ | |
| 745 | /* Uses the same bit definitions as PHY_INT_REG */ | |
| 746 | ||
| 747 | ||
| fe8c2806 WD |
748 | /*------------------------------------------------------------------------- |
| 749 | . I define some macros to make it easier to do somewhat common | |
| 750 | . or slightly complicated, repeated tasks. | |
| 751 | --------------------------------------------------------------------------*/ | |
| 752 | ||
| 753 | /* select a register bank, 0 to 3 */ | |
| 754 | ||
| 755 | #define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } | |
| 756 | ||
| 757 | /* this enables an interrupt in the interrupt mask register */ | |
| 758 | #define SMC_ENABLE_INT(x) {\ | |
| 759 | unsigned char mask;\ | |
| 760 | SMC_SELECT_BANK(2);\ | |
| 761 | mask = SMC_inb( IM_REG );\ | |
| 762 | mask |= (x);\ | |
| 763 | SMC_outb( mask, IM_REG ); \ | |
| 764 | } | |
| 765 | ||
| 766 | /* this disables an interrupt from the interrupt mask register */ | |
| 767 | ||
| 768 | #define SMC_DISABLE_INT(x) {\ | |
| 769 | unsigned char mask;\ | |
| 770 | SMC_SELECT_BANK(2);\ | |
| 771 | mask = SMC_inb( IM_REG );\ | |
| 772 | mask &= ~(x);\ | |
| 773 | SMC_outb( mask, IM_REG ); \ | |
| 774 | } | |
| 775 | ||
| 776 | /*---------------------------------------------------------------------- | |
| 777 | . Define the interrupts that I want to receive from the card | |
| 778 | . | |
| 779 | . I want: | |
| 780 | . IM_EPH_INT, for nasty errors | |
| 781 | . IM_RCV_INT, for happy received packets | |
| 782 | . IM_RX_OVRN_INT, because I have to kick the receiver | |
| 783 | . IM_MDINT, for PHY Register 18 Status Changes | |
| 784 | --------------------------------------------------------------------------*/ | |
| 785 | #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ | |
| 786 | IM_MDINT) | |
| 787 | ||
| 788 | #endif /* _SMC_91111_H_ */ |