]>
Commit | Line | Data |
---|---|---|
de1b686b SH |
1 | /* |
2 | * SMSC LAN9[12]1[567] Network driver | |
3 | * | |
cce9cfda | 4 | * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
de1b686b SH |
5 | * |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | ||
27 | #ifdef CONFIG_DRIVER_SMC911X | |
28 | ||
29 | #include <command.h> | |
30 | #include <net.h> | |
31 | #include <miiphy.h> | |
32 | ||
3e0f331c GL |
33 | #ifdef CONFIG_DRIVER_SMC911X_32_BIT |
34 | static inline u32 reg_read(u32 addr) | |
35 | { | |
36 | return *(volatile u32*)addr; | |
37 | } | |
38 | static inline void reg_write(u32 addr, u32 val) | |
39 | { | |
40 | *(volatile u32*)addr = val; | |
41 | } | |
42 | #else | |
43 | #error "SMC911X: Only 32-bit bus is supported" | |
44 | #endif | |
de1b686b | 45 | |
3e0f331c | 46 | #define mdelay(n) udelay((n)*1000) |
de1b686b SH |
47 | |
48 | /* Below are the register offsets and bit definitions | |
49 | * of the Lan911x memory space | |
50 | */ | |
3e0f331c GL |
51 | #define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00) |
52 | ||
53 | #define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20) | |
54 | #define TX_CMD_A_INT_ON_COMP 0x80000000 | |
55 | #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 | |
56 | #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 | |
57 | #define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 | |
58 | #define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 | |
59 | #define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 | |
60 | #define TX_CMD_A_INT_FIRST_SEG 0x00002000 | |
61 | #define TX_CMD_A_INT_LAST_SEG 0x00001000 | |
62 | #define TX_CMD_A_BUF_SIZE 0x000007FF | |
63 | #define TX_CMD_B_PKT_TAG 0xFFFF0000 | |
64 | #define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 | |
65 | #define TX_CMD_B_DISABLE_PADDING 0x00001000 | |
66 | #define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF | |
67 | ||
68 | #define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40) | |
69 | #define RX_STS_PKT_LEN 0x3FFF0000 | |
70 | #define RX_STS_ES 0x00008000 | |
71 | #define RX_STS_BCST 0x00002000 | |
72 | #define RX_STS_LEN_ERR 0x00001000 | |
73 | #define RX_STS_RUNT_ERR 0x00000800 | |
74 | #define RX_STS_MCAST 0x00000400 | |
75 | #define RX_STS_TOO_LONG 0x00000080 | |
76 | #define RX_STS_COLL 0x00000040 | |
77 | #define RX_STS_ETH_TYPE 0x00000020 | |
78 | #define RX_STS_WDOG_TMT 0x00000010 | |
79 | #define RX_STS_MII_ERR 0x00000008 | |
80 | #define RX_STS_DRIBBLING 0x00000004 | |
81 | #define RX_STS_CRC_ERR 0x00000002 | |
53677ef1 | 82 | #define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) |
3e0f331c GL |
83 | #define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) |
84 | #define TX_STS_TAG 0xFFFF0000 | |
85 | #define TX_STS_ES 0x00008000 | |
86 | #define TX_STS_LOC 0x00000800 | |
87 | #define TX_STS_NO_CARR 0x00000400 | |
88 | #define TX_STS_LATE_COLL 0x00000200 | |
89 | #define TX_STS_MANY_COLL 0x00000100 | |
90 | #define TX_STS_COLL_CNT 0x00000078 | |
91 | #define TX_STS_MANY_DEFER 0x00000004 | |
92 | #define TX_STS_UNDERRUN 0x00000002 | |
93 | #define TX_STS_DEFERRED 0x00000001 | |
94 | #define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C) | |
95 | #define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50) | |
96 | #define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ | |
97 | #define ID_REV_REV_ID 0x0000FFFF /* RO */ | |
98 | ||
99 | #define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54) | |
100 | #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ | |
101 | #define INT_CFG_INT_DEAS_CLR 0x00004000 | |
102 | #define INT_CFG_INT_DEAS_STS 0x00002000 | |
103 | #define INT_CFG_IRQ_INT 0x00001000 /* RO */ | |
104 | #define INT_CFG_IRQ_EN 0x00000100 /* R/W */ | |
105 | #define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */ | |
106 | #define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */ | |
107 | ||
108 | #define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58) | |
109 | #define INT_STS_SW_INT 0x80000000 /* R/WC */ | |
110 | #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ | |
111 | #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ | |
112 | #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ | |
113 | #define INT_STS_RXDF_INT 0x00400000 /* R/WC */ | |
114 | #define INT_STS_TX_IOC 0x00200000 /* R/WC */ | |
115 | #define INT_STS_RXD_INT 0x00100000 /* R/WC */ | |
116 | #define INT_STS_GPT_INT 0x00080000 /* R/WC */ | |
117 | #define INT_STS_PHY_INT 0x00040000 /* RO */ | |
118 | #define INT_STS_PME_INT 0x00020000 /* R/WC */ | |
119 | #define INT_STS_TXSO 0x00010000 /* R/WC */ | |
120 | #define INT_STS_RWT 0x00008000 /* R/WC */ | |
121 | #define INT_STS_RXE 0x00004000 /* R/WC */ | |
122 | #define INT_STS_TXE 0x00002000 /* R/WC */ | |
123 | /*#define INT_STS_ERX 0x00001000*/ /* R/WC */ | |
124 | #define INT_STS_TDFU 0x00000800 /* R/WC */ | |
125 | #define INT_STS_TDFO 0x00000400 /* R/WC */ | |
126 | #define INT_STS_TDFA 0x00000200 /* R/WC */ | |
127 | #define INT_STS_TSFF 0x00000100 /* R/WC */ | |
128 | #define INT_STS_TSFL 0x00000080 /* R/WC */ | |
129 | /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ | |
130 | #define INT_STS_RDFO 0x00000040 /* R/WC */ | |
131 | #define INT_STS_RDFL 0x00000020 /* R/WC */ | |
132 | #define INT_STS_RSFF 0x00000010 /* R/WC */ | |
133 | #define INT_STS_RSFL 0x00000008 /* R/WC */ | |
134 | #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ | |
135 | #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ | |
136 | #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ | |
137 | #define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C) | |
138 | #define INT_EN_SW_INT_EN 0x80000000 /* R/W */ | |
139 | #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ | |
140 | #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ | |
141 | #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ | |
142 | /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ | |
143 | #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ | |
144 | #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ | |
145 | #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ | |
146 | #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ | |
147 | #define INT_EN_PME_INT_EN 0x00020000 /* R/W */ | |
148 | #define INT_EN_TXSO_EN 0x00010000 /* R/W */ | |
149 | #define INT_EN_RWT_EN 0x00008000 /* R/W */ | |
150 | #define INT_EN_RXE_EN 0x00004000 /* R/W */ | |
151 | #define INT_EN_TXE_EN 0x00002000 /* R/W */ | |
152 | /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ | |
153 | #define INT_EN_TDFU_EN 0x00000800 /* R/W */ | |
154 | #define INT_EN_TDFO_EN 0x00000400 /* R/W */ | |
155 | #define INT_EN_TDFA_EN 0x00000200 /* R/W */ | |
156 | #define INT_EN_TSFF_EN 0x00000100 /* R/W */ | |
157 | #define INT_EN_TSFL_EN 0x00000080 /* R/W */ | |
158 | /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ | |
159 | #define INT_EN_RDFO_EN 0x00000040 /* R/W */ | |
160 | #define INT_EN_RDFL_EN 0x00000020 /* R/W */ | |
161 | #define INT_EN_RSFF_EN 0x00000010 /* R/W */ | |
162 | #define INT_EN_RSFL_EN 0x00000008 /* R/W */ | |
163 | #define INT_EN_GPIO2_INT 0x00000004 /* R/W */ | |
164 | #define INT_EN_GPIO1_INT 0x00000002 /* R/W */ | |
165 | #define INT_EN_GPIO0_INT 0x00000001 /* R/W */ | |
166 | ||
167 | #define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64) | |
168 | #define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68) | |
169 | #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ | |
170 | #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ | |
171 | #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ | |
172 | #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ | |
173 | ||
174 | #define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C) | |
175 | #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ | |
176 | #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ | |
177 | #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ | |
178 | #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ | |
179 | #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ | |
180 | #define RX_CFG_RX_DUMP 0x00008000 /* R/W */ | |
181 | #define RX_CFG_RXDOFF 0x00001F00 /* R/W */ | |
182 | /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ | |
183 | ||
184 | #define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70) | |
185 | /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ | |
186 | /*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */ | |
187 | #define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ | |
188 | #define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ | |
189 | #define TX_CFG_TXSAO 0x00000004 /* R/W */ | |
190 | #define TX_CFG_TX_ON 0x00000002 /* R/W */ | |
191 | #define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ | |
192 | ||
193 | #define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74) | |
194 | #define HW_CFG_TTM 0x00200000 /* R/W */ | |
195 | #define HW_CFG_SF 0x00100000 /* R/W */ | |
196 | #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ | |
197 | #define HW_CFG_TR 0x00003000 /* R/W */ | |
198 | #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ | |
53677ef1 WD |
199 | #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ |
200 | #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ | |
201 | #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ | |
3e0f331c GL |
202 | #define HW_CFG_SMI_SEL 0x00000010 /* R/W */ |
203 | #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ | |
204 | #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ | |
205 | #define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ | |
206 | #define HW_CFG_SRST_TO 0x00000002 /* RO */ | |
207 | #define HW_CFG_SRST 0x00000001 /* Self Clearing */ | |
208 | ||
209 | #define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78) | |
210 | #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ | |
211 | #define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ | |
212 | ||
213 | #define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C) | |
214 | #define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ | |
215 | #define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ | |
216 | ||
217 | #define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80) | |
218 | #define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ | |
219 | #define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ | |
220 | ||
221 | #define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84) | |
222 | #define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ | |
223 | #define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ | |
224 | #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ | |
225 | #define PMT_CTRL_ED_EN 0x00000100 /* R/W */ | |
226 | #define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */ | |
227 | #define PMT_CTRL_WUPS 0x00000030 /* R/WC */ | |
228 | #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ | |
229 | #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ | |
230 | #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ | |
231 | #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ | |
232 | #define PMT_CTRL_PME_IND 0x00000008 /* R/W */ | |
233 | #define PMT_CTRL_PME_POL 0x00000004 /* R/W */ | |
234 | #define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */ | |
235 | #define PMT_CTRL_READY 0x00000001 /* RO */ | |
236 | ||
237 | #define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88) | |
238 | #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ | |
239 | #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ | |
240 | #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ | |
241 | #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ | |
242 | #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ | |
243 | #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ | |
244 | #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ | |
245 | #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ | |
246 | #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ | |
247 | #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ | |
248 | #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ | |
249 | #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ | |
250 | #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ | |
251 | #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ | |
252 | #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ | |
253 | #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ | |
254 | #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ | |
255 | #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ | |
256 | ||
257 | #define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C) | |
258 | #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ | |
259 | #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ | |
260 | ||
261 | #define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90) | |
262 | #define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ | |
263 | ||
264 | #define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98) | |
265 | #define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C) | |
266 | #define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0) | |
267 | #define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4) | |
268 | #define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ | |
269 | #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ | |
270 | #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ | |
271 | ||
272 | #define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8) | |
273 | #define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC) | |
274 | #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ | |
275 | #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ | |
276 | #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ | |
277 | #define AFC_CFG_FCMULT 0x00000008 /* R/W */ | |
278 | #define AFC_CFG_FCBRD 0x00000004 /* R/W */ | |
279 | #define AFC_CFG_FCADD 0x00000002 /* R/W */ | |
280 | #define AFC_CFG_FCANY 0x00000001 /* R/W */ | |
281 | ||
282 | #define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0) | |
283 | #define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ | |
284 | #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ | |
285 | #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ | |
286 | #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ | |
287 | #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ | |
288 | #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ | |
289 | #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ | |
290 | #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ | |
291 | #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ | |
292 | #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ | |
293 | #define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ | |
294 | #define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ | |
295 | #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ | |
296 | ||
297 | #define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4) | |
298 | #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ | |
de1b686b SH |
299 | /* end of LAN register offsets and bit definitions */ |
300 | ||
301 | /* MAC Control and Status registers */ | |
3e0f331c | 302 | #define MAC_CR 0x01 /* R/W */ |
de1b686b SH |
303 | |
304 | /* MAC_CR - MAC Control Register */ | |
3e0f331c | 305 | #define MAC_CR_RXALL 0x80000000 |
de1b686b | 306 | /* TODO: delete this bit? It is not described in the data sheet. */ |
3e0f331c GL |
307 | #define MAC_CR_HBDIS 0x10000000 |
308 | #define MAC_CR_RCVOWN 0x00800000 | |
309 | #define MAC_CR_LOOPBK 0x00200000 | |
310 | #define MAC_CR_FDPX 0x00100000 | |
311 | #define MAC_CR_MCPAS 0x00080000 | |
312 | #define MAC_CR_PRMS 0x00040000 | |
313 | #define MAC_CR_INVFILT 0x00020000 | |
314 | #define MAC_CR_PASSBAD 0x00010000 | |
315 | #define MAC_CR_HFILT 0x00008000 | |
316 | #define MAC_CR_HPFILT 0x00002000 | |
317 | #define MAC_CR_LCOLL 0x00001000 | |
318 | #define MAC_CR_BCAST 0x00000800 | |
319 | #define MAC_CR_DISRTY 0x00000400 | |
320 | #define MAC_CR_PADSTR 0x00000100 | |
321 | #define MAC_CR_BOLMT_MASK 0x000000C0 | |
322 | #define MAC_CR_DFCHK 0x00000020 | |
323 | #define MAC_CR_TXEN 0x00000008 | |
324 | #define MAC_CR_RXEN 0x00000004 | |
325 | ||
326 | #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ | |
327 | #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ | |
328 | #define HASHH 0x04 /* R/W */ | |
329 | #define HASHL 0x05 /* R/W */ | |
330 | ||
331 | #define MII_ACC 0x06 /* R/W */ | |
332 | #define MII_ACC_PHY_ADDR 0x0000F800 | |
333 | #define MII_ACC_MIIRINDA 0x000007C0 | |
334 | #define MII_ACC_MII_WRITE 0x00000002 | |
335 | #define MII_ACC_MII_BUSY 0x00000001 | |
336 | ||
337 | #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ | |
338 | ||
339 | #define FLOW 0x08 /* R/W */ | |
340 | #define FLOW_FCPT 0xFFFF0000 | |
341 | #define FLOW_FCPASS 0x00000004 | |
342 | #define FLOW_FCEN 0x00000002 | |
343 | #define FLOW_FCBSY 0x00000001 | |
344 | ||
345 | #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ | |
346 | #define VLAN1_VTI1 0x0000ffff | |
347 | ||
348 | #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ | |
349 | #define VLAN2_VTI2 0x0000ffff | |
350 | ||
351 | #define WUFF 0x0B /* WO */ | |
352 | ||
353 | #define WUCSR 0x0C /* R/W */ | |
354 | #define WUCSR_GUE 0x00000200 | |
355 | #define WUCSR_WUFR 0x00000040 | |
356 | #define WUCSR_MPR 0x00000020 | |
357 | #define WUCSR_WAKE_EN 0x00000004 | |
358 | #define WUCSR_MPEN 0x00000002 | |
de1b686b SH |
359 | |
360 | /* Chip ID values */ | |
361 | #define CHIP_9115 0x115 | |
362 | #define CHIP_9116 0x116 | |
363 | #define CHIP_9117 0x117 | |
364 | #define CHIP_9118 0x118 | |
365 | #define CHIP_9215 0x115a | |
366 | #define CHIP_9216 0x116a | |
367 | #define CHIP_9217 0x117a | |
368 | #define CHIP_9218 0x118a | |
369 | ||
370 | struct chip_id { | |
371 | u16 id; | |
372 | char *name; | |
373 | }; | |
374 | ||
375 | static const struct chip_id chip_ids[] = { | |
376 | { CHIP_9115, "LAN9115" }, | |
377 | { CHIP_9116, "LAN9116" }, | |
378 | { CHIP_9117, "LAN9117" }, | |
379 | { CHIP_9118, "LAN9118" }, | |
380 | { CHIP_9215, "LAN9215" }, | |
381 | { CHIP_9216, "LAN9216" }, | |
382 | { CHIP_9217, "LAN9217" }, | |
383 | { CHIP_9218, "LAN9218" }, | |
384 | { 0, NULL }, | |
385 | }; | |
386 | ||
387 | #define DRIVERNAME "smc911x" | |
388 | ||
389 | u32 smc911x_get_mac_csr(u8 reg) | |
390 | { | |
3e0f331c GL |
391 | while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) |
392 | ; | |
393 | reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); | |
394 | while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) | |
395 | ; | |
de1b686b | 396 | |
3e0f331c | 397 | return reg_read(MAC_CSR_DATA); |
de1b686b SH |
398 | } |
399 | ||
400 | void smc911x_set_mac_csr(u8 reg, u32 data) | |
401 | { | |
3e0f331c GL |
402 | while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) |
403 | ; | |
404 | reg_write(MAC_CSR_DATA, data); | |
405 | reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); | |
406 | while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) | |
407 | ; | |
de1b686b SH |
408 | } |
409 | ||
410 | static int smx911x_handle_mac_address(bd_t *bd) | |
411 | { | |
412 | unsigned long addrh, addrl; | |
413 | unsigned char *m = bd->bi_enetaddr; | |
414 | ||
415 | /* if the environment has a valid mac address then use it */ | |
416 | if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) { | |
417 | addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24; | |
418 | addrh = m[4] | m[5] << 8; | |
419 | smc911x_set_mac_csr(ADDRH, addrh); | |
420 | smc911x_set_mac_csr(ADDRL, addrl); | |
421 | } else { | |
422 | /* if not, try to get one from the eeprom */ | |
423 | addrh = smc911x_get_mac_csr(ADDRH); | |
424 | addrl = smc911x_get_mac_csr(ADDRL); | |
425 | ||
426 | m[0] = (addrl ) & 0xff; | |
427 | m[1] = (addrl >> 8 ) & 0xff; | |
428 | m[2] = (addrl >> 16 ) & 0xff; | |
429 | m[3] = (addrl >> 24 ) & 0xff; | |
430 | m[4] = (addrh ) & 0xff; | |
431 | m[5] = (addrh >> 8 ) & 0xff; | |
432 | ||
433 | /* we get 0xff when there is no eeprom connected */ | |
434 | if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) { | |
435 | printf(DRIVERNAME ": no valid mac address in environment " | |
436 | "and no eeprom found\n"); | |
437 | return -1; | |
438 | } | |
439 | } | |
440 | ||
441 | printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n", | |
442 | m[0], m[1], m[2], m[3], m[4], m[5]); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val) | |
448 | { | |
3e0f331c GL |
449 | while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) |
450 | ; | |
de1b686b | 451 | |
3e0f331c | 452 | smc911x_set_mac_csr(MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY); |
de1b686b | 453 | |
3e0f331c GL |
454 | while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) |
455 | ; | |
de1b686b SH |
456 | |
457 | *val = smc911x_get_mac_csr(MII_DATA); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val) | |
463 | { | |
3e0f331c GL |
464 | while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) |
465 | ; | |
de1b686b SH |
466 | |
467 | smc911x_set_mac_csr(MII_DATA, val); | |
468 | smc911x_set_mac_csr(MII_ACC, | |
469 | phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); | |
470 | ||
3e0f331c GL |
471 | while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY) |
472 | ; | |
de1b686b SH |
473 | return 0; |
474 | } | |
475 | ||
476 | static int smc911x_phy_reset(void) | |
477 | { | |
478 | u32 reg; | |
479 | ||
3e0f331c | 480 | reg = reg_read(PMT_CTRL); |
de1b686b SH |
481 | reg &= ~0xfffff030; |
482 | reg |= PMT_CTRL_PHY_RST; | |
3e0f331c | 483 | reg_write(PMT_CTRL, reg); |
de1b686b SH |
484 | |
485 | mdelay(100); | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
490 | static void smc911x_phy_configure(void) | |
491 | { | |
492 | int timeout; | |
493 | u16 status; | |
494 | ||
495 | smc911x_phy_reset(); | |
496 | ||
497 | smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET); | |
498 | mdelay(1); | |
499 | smc911x_miiphy_write(1, PHY_ANAR, 0x01e1); | |
500 | smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); | |
501 | ||
502 | timeout = 5000; | |
503 | do { | |
504 | mdelay(1); | |
505 | if ((timeout--) == 0) | |
506 | goto err_out; | |
507 | ||
508 | if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0) | |
509 | goto err_out; | |
510 | } while (!(status & PHY_BMSR_LS)); | |
511 | ||
512 | printf(DRIVERNAME ": phy initialized\n"); | |
513 | ||
514 | return; | |
515 | ||
516 | err_out: | |
517 | printf(DRIVERNAME ": autonegotiation timed out\n"); | |
518 | } | |
519 | ||
520 | static void smc911x_reset(void) | |
521 | { | |
522 | int timeout; | |
523 | ||
524 | /* Take out of PM setting first */ | |
3e0f331c | 525 | if (reg_read(PMT_CTRL) & PMT_CTRL_READY) { |
de1b686b | 526 | /* Write to the bytetest will take out of powerdown */ |
3e0f331c | 527 | reg_write(BYTE_TEST, 0x0); |
de1b686b SH |
528 | |
529 | timeout = 10; | |
530 | ||
3e0f331c | 531 | while (timeout-- && !(reg_read(PMT_CTRL) & PMT_CTRL_READY)) |
de1b686b SH |
532 | udelay(10); |
533 | if (!timeout) { | |
534 | printf(DRIVERNAME | |
535 | ": timeout waiting for PM restore\n"); | |
536 | return; | |
537 | } | |
538 | } | |
539 | ||
540 | /* Disable interrupts */ | |
3e0f331c | 541 | reg_write(INT_EN, 0); |
de1b686b | 542 | |
3e0f331c | 543 | reg_write(HW_CFG, HW_CFG_SRST); |
de1b686b SH |
544 | |
545 | timeout = 1000; | |
3e0f331c | 546 | while (timeout-- && reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) |
de1b686b SH |
547 | udelay(10); |
548 | ||
3e0f331c | 549 | if (!timeout) { |
de1b686b SH |
550 | printf(DRIVERNAME ": reset timeout\n"); |
551 | return; | |
552 | } | |
553 | ||
554 | /* Reset the FIFO level and flow control settings */ | |
555 | smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); | |
3e0f331c | 556 | reg_write(AFC_CFG, 0x0050287F); |
de1b686b SH |
557 | |
558 | /* Set to LED outputs */ | |
3e0f331c | 559 | reg_write(GPIO_CFG, 0x70070000); |
de1b686b SH |
560 | } |
561 | ||
562 | static void smc911x_enable(void) | |
563 | { | |
564 | /* Enable TX */ | |
3e0f331c | 565 | reg_write(HW_CFG, 8 << 16 | HW_CFG_SF); |
de1b686b | 566 | |
3e0f331c | 567 | reg_write(GPT_CFG, GPT_CFG_TIMER_EN | 10000); |
de1b686b | 568 | |
3e0f331c | 569 | reg_write(TX_CFG, TX_CFG_TX_ON); |
de1b686b SH |
570 | |
571 | /* no padding to start of packets */ | |
3e0f331c | 572 | reg_write(RX_CFG, 0); |
de1b686b SH |
573 | |
574 | smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); | |
575 | ||
576 | } | |
577 | ||
578 | int eth_init(bd_t *bd) | |
579 | { | |
580 | unsigned long val, i; | |
581 | ||
582 | printf(DRIVERNAME ": initializing\n"); | |
583 | ||
3e0f331c GL |
584 | val = reg_read(BYTE_TEST); |
585 | if (val != 0x87654321) { | |
de1b686b SH |
586 | printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val); |
587 | goto err_out; | |
588 | } | |
589 | ||
3e0f331c GL |
590 | val = reg_read(ID_REV) >> 16; |
591 | for (i = 0; chip_ids[i].id != 0; i++) { | |
de1b686b SH |
592 | if (chip_ids[i].id == val) break; |
593 | } | |
594 | if (!chip_ids[i].id) { | |
595 | printf(DRIVERNAME ": Unknown chip ID %04x\n", val); | |
596 | goto err_out; | |
597 | } | |
598 | ||
599 | printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); | |
600 | ||
601 | smc911x_reset(); | |
602 | ||
603 | /* Configure the PHY, initialize the link state */ | |
604 | smc911x_phy_configure(); | |
605 | ||
606 | if (smx911x_handle_mac_address(bd)) | |
607 | goto err_out; | |
608 | ||
609 | /* Turn on Tx + Rx */ | |
610 | smc911x_enable(); | |
611 | ||
612 | return 0; | |
613 | ||
614 | err_out: | |
615 | return -1; | |
616 | } | |
617 | ||
618 | int eth_send(volatile void *packet, int length) | |
619 | { | |
620 | u32 *data = (u32*)packet; | |
621 | u32 tmplen; | |
622 | u32 status; | |
623 | ||
3e0f331c GL |
624 | reg_write(TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length); |
625 | reg_write(TX_DATA_FIFO, length); | |
de1b686b SH |
626 | |
627 | tmplen = (length + 3) / 4; | |
628 | ||
3e0f331c GL |
629 | while (tmplen--) |
630 | reg_write(TX_DATA_FIFO, *data++); | |
de1b686b SH |
631 | |
632 | /* wait for transmission */ | |
3e0f331c | 633 | while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16)); |
de1b686b SH |
634 | |
635 | /* get status. Ignore 'no carrier' error, it has no meaning for | |
636 | * full duplex operation | |
637 | */ | |
3e0f331c | 638 | status = reg_read(TX_STATUS_FIFO) & (TX_STS_LOC | TX_STS_LATE_COLL | |
de1b686b SH |
639 | TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); |
640 | ||
3e0f331c | 641 | if (!status) |
de1b686b SH |
642 | return 0; |
643 | ||
644 | printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", | |
645 | status & TX_STS_LOC ? "TX_STS_LOC " : "", | |
646 | status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", | |
647 | status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", | |
648 | status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", | |
649 | status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); | |
650 | ||
651 | return -1; | |
652 | } | |
653 | ||
654 | void eth_halt(void) | |
655 | { | |
656 | smc911x_reset(); | |
657 | } | |
658 | ||
659 | int eth_rx(void) | |
660 | { | |
661 | u32 *data = (u32 *)NetRxPackets[0]; | |
662 | u32 pktlen, tmplen; | |
663 | u32 status; | |
664 | ||
3e0f331c GL |
665 | if ((reg_read(RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) { |
666 | status = reg_read(RX_STATUS_FIFO); | |
de1b686b SH |
667 | pktlen = (status & RX_STS_PKT_LEN) >> 16; |
668 | ||
3e0f331c | 669 | reg_write(RX_CFG, 0); |
de1b686b SH |
670 | |
671 | tmplen = (pktlen + 2+ 3) / 4; | |
3e0f331c GL |
672 | while (tmplen--) |
673 | *data++ = reg_read(RX_DATA_FIFO); | |
de1b686b | 674 | |
3e0f331c | 675 | if (status & RX_STS_ES) |
de1b686b SH |
676 | printf(DRIVERNAME |
677 | ": dropped bad packet. Status: 0x%08x\n", | |
678 | status); | |
679 | else | |
680 | NetReceive(NetRxPackets[0], pktlen); | |
681 | } | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | #endif /* CONFIG_DRIVER_SMC911X */ |