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Merge branch 'master' of git://git.denx.de/u-boot-sunxi
[people/ms/u-boot.git] / drivers / net / sun8i_emac.c
CommitLineData
a29710c5
AST		 1/*
2 * (C) Copyright 2016
3 * Author: Amit Singh Tomar, amittomer25@gmail.com
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Ethernet driver for H3/A64/A83T based SoC's
8 *
9 * It is derived from the work done by
10 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
11 *
12*/
13
14#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/gpio.h>
17#include <common.h>
18#include <dm.h>
19#include <fdt_support.h>
20#include <linux/err.h>
21#include <malloc.h>
22#include <miiphy.h>
23#include <net.h>
4d555ae3
PT		 24#ifdef CONFIG_DM_GPIO
25#include <asm-generic/gpio.h>
26#endif
a29710c5 27
a29710c5
AST		 28#define MDIO_CMD_MII_BUSY BIT(0)
29#define MDIO_CMD_MII_WRITE BIT(1)
30
31#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
32#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
33#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
34#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
35
36#define CONFIG_TX_DESCR_NUM 32
37#define CONFIG_RX_DESCR_NUM 32
4069437d
HG		 38#define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
39
40/*
41 * The datasheet says that each descriptor can transfers up to 4096 bytes
42 * But later, the register documentation reduces that value to 2048,
43 * using 2048 cause strange behaviours and even BSP driver use 2047
44 */
45#define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
a29710c5
AST		 46
47#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
48#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
49
50#define H3_EPHY_DEFAULT_VALUE 0x58000
51#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
52#define H3_EPHY_ADDR_SHIFT 20
53#define REG_PHY_ADDR_MASK GENMASK(4, 0)
54#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
55#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
56#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
57
58#define SC_RMII_EN BIT(13)
59#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
60#define SC_ETCS_MASK GENMASK(1, 0)
61#define SC_ETCS_EXT_GMII 0x1
62#define SC_ETCS_INT_GMII 0x2
63
64#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
65
66#define AHB_GATE_OFFSET_EPHY 0
67
7b82a229 68#if defined(CONFIG_MACH_SUNXI_H3_H5)
a29710c5
AST		 69#define SUN8I_GPD8_GMAC 2
70#else
71#define SUN8I_GPD8_GMAC 4
72#endif
73
74/* H3/A64 EMAC Register's offset */
75#define EMAC_CTL0 0x00
76#define EMAC_CTL1 0x04
77#define EMAC_INT_STA 0x08
78#define EMAC_INT_EN 0x0c
79#define EMAC_TX_CTL0 0x10
80#define EMAC_TX_CTL1 0x14
81#define EMAC_TX_FLOW_CTL 0x1c
82#define EMAC_TX_DMA_DESC 0x20
83#define EMAC_RX_CTL0 0x24
84#define EMAC_RX_CTL1 0x28
85#define EMAC_RX_DMA_DESC 0x34
86#define EMAC_MII_CMD 0x48
87#define EMAC_MII_DATA 0x4c
88#define EMAC_ADDR0_HIGH 0x50
89#define EMAC_ADDR0_LOW 0x54
90#define EMAC_TX_DMA_STA 0xb0
91#define EMAC_TX_CUR_DESC 0xb4
92#define EMAC_TX_CUR_BUF 0xb8
93#define EMAC_RX_DMA_STA 0xc0
94#define EMAC_RX_CUR_DESC 0xc4
95
96DECLARE_GLOBAL_DATA_PTR;
97
98enum emac_variant {
99 A83T_EMAC = 1,
100 H3_EMAC,
101 A64_EMAC,
102};
103
104struct emac_dma_desc {
105 u32 status;
106 u32 st;
107 u32 buf_addr;
108 u32 next;
109} __aligned(ARCH_DMA_MINALIGN);
110
111struct emac_eth_dev {
112 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
113 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
114 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
115 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
116
117 u32 interface;
118 u32 phyaddr;
119 u32 link;
120 u32 speed;
121 u32 duplex;
122 u32 phy_configured;
123 u32 tx_currdescnum;
124 u32 rx_currdescnum;
125 u32 addr;
126 u32 tx_slot;
127 bool use_internal_phy;
128
129 enum emac_variant variant;
130 void *mac_reg;
131 phys_addr_t sysctl_reg;
132 struct phy_device *phydev;
133 struct mii_dev *bus;
4d555ae3
PT		 134#ifdef CONFIG_DM_GPIO
135 struct gpio_desc reset_gpio;
136#endif
137};
138
139
140struct sun8i_eth_pdata {
141 struct eth_pdata eth_pdata;
142 u32 reset_delays[3];
a29710c5
AST		 143};
144
4d555ae3 145
a29710c5
AST		 146static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
147{
4d555ae3
PT		 148 struct udevice *dev = bus->priv;
149 struct emac_eth_dev *priv = dev_get_priv(dev);
a29710c5
AST		 150 ulong start;
151 u32 miiaddr = 0;
152 int timeout = CONFIG_MDIO_TIMEOUT;
153
154 miiaddr &= ~MDIO_CMD_MII_WRITE;
155 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
156 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
157 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
158
159 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
160
161 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
162 MDIO_CMD_MII_PHY_ADDR_MASK;
163
164 miiaddr |= MDIO_CMD_MII_BUSY;
165
166 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
167
168 start = get_timer(0);
169 while (get_timer(start) < timeout) {
170 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
171 return readl(priv->mac_reg + EMAC_MII_DATA);
172 udelay(10);
173 };
174
175 return -1;
176}
177
178static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
179 u16 val)
180{
4d555ae3
PT		 181 struct udevice *dev = bus->priv;
182 struct emac_eth_dev *priv = dev_get_priv(dev);
a29710c5
AST		 183 ulong start;
184 u32 miiaddr = 0;
185 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
186
187 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
188 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
189 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
190
191 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
192 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
193 MDIO_CMD_MII_PHY_ADDR_MASK;
194
195 miiaddr |= MDIO_CMD_MII_WRITE;
196 miiaddr |= MDIO_CMD_MII_BUSY;
197
a29710c5 198 writel(val, priv->mac_reg + EMAC_MII_DATA);
1deeecb6 199 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
a29710c5
AST		 200
201 start = get_timer(0);
202 while (get_timer(start) < timeout) {
203 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
204 MDIO_CMD_MII_BUSY)) {
205 ret = 0;
206 break;
207 }
208 udelay(10);
209 };
210
211 return ret;
212}
213
214static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
215{
216 u32 macid_lo, macid_hi;
217
218 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
219 (mac_id[3] << 24);
220 macid_hi = mac_id[4] + (mac_id[5] << 8);
221
222 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
223 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
224
225 return 0;
226}
227
228static void sun8i_adjust_link(struct emac_eth_dev *priv,
229 struct phy_device *phydev)
230{
231 u32 v;
232
233 v = readl(priv->mac_reg + EMAC_CTL0);
234
235 if (phydev->duplex)
236 v |= BIT(0);
237 else
238 v &= ~BIT(0);
239
240 v &= ~0x0C;
241
242 switch (phydev->speed) {
243 case 1000:
244 break;
245 case 100:
246 v |= BIT(2);
247 v |= BIT(3);
248 break;
249 case 10:
250 v |= BIT(3);
251 break;
252 }
253 writel(v, priv->mac_reg + EMAC_CTL0);
254}
255
256static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
257{
258 if (priv->use_internal_phy) {
259 /* H3 based SoC's that has an Internal 100MBit PHY
260 * needs to be configured and powered up before use
261 */
262 *reg &= ~H3_EPHY_DEFAULT_MASK;
263 *reg |= H3_EPHY_DEFAULT_VALUE;
264 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
265 *reg &= ~H3_EPHY_SHUTDOWN;
266 *reg |= H3_EPHY_SELECT;
267 } else
268 /* This is to select External Gigabit PHY on
269 * the boards with H3 SoC.
270 */
271 *reg &= ~H3_EPHY_SELECT;
272
273 return 0;
274}
275
276static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
277{
278 int ret;
279 u32 reg;
280
281 reg = readl(priv->sysctl_reg);
282
283 if (priv->variant == H3_EMAC) {
284 ret = sun8i_emac_set_syscon_ephy(priv, &reg);
285 if (ret)
286 return ret;
287 }
288
289 reg &= ~(SC_ETCS_MASK | SC_EPIT);
290 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
291 reg &= ~SC_RMII_EN;
292
293 switch (priv->interface) {
294 case PHY_INTERFACE_MODE_MII:
295 /* default */
296 break;
297 case PHY_INTERFACE_MODE_RGMII:
298 reg |= SC_EPIT | SC_ETCS_INT_GMII;
299 break;
300 case PHY_INTERFACE_MODE_RMII:
301 if (priv->variant == H3_EMAC ||
302 priv->variant == A64_EMAC) {
303 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
304 break;
305 }
306 /* RMII not supported on A83T */
307 default:
308 debug("%s: Invalid PHY interface\n", __func__);
309 return -EINVAL;
310 }
311
312 writel(reg, priv->sysctl_reg);
313
314 return 0;
315}
316
317static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
318{
319 struct phy_device *phydev;
320
321 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
322 if (!phydev)
323 return -ENODEV;
324
325 phy_connect_dev(phydev, dev);
326
327 priv->phydev = phydev;
328 phy_config(priv->phydev);
329
330 return 0;
331}
332
333static void rx_descs_init(struct emac_eth_dev *priv)
334{
335 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
336 char *rxbuffs = &priv->rxbuffer[0];
337 struct emac_dma_desc *desc_p;
338 u32 idx;
339
340 /* flush Rx buffers */
341 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
342 RX_TOTAL_BUFSIZE);
343
344 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
345 desc_p = &desc_table_p[idx];
346 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
347 ;
348 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
4069437d 349 desc_p->st |= CONFIG_ETH_RXSIZE;
a29710c5
AST		 350 desc_p->status = BIT(31);
351 }
352
353 /* Correcting the last pointer of the chain */
354 desc_p->next = (uintptr_t)&desc_table_p[0];
355
356 flush_dcache_range((uintptr_t)priv->rx_chain,
357 (uintptr_t)priv->rx_chain +
358 sizeof(priv->rx_chain));
359
360 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
361 priv->rx_currdescnum = 0;
362}
363
364static void tx_descs_init(struct emac_eth_dev *priv)
365{
366 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
367 char *txbuffs = &priv->txbuffer[0];
368 struct emac_dma_desc *desc_p;
369 u32 idx;
370
371 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
372 desc_p = &desc_table_p[idx];
373 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
374 ;
375 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
376 desc_p->status = (1 << 31);
377 desc_p->st = 0;
378 }
379
380 /* Correcting the last pointer of the chain */
381 desc_p->next = (uintptr_t)&desc_table_p[0];
382
383 /* Flush all Tx buffer descriptors */
384 flush_dcache_range((uintptr_t)priv->tx_chain,
385 (uintptr_t)priv->tx_chain +
386 sizeof(priv->tx_chain));
387
388 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
389 priv->tx_currdescnum = 0;
390}
391
392static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
393{
394 u32 reg, v;
395 int timeout = 100;
396
397 reg = readl((priv->mac_reg + EMAC_CTL1));
398
399 if (!(reg & 0x1)) {
400 /* Soft reset MAC */
401 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
402 do {
403 reg = readl(priv->mac_reg + EMAC_CTL1);
404 } while ((reg & 0x01) != 0 && (--timeout));
405 if (!timeout) {
406 printf("%s: Timeout\n", __func__);
407 return -1;
408 }
409 }
410
411 /* Rewrite mac address after reset */
412 _sun8i_write_hwaddr(priv, enetaddr);
413
414 v = readl(priv->mac_reg + EMAC_TX_CTL1);
415 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
416 v |= BIT(1);
417 writel(v, priv->mac_reg + EMAC_TX_CTL1);
418
419 v = readl(priv->mac_reg + EMAC_RX_CTL1);
420 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
421 * complete frame has been written to RX DMA FIFO
422 */
423 v |= BIT(1);
424 writel(v, priv->mac_reg + EMAC_RX_CTL1);
425
426 /* DMA */
427 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
428
429 /* Initialize rx/tx descriptors */
430 rx_descs_init(priv);
431 tx_descs_init(priv);
432
433 /* PHY Start Up */
434 genphy_parse_link(priv->phydev);
435
436 sun8i_adjust_link(priv, priv->phydev);
437
438 /* Start RX DMA */
439 v = readl(priv->mac_reg + EMAC_RX_CTL1);
440 v |= BIT(30);
441 writel(v, priv->mac_reg + EMAC_RX_CTL1);
442 /* Start TX DMA */
443 v = readl(priv->mac_reg + EMAC_TX_CTL1);
444 v |= BIT(30);
445 writel(v, priv->mac_reg + EMAC_TX_CTL1);
446
447 /* Enable RX/TX */
448 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
449 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
450
451 return 0;
452}
453
454static int parse_phy_pins(struct udevice *dev)
455{
456 int offset;
457 const char *pin_name;
458 int drive, pull, i;
459
e160f7d4 460 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
a29710c5
AST		 461 "pinctrl-0");
462 if (offset < 0) {
463 printf("WARNING: emac: cannot find pinctrl-0 node\n");
464 return offset;
465 }
466
467 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
468 "allwinner,drive", 4);
469 pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
470 "allwinner,pull", 0);
471 for (i = 0; ; i++) {
472 int pin;
473
b02e4044 474 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
6e67f176 475 "allwinner,pins", i, NULL);
b02e4044 476 if (!pin_name)
a29710c5
AST		 477 break;
478 if (pin_name[0] != 'P')
479 continue;
480 pin = (pin_name[1] - 'A') << 5;
481 if (pin >= 26 << 5)
482 continue;
483 pin += simple_strtol(&pin_name[2], NULL, 10);
484
485 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
486 sunxi_gpio_set_drv(pin, drive);
487 sunxi_gpio_set_pull(pin, pull);
488 }
489
490 if (!i) {
491 printf("WARNING: emac: cannot find allwinner,pins property\n");
492 return -2;
493 }
494
495 return 0;
496}
497
498static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
499{
500 u32 status, desc_num = priv->rx_currdescnum;
501 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
502 int length = -EAGAIN;
503 int good_packet = 1;
504 uintptr_t desc_start = (uintptr_t)desc_p;
505 uintptr_t desc_end = desc_start +
506 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
507
508 ulong data_start = (uintptr_t)desc_p->buf_addr;
509 ulong data_end;
510
511 /* Invalidate entire buffer descriptor */
512 invalidate_dcache_range(desc_start, desc_end);
513
514 status = desc_p->status;
515
516 /* Check for DMA own bit */
517 if (!(status & BIT(31))) {
518 length = (desc_p->status >> 16) & 0x3FFF;
519
520 if (length < 0x40) {
521 good_packet = 0;
522 debug("RX: Bad Packet (runt)\n");
523 }
524
525 data_end = data_start + length;
526 /* Invalidate received data */
527 invalidate_dcache_range(rounddown(data_start,
528 ARCH_DMA_MINALIGN),
529 roundup(data_end,
530 ARCH_DMA_MINALIGN));
531 if (good_packet) {
4069437d 532 if (length > CONFIG_ETH_RXSIZE) {
a29710c5
AST		 533 printf("Received packet is too big (len=%d)\n",
534 length);
535 return -EMSGSIZE;
536 }
537 *packetp = (uchar *)(ulong)desc_p->buf_addr;
538 return length;
539 }
540 }
541
542 return length;
543}
544
545static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
546 int len)
547{
548 u32 v, desc_num = priv->tx_currdescnum;
549 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
550 uintptr_t desc_start = (uintptr_t)desc_p;
551 uintptr_t desc_end = desc_start +
552 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
553
554 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
555 uintptr_t data_end = data_start +
556 roundup(len, ARCH_DMA_MINALIGN);
557
558 /* Invalidate entire buffer descriptor */
559 invalidate_dcache_range(desc_start, desc_end);
560
561 desc_p->st = len;
562 /* Mandatory undocumented bit */
563 desc_p->st |= BIT(24);
564
565 memcpy((void *)data_start, packet, len);
566
567 /* Flush data to be sent */
568 flush_dcache_range(data_start, data_end);
569
570 /* frame end */
571 desc_p->st |= BIT(30);
572 desc_p->st |= BIT(31);
573
574 /*frame begin */
575 desc_p->st |= BIT(29);
576 desc_p->status = BIT(31);
577
578 /*Descriptors st and status field has changed, so FLUSH it */
579 flush_dcache_range(desc_start, desc_end);
580
581 /* Move to next Descriptor and wrap around */
582 if (++desc_num >= CONFIG_TX_DESCR_NUM)
583 desc_num = 0;
584 priv->tx_currdescnum = desc_num;
585
586 /* Start the DMA */
587 v = readl(priv->mac_reg + EMAC_TX_CTL1);
588 v |= BIT(31);/* mandatory */
589 v |= BIT(30);/* mandatory */
590 writel(v, priv->mac_reg + EMAC_TX_CTL1);
591
592 return 0;
593}
594
595static int sun8i_eth_write_hwaddr(struct udevice *dev)
596{
597 struct eth_pdata *pdata = dev_get_platdata(dev);
598 struct emac_eth_dev *priv = dev_get_priv(dev);
599
600 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
601}
602
603static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
604{
605 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
606
607 if (priv->use_internal_phy) {
608 /* Set clock gating for ephy */
609 setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
610
a29710c5
AST		 611 /* Deassert EPHY */
612 setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
613 }
614
615 /* Set clock gating for emac */
616 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
617
a29710c5
AST		 618 /* De-assert EMAC */
619 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
620}
621
4d555ae3
PT		 622#if defined(CONFIG_DM_GPIO)
623static int sun8i_mdio_reset(struct mii_dev *bus)
624{
625 struct udevice *dev = bus->priv;
626 struct emac_eth_dev *priv = dev_get_priv(dev);
627 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
628 int ret;
629
630 if (!dm_gpio_is_valid(&priv->reset_gpio))
631 return 0;
632
633 /* reset the phy */
634 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
635 if (ret)
636 return ret;
637
638 udelay(pdata->reset_delays[0]);
639
640 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
641 if (ret)
642 return ret;
643
644 udelay(pdata->reset_delays[1]);
645
646 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
647 if (ret)
648 return ret;
649
650 udelay(pdata->reset_delays[2]);
651
652 return 0;
653}
654#endif
655
656static int sun8i_mdio_init(const char *name, struct udevice *priv)
a29710c5
AST		 657{
658 struct mii_dev *bus = mdio_alloc();
659
660 if (!bus) {
661 debug("Failed to allocate MDIO bus\n");
662 return -ENOMEM;
663 }
664
665 bus->read = sun8i_mdio_read;
666 bus->write = sun8i_mdio_write;
667 snprintf(bus->name, sizeof(bus->name), name);
668 bus->priv = (void *)priv;
4d555ae3
PT		 669#if defined(CONFIG_DM_GPIO)
670 bus->reset = sun8i_mdio_reset;
671#endif
a29710c5
AST		 672
673 return mdio_register(bus);
674}
675
676static int sun8i_emac_eth_start(struct udevice *dev)
677{
678 struct eth_pdata *pdata = dev_get_platdata(dev);
679
680 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
681}
682
683static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
684{
685 struct emac_eth_dev *priv = dev_get_priv(dev);
686
687 return _sun8i_emac_eth_send(priv, packet, length);
688}
689
690static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
691{
692 struct emac_eth_dev *priv = dev_get_priv(dev);
693
694 return _sun8i_eth_recv(priv, packetp);
695}
696
697static int _sun8i_free_pkt(struct emac_eth_dev *priv)
698{
699 u32 desc_num = priv->rx_currdescnum;
700 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
701 uintptr_t desc_start = (uintptr_t)desc_p;
702 uintptr_t desc_end = desc_start +
703 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
704
705 /* Make the current descriptor valid again */
706 desc_p->status |= BIT(31);
707
708 /* Flush Status field of descriptor */
709 flush_dcache_range(desc_start, desc_end);
710
711 /* Move to next desc and wrap-around condition. */
712 if (++desc_num >= CONFIG_RX_DESCR_NUM)
713 desc_num = 0;
714 priv->rx_currdescnum = desc_num;
715
716 return 0;
717}
718
719static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
720 int length)
721{
722 struct emac_eth_dev *priv = dev_get_priv(dev);
723
724 return _sun8i_free_pkt(priv);
725}
726
727static void sun8i_emac_eth_stop(struct udevice *dev)
728{
729 struct emac_eth_dev *priv = dev_get_priv(dev);
730
731 /* Stop Rx/Tx transmitter */
732 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
733 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
734
735 /* Stop TX DMA */
736 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
737
738 phy_shutdown(priv->phydev);
739}
740
741static int sun8i_emac_eth_probe(struct udevice *dev)
742{
743 struct eth_pdata *pdata = dev_get_platdata(dev);
744 struct emac_eth_dev *priv = dev_get_priv(dev);
745
746 priv->mac_reg = (void *)pdata->iobase;
747
748 sun8i_emac_board_setup(priv);
a85ba87d 749 sun8i_emac_set_syscon(priv);
a29710c5 750
4d555ae3 751 sun8i_mdio_init(dev->name, dev);
a29710c5
AST		 752 priv->bus = miiphy_get_dev_by_name(dev->name);
753
a29710c5
AST		 754 return sun8i_phy_init(priv, dev);
755}
756
757static const struct eth_ops sun8i_emac_eth_ops = {
758 .start = sun8i_emac_eth_start,
759 .write_hwaddr = sun8i_eth_write_hwaddr,
760 .send = sun8i_emac_eth_send,
761 .recv = sun8i_emac_eth_recv,
762 .free_pkt = sun8i_eth_free_pkt,
763 .stop = sun8i_emac_eth_stop,
764};
765
766static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
767{
4d555ae3
PT		 768 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
769 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
a29710c5
AST		 770 struct emac_eth_dev *priv = dev_get_priv(dev);
771 const char *phy_mode;
e160f7d4 772 int node = dev_of_offset(dev);
a29710c5 773 int offset = 0;
4d555ae3
PT		 774#ifdef CONFIG_DM_GPIO
775 int reset_flags = GPIOD_IS_OUT;
776 int ret = 0;
777#endif
a29710c5
AST		 778
779 pdata->iobase = dev_get_addr_name(dev, "emac");
780 priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
781
782 pdata->phy_interface = -1;
783 priv->phyaddr = -1;
784 priv->use_internal_phy = false;
785
e160f7d4 786 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
a29710c5
AST		 787 "phy");
788 if (offset > 0)
789 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
790 -1);
791
e160f7d4 792 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
a29710c5
AST		 793
794 if (phy_mode)
795 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
796 printf("phy interface%d\n", pdata->phy_interface);
797
798 if (pdata->phy_interface == -1) {
799 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
800 return -EINVAL;
801 }
802
803 priv->variant = dev_get_driver_data(dev);
804
805 if (!priv->variant) {
806 printf("%s: Missing variant '%s'\n", __func__,
807 (char *)priv->variant);
808 return -EINVAL;
809 }
810
811 if (priv->variant == H3_EMAC) {
e160f7d4 812 if (fdt_getprop(gd->fdt_blob, node,
a29710c5
AST		 813 "allwinner,use-internal-phy", NULL))
814 priv->use_internal_phy = true;
815 }
816
817 priv->interface = pdata->phy_interface;
818
819 if (!priv->use_internal_phy)
820 parse_phy_pins(dev);
821
4d555ae3
PT		 822#ifdef CONFIG_DM_GPIO
823 if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
824 "snps,reset-active-low"))
825 reset_flags |= GPIOD_ACTIVE_LOW;
826
827 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
828 &priv->reset_gpio, reset_flags);
829
830 if (ret == 0) {
831 ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
832 "snps,reset-delays-us",
833 sun8i_pdata->reset_delays, 3);
834 } else if (ret == -ENOENT) {
835 ret = 0;
836 }
837#endif
838
a29710c5
AST		 839 return 0;
840}
841
842static const struct udevice_id sun8i_emac_eth_ids[] = {
843 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
844 {.compatible = "allwinner,sun50i-a64-emac",
845 .data = (uintptr_t)A64_EMAC },
846 {.compatible = "allwinner,sun8i-a83t-emac",
847 .data = (uintptr_t)A83T_EMAC },
848 { }
849};
850
851U_BOOT_DRIVER(eth_sun8i_emac) = {
852 .name = "eth_sun8i_emac",
853 .id = UCLASS_ETH,
854 .of_match = sun8i_emac_eth_ids,
855 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
856 .probe = sun8i_emac_eth_probe,
857 .ops = &sun8i_emac_eth_ops,
858 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
4d555ae3 859 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
a29710c5
AST		 860 .flags = DM_FLAG_ALLOC_PRIV_DMA,
861};
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