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c609719b WD |
1 | |
2 | /******************************************************************************/ | |
3 | /* */ | |
4 | /* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ | |
5 | /* Corporation. */ | |
6 | /* All rights reserved. */ | |
7 | /* */ | |
8 | /* This program is free software; you can redistribute it and/or modify */ | |
9 | /* it under the terms of the GNU General Public License as published by */ | |
10 | /* the Free Software Foundation, located in the file LICENSE. */ | |
11 | /* */ | |
12 | /* History: */ | |
13 | /* */ | |
14 | /******************************************************************************/ | |
15 | ||
16 | #ifndef TIGON3_H | |
17 | #define TIGON3_H | |
18 | ||
19 | #include "bcm570x_lm.h" | |
20 | #if INCLUDE_TBI_SUPPORT | |
21 | #include "bcm570x_autoneg.h" | |
22 | #endif | |
23 | ||
c609719b WD |
24 | /* io defines */ |
25 | #if !defined(BIG_ENDIAN_HOST) | |
26 | #define readl(addr) \ | |
8bde7f77 | 27 | (LONGSWAP((*(volatile unsigned int *)(addr)))) |
c609719b | 28 | #define writel(b,addr) \ |
8bde7f77 | 29 | ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) |
c609719b | 30 | #else |
f539edc0 | 31 | #if 0 /* !defined(PPC603) */ |
c609719b WD |
32 | #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) |
33 | #define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b)) | |
34 | #else | |
35 | #if 1 | |
36 | #define readl(addr) (*(volatile unsigned int*)(addr)) | |
37 | #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) | |
38 | #else | |
f539edc0 VB |
39 | extern int sprintf (char *buf, const char *f, ...); |
40 | static __inline unsigned int readl (void *addr) | |
41 | { | |
42 | char buf[128]; | |
43 | unsigned int tmp = (*(volatile unsigned int *)(addr)); | |
44 | sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp, | |
45 | addr, 0, 0); | |
46 | sysSerialPrintString (buf); | |
47 | return tmp; | |
c609719b | 48 | } |
f539edc0 VB |
49 | static __inline void writel (unsigned int b, unsigned int addr) |
50 | { | |
51 | char buf[128]; | |
52 | ((*(volatile unsigned int *)(addr)) = (b)); | |
53 | sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b, | |
54 | addr, 0, 0); | |
55 | sysSerialPrintString (buf); | |
c609719b WD |
56 | } |
57 | #endif | |
f539edc0 | 58 | #endif /* PPC603 */ |
c609719b WD |
59 | #endif |
60 | ||
c609719b WD |
61 | /******************************************************************************/ |
62 | /* Constants. */ | |
63 | /******************************************************************************/ | |
64 | ||
65 | /* Maxim number of packet descriptors used for sending packets. */ | |
66 | #define MAX_TX_PACKET_DESC_COUNT 600 | |
67 | #define DEFAULT_TX_PACKET_DESC_COUNT 2 | |
68 | ||
69 | /* Maximum number of packet descriptors used for receiving packets. */ | |
70 | #if T3_JUMBO_RCB_ENTRY_COUNT | |
71 | #define MAX_RX_PACKET_DESC_COUNT \ | |
72 | (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT) | |
73 | #else | |
74 | #define MAX_RX_PACKET_DESC_COUNT 800 | |
75 | #endif | |
76 | #define DEFAULT_RX_PACKET_DESC_COUNT 2 | |
77 | ||
78 | /* Threshhold for double copying small tx packets. 0 will disable double */ | |
79 | /* copying of small Tx packets. */ | |
80 | #define DEFAULT_TX_COPY_BUFFER_SIZE 0 | |
81 | #define MIN_TX_COPY_BUFFER_SIZE 64 | |
82 | #define MAX_TX_COPY_BUFFER_SIZE 512 | |
83 | ||
84 | /* Cache line. */ | |
85 | #define COMMON_CACHE_LINE_SIZE 0x20 | |
86 | #define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1) | |
87 | ||
88 | /* Maximum number of fragment we can handle. */ | |
89 | #ifndef MAX_FRAGMENT_COUNT | |
90 | #define MAX_FRAGMENT_COUNT 32 | |
91 | #endif | |
92 | ||
93 | /* B0 bug. */ | |
94 | #define BCM5700_BX_MIN_FRAG_SIZE 10 | |
f539edc0 | 95 | #define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ |
c609719b WD |
96 | #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) |
97 | #define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ | |
8bde7f77 | 98 | MAX_FRAGMENT_COUNT) |
c609719b WD |
99 | |
100 | /* MAGIC number. */ | |
101 | /* #define T3_MAGIC_NUM 'KevT' */ | |
102 | #define T3_FIRMWARE_MAILBOX 0x0b50 | |
103 | #define T3_MAGIC_NUM 0x4B657654 | |
104 | #define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b | |
105 | ||
106 | #define T3_NIC_DATA_SIG_ADDR 0x0b54 | |
107 | #define T3_NIC_DATA_SIG 0x4b657654 | |
108 | ||
109 | #define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58 | |
110 | #define T3_NIC_CFG_LED_MODE_UNKNOWN BIT_NONE | |
111 | #define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED BIT_2 | |
112 | #define T3_NIC_CFG_LED_MODE_LINK_SPEED BIT_3 | |
113 | #define T3_NIC_CFG_LED_MODE_OPEN_DRAIN BIT_2 | |
114 | #define T3_NIC_CFG_LED_MODE_OUTPUT BIT_3 | |
115 | #define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3) | |
116 | #define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE | |
117 | #define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4 | |
118 | #define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5 | |
119 | #define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5) | |
120 | #define T3_NIC_CFG_ENABLE_WOL BIT_6 | |
121 | #define T3_NIC_CFG_ENABLE_ASF BIT_7 | |
122 | #define T3_NIC_EEPROM_WP BIT_8 | |
123 | ||
124 | #define T3_NIC_DATA_PHY_ID_ADDR 0x0b74 | |
125 | #define T3_NIC_PHY_ID1_MASK 0xffff0000 | |
126 | #define T3_NIC_PHY_ID2_MASK 0x0000ffff | |
127 | ||
128 | #define T3_CMD_MAILBOX 0x0b78 | |
129 | #define T3_CMD_NICDRV_ALIVE 0x01 | |
130 | #define T3_CMD_NICDRV_PAUSE_FW 0x02 | |
131 | #define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03 | |
132 | #define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04 | |
133 | #define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05 | |
134 | #define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06 | |
135 | ||
136 | #define T3_CMD_LENGTH_MAILBOX 0x0b7c | |
137 | #define T3_CMD_DATA_MAILBOX 0x0b80 | |
138 | ||
139 | #define T3_ASF_FW_STATUS_MAILBOX 0x0c00 | |
140 | ||
141 | #define T3_DRV_STATE_MAILBOX 0x0c04 | |
142 | #define T3_DRV_STATE_START 0x01 | |
143 | #define T3_DRV_STATE_UNLOAD 0x02 | |
144 | #define T3_DRV_STATE_WOL 0x03 | |
145 | #define T3_DRV_STATE_SUSPEND 0x04 | |
146 | ||
147 | #define T3_FW_RESET_TYPE_MAILBOX 0x0c08 | |
148 | ||
149 | #define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14 | |
150 | #define T3_MAC_ADDR_LOW_MAILBOX 0x0c18 | |
151 | ||
152 | /******************************************************************************/ | |
153 | /* Hardware constants. */ | |
154 | /******************************************************************************/ | |
155 | ||
156 | /* Number of entries in the send ring: must be 512. */ | |
157 | #define T3_SEND_RCB_ENTRY_COUNT 512 | |
158 | #define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1) | |
159 | ||
160 | /* Number of send RCBs. May be 1-16 but for now, only support one. */ | |
161 | #define T3_MAX_SEND_RCB_COUNT 16 | |
162 | ||
163 | /* Number of entries in the Standard Receive RCB. Must be 512 entries. */ | |
164 | #define T3_STD_RCV_RCB_ENTRY_COUNT 512 | |
165 | #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) | |
f539edc0 | 166 | #define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ |
c609719b WD |
167 | #define MAX_STD_RCV_BUFFER_SIZE 0x600 |
168 | ||
169 | /* Number of entries in the Mini Receive RCB. This value can either be */ | |
170 | /* 0, 1024. Currently Mini Receive RCB is disabled. */ | |
171 | #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT | |
172 | #define T3_MINI_RCV_RCB_ENTRY_COUNT 0 | |
f539edc0 | 173 | #endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ |
c609719b WD |
174 | #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) |
175 | #define MAX_MINI_RCV_BUFFER_SIZE 512 | |
176 | #define DEFAULT_MINI_RCV_BUFFER_SIZE 64 | |
f539edc0 | 177 | #define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ |
c609719b WD |
178 | |
179 | /* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ | |
180 | /* Currently, Jumbo Receive RCB is disabled. */ | |
181 | #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT | |
182 | #define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 | |
f539edc0 | 183 | #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ |
c609719b WD |
184 | #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) |
185 | ||
f539edc0 VB |
186 | #define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ |
187 | #define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ | |
188 | #define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ | |
c609719b | 189 | |
f539edc0 VB |
190 | #define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ |
191 | #define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ | |
c609719b WD |
192 | |
193 | /* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ | |
194 | #define T3_MAX_RCV_RETURN_RCB_COUNT 16 | |
195 | ||
196 | /* Number of entries in a Receive Return ring. This value is either 1024 */ | |
197 | /* or 2048. */ | |
198 | #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT | |
199 | #define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 | |
f539edc0 | 200 | #endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ |
c609719b WD |
201 | #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) |
202 | ||
c609719b WD |
203 | /* Default coalescing parameters. */ |
204 | #define DEFAULT_RX_COALESCING_TICKS 100 | |
205 | #define MAX_RX_COALESCING_TICKS 500 | |
206 | #define DEFAULT_TX_COALESCING_TICKS 400 | |
207 | #define MAX_TX_COALESCING_TICKS 500 | |
208 | #define DEFAULT_RX_MAX_COALESCED_FRAMES 10 | |
209 | #define MAX_RX_MAX_COALESCED_FRAMES 100 | |
210 | #define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5 | |
211 | #define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 42 | |
212 | #define ADAPTIVE_LO_RX_COALESCING_TICKS 50 | |
213 | #define ADAPTIVE_HI_RX_COALESCING_TICKS 300 | |
214 | #define ADAPTIVE_LO_PKT_THRESH 30000 | |
215 | #define ADAPTIVE_HI_PKT_THRESH 74000 | |
216 | #define DEFAULT_TX_MAX_COALESCED_FRAMES 40 | |
217 | #define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 25 | |
218 | #define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75 | |
219 | #define MAX_TX_MAX_COALESCED_FRAMES 100 | |
220 | ||
221 | #define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25 | |
222 | #define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25 | |
223 | #define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 5 | |
224 | #define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5 | |
225 | ||
226 | #define BAD_DEFAULT_VALUE 0xffffffff | |
227 | ||
228 | #define DEFAULT_STATS_COALESCING_TICKS 1000000 | |
229 | #define MAX_STATS_COALESCING_TICKS 3600000000U | |
230 | ||
c609719b WD |
231 | /* Receive BD Replenish thresholds. */ |
232 | #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 | |
233 | #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 | |
234 | ||
235 | #define SPLIT_MODE_DISABLE 0 | |
236 | #define SPLIT_MODE_ENABLE 1 | |
237 | ||
238 | #define SPLIT_MODE_5704_MAX_REQ 3 | |
239 | ||
240 | /* Maximum physical fragment size. */ | |
241 | #define MAX_FRAGMENT_SIZE (64 * 1024) | |
242 | ||
c609719b WD |
243 | /* Standard view. */ |
244 | #define T3_STD_VIEW_SIZE (64 * 1024) | |
245 | #define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) | |
246 | ||
c609719b WD |
247 | /* Buffer descriptor base address on the NIC's memory. */ |
248 | ||
249 | #define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 | |
250 | #define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000 | |
251 | #define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000 | |
252 | ||
253 | #define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000 | |
254 | #define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000 | |
255 | #define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 | |
256 | ||
257 | #define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ | |
8bde7f77 | 258 | sizeof(T3_SND_BD) / 4) |
c609719b WD |
259 | |
260 | #define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ | |
8bde7f77 | 261 | sizeof(T3_RCV_BD) / 4) |
c609719b WD |
262 | |
263 | #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ | |
8bde7f77 | 264 | sizeof(T3_EXT_RCV_BD) / 4) |
c609719b | 265 | |
c609719b WD |
266 | /* MBUF pool. */ |
267 | #define T3_NIC_MBUF_POOL_ADDR 0x8000 | |
268 | /* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */ | |
269 | #define T3_NIC_MBUF_POOL_SIZE96 0x18000 | |
270 | #define T3_NIC_MBUF_POOL_SIZE64 0x10000 | |
271 | ||
c609719b WD |
272 | #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 |
273 | ||
274 | /* DMA descriptor pool */ | |
275 | #define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 | |
f539edc0 | 276 | #define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ |
c609719b WD |
277 | |
278 | #define T3_DEF_DMA_MBUF_LOW_WMARK 0x40 | |
279 | #define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 | |
280 | #define T3_DEF_MBUF_HIGH_WMARK 0x60 | |
281 | ||
282 | #define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304 | |
283 | #define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152 | |
284 | #define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380 | |
285 | ||
286 | #define T3_DEF_DMA_DESC_LOW_WMARK 5 | |
287 | #define T3_DEF_DMA_DESC_HIGH_WMARK 10 | |
288 | ||
289 | /* Maximum size of giant TCP packet can be sent */ | |
290 | #define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000 | |
291 | #define T3_TCP_SEG_MIN_NUM_SEG 20 | |
292 | ||
293 | #define T3_RX_CPU_ID 0x1 | |
294 | #define T3_TX_CPU_ID 0x2 | |
295 | #define T3_RX_CPU_SPAD_ADDR 0x30000 | |
296 | #define T3_RX_CPU_SPAD_SIZE 0x4000 | |
297 | #define T3_TX_CPU_SPAD_ADDR 0x34000 | |
298 | #define T3_TX_CPU_SPAD_SIZE 0x4000 | |
299 | ||
f539edc0 VB |
300 | typedef struct T3_DIR_ENTRY { |
301 | PLM_UINT8 Buffer; | |
302 | LM_UINT32 Offset; | |
303 | LM_UINT32 Length; | |
304 | } T3_DIR_ENTRY, *PT3_DIR_ENTRY; | |
305 | ||
306 | typedef struct T3_FWIMG_INFO { | |
307 | LM_UINT32 StartAddress; | |
308 | T3_DIR_ENTRY Text; | |
309 | T3_DIR_ENTRY ROnlyData; | |
310 | T3_DIR_ENTRY Data; | |
311 | T3_DIR_ENTRY Sbss; | |
312 | T3_DIR_ENTRY Bss; | |
c609719b WD |
313 | } T3_FWIMG_INFO, *PT3_FWIMG_INFO; |
314 | ||
c609719b WD |
315 | /******************************************************************************/ |
316 | /* Tigon3 PCI Registers. */ | |
317 | /******************************************************************************/ | |
318 | #define T3_PCI_ID_BCM5700 0x164414e4 | |
319 | #define T3_PCI_ID_BCM5701 0x164514e4 | |
320 | #define T3_PCI_ID_BCM5702 0x164614e4 | |
321 | #define T3_PCI_ID_BCM5702x 0x16A614e4 | |
322 | #define T3_PCI_ID_BCM5703 0x164714e4 | |
323 | #define T3_PCI_ID_BCM5703x 0x16A714e4 | |
324 | #define T3_PCI_ID_BCM5702FE 0x164D14e4 | |
325 | #define T3_PCI_ID_BCM5704 0x164814e4 | |
326 | ||
327 | #define T3_PCI_VENDOR_ID (T3_PCI_ID & 0xffff) | |
328 | #define T3_PCI_DEVICE_ID (T3_PCI_ID >> 16) | |
329 | ||
330 | #define T3_PCI_MISC_HOST_CTRL_REG 0x68 | |
331 | ||
332 | /* The most significant 16bit of register 0x68. */ | |
333 | /* ChipId:4, ChipRev:4, MetalRev:8 */ | |
334 | #define T3_CHIP_ID_5700_A0 0x7000 | |
335 | #define T3_CHIP_ID_5700_A1 0x7001 | |
336 | #define T3_CHIP_ID_5700_B0 0x7100 | |
337 | #define T3_CHIP_ID_5700_B1 0x7101 | |
338 | #define T3_CHIP_ID_5700_C0 0x7200 | |
339 | ||
340 | #define T3_CHIP_ID_5701_A0 0x0000 | |
341 | #define T3_CHIP_ID_5701_B0 0x0100 | |
342 | #define T3_CHIP_ID_5701_B2 0x0102 | |
343 | #define T3_CHIP_ID_5701_B5 0x0105 | |
344 | ||
345 | #define T3_CHIP_ID_5703_A0 0x1000 | |
346 | #define T3_CHIP_ID_5703_A1 0x1001 | |
347 | #define T3_CHIP_ID_5703_A2 0x1002 | |
348 | ||
349 | #define T3_CHIP_ID_5704_A0 0x2000 | |
350 | ||
351 | /* Chip Id. */ | |
352 | #define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12) | |
353 | #define T3_ASIC_REV_5700 0x07 | |
354 | #define T3_ASIC_REV_5701 0x00 | |
355 | #define T3_ASIC_REV_5703 0x01 | |
356 | #define T3_ASIC_REV_5704 0x02 | |
357 | ||
c609719b WD |
358 | /* Chip id and revision. */ |
359 | #define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) | |
360 | #define T3_CHIP_REV_5700_AX 0x70 | |
361 | #define T3_CHIP_REV_5700_BX 0x71 | |
362 | #define T3_CHIP_REV_5700_CX 0x72 | |
363 | #define T3_CHIP_REV_5701_AX 0x00 | |
364 | ||
365 | /* Metal revision. */ | |
366 | #define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff) | |
367 | #define T3_METAL_REV_A0 0x00 | |
368 | #define T3_METAL_REV_A1 0x01 | |
369 | #define T3_METAL_REV_B0 0x00 | |
370 | #define T3_METAL_REV_B1 0x01 | |
371 | #define T3_METAL_REV_B2 0x02 | |
372 | ||
373 | #define T3_PCI_REG_CLOCK_CTRL 0x74 | |
374 | ||
375 | #define T3_PCI_DISABLE_RX_CLOCK BIT_10 | |
376 | #define T3_PCI_DISABLE_TX_CLOCK BIT_11 | |
377 | #define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12 | |
378 | #define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 | |
379 | #define T3_PCI_44MHZ_CORE_CLOCK BIT_18 | |
380 | ||
c609719b WD |
381 | #define T3_PCI_REG_ADDR_REG 0x78 |
382 | #define T3_PCI_REG_DATA_REG 0x80 | |
383 | ||
384 | #define T3_PCI_MEM_WIN_ADDR_REG 0x7c | |
385 | #define T3_PCI_MEM_WIN_DATA_REG 0x84 | |
386 | ||
387 | #define T3_PCI_PM_CAP_REG 0x48 | |
388 | ||
389 | #define T3_PCI_PM_CAP_PME_D3COLD BIT_31 | |
390 | #define T3_PCI_PM_CAP_PME_D3HOT BIT_30 | |
391 | ||
392 | #define T3_PCI_PM_STATUS_CTRL_REG 0x4c | |
393 | ||
394 | #define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1) | |
395 | #define T3_PM_POWER_STATE_D0 BIT_NONE | |
396 | #define T3_PM_POWER_STATE_D1 BIT_0 | |
397 | #define T3_PM_POWER_STATE_D2 BIT_1 | |
398 | #define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1) | |
399 | ||
400 | #define T3_PM_PME_ENABLE BIT_8 | |
401 | #define T3_PM_PME_ASSERTED BIT_15 | |
402 | ||
c609719b WD |
403 | /* PCI state register. */ |
404 | #define T3_PCI_STATE_REG 0x70 | |
405 | ||
406 | #define T3_PCI_STATE_FORCE_RESET BIT_0 | |
407 | #define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1 | |
408 | #define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2 | |
409 | #define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 | |
410 | #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 | |
411 | ||
c609719b WD |
412 | /* Broadcom subsystem/subvendor IDs. */ |
413 | #define T3_SVID_BROADCOM 0x14e4 | |
414 | ||
415 | #define T3_SSID_BROADCOM_BCM95700A6 0x1644 | |
416 | #define T3_SSID_BROADCOM_BCM95701A5 0x0001 | |
f539edc0 VB |
417 | #define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ |
418 | #define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ | |
c609719b WD |
419 | #define T3_SSID_BROADCOM_BCM95701T1 0x0005 |
420 | #define T3_SSID_BROADCOM_BCM95701T8 0x0006 | |
f539edc0 | 421 | #define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ |
c609719b WD |
422 | #define T3_SSID_BROADCOM_BCM95701A10 0x0008 |
423 | #define T3_SSID_BROADCOM_BCM95701A12 0x8008 | |
424 | #define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 | |
425 | #define T3_SSID_BROADCOM_BCM95703Ax2 0x8009 | |
426 | ||
427 | /* 3COM subsystem/subvendor IDs. */ | |
428 | #define T3_SVID_3COM 0x10b7 | |
429 | ||
430 | #define T3_SSID_3COM_3C996T 0x1000 | |
431 | #define T3_SSID_3COM_3C996BT 0x1006 | |
432 | #define T3_SSID_3COM_3C996CT 0x1002 | |
433 | #define T3_SSID_3COM_3C997T 0x1003 | |
434 | #define T3_SSID_3COM_3C1000T 0x1007 | |
435 | #define T3_SSID_3COM_3C940BR01 0x1008 | |
436 | ||
437 | /* Fiber boards. */ | |
438 | #define T3_SSID_3COM_3C996SX 0x1004 | |
439 | #define T3_SSID_3COM_3C997SX 0x1005 | |
440 | ||
c609719b WD |
441 | /* Dell subsystem/subvendor IDs. */ |
442 | ||
443 | #define T3_SVID_DELL 0x1028 | |
444 | ||
445 | #define T3_SSID_DELL_VIPER 0x00d1 | |
446 | #define T3_SSID_DELL_JAGUAR 0x0106 | |
447 | #define T3_SSID_DELL_MERLOT 0x0109 | |
448 | #define T3_SSID_DELL_SLIM_MERLOT 0x010a | |
449 | ||
450 | /* Compaq subsystem/subvendor IDs */ | |
451 | ||
452 | #define T3_SVID_COMPAQ 0x0e11 | |
453 | ||
454 | #define T3_SSID_COMPAQ_BANSHEE 0x007c | |
455 | #define T3_SSID_COMPAQ_BANSHEE_2 0x009a | |
456 | #define T3_SSID_COMPAQ_CHANGELING 0x007d | |
457 | #define T3_SSID_COMPAQ_NC7780 0x0085 | |
458 | #define T3_SSID_COMPAQ_NC7780_2 0x0099 | |
459 | ||
c609719b WD |
460 | /******************************************************************************/ |
461 | /* MII registers. */ | |
462 | /******************************************************************************/ | |
463 | ||
464 | /* Control register. */ | |
465 | #define PHY_CTRL_REG 0x00 | |
466 | ||
467 | #define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) | |
468 | #define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE | |
469 | #define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 | |
470 | #define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 | |
471 | #define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 | |
472 | #define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 | |
473 | #define PHY_CTRL_RESTART_AUTO_NEG BIT_9 | |
474 | #define PHY_CTRL_ISOLATE_PHY BIT_10 | |
475 | #define PHY_CTRL_LOWER_POWER_MODE BIT_11 | |
476 | #define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 | |
477 | #define PHY_CTRL_LOOPBACK_MODE BIT_14 | |
478 | #define PHY_CTRL_PHY_RESET BIT_15 | |
479 | ||
c609719b WD |
480 | /* Status register. */ |
481 | #define PHY_STATUS_REG 0x01 | |
482 | ||
483 | #define PHY_STATUS_LINK_PASS BIT_2 | |
484 | #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 | |
485 | ||
c609719b WD |
486 | /* Phy Id registers. */ |
487 | #define PHY_ID1_REG 0x02 | |
488 | #define PHY_ID1_OUI_MASK 0xffff | |
489 | ||
490 | #define PHY_ID2_REG 0x03 | |
491 | #define PHY_ID2_REV_MASK 0x000f | |
492 | #define PHY_ID2_MODEL_MASK 0x03f0 | |
493 | #define PHY_ID2_OUI_MASK 0xfc00 | |
494 | ||
c609719b WD |
495 | /* Auto-negotiation advertisement register. */ |
496 | #define PHY_AN_AD_REG 0x04 | |
497 | ||
498 | #define PHY_AN_AD_ASYM_PAUSE BIT_11 | |
499 | #define PHY_AN_AD_PAUSE_CAPABLE BIT_10 | |
500 | #define PHY_AN_AD_10BASET_HALF BIT_5 | |
501 | #define PHY_AN_AD_10BASET_FULL BIT_6 | |
502 | #define PHY_AN_AD_100BASETX_HALF BIT_7 | |
503 | #define PHY_AN_AD_100BASETX_FULL BIT_8 | |
504 | #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 | |
505 | ||
c609719b WD |
506 | /* Auto-negotiation Link Partner Ability register. */ |
507 | #define PHY_LINK_PARTNER_ABILITY_REG 0x05 | |
508 | ||
509 | #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 | |
510 | #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 | |
511 | ||
c609719b WD |
512 | /* Auto-negotiation expansion register. */ |
513 | #define PHY_AN_EXPANSION_REG 0x06 | |
514 | ||
c609719b WD |
515 | /******************************************************************************/ |
516 | /* BCM5400 and BCM5401 phy info. */ | |
517 | /******************************************************************************/ | |
518 | ||
519 | #define PHY_DEVICE_ID 1 | |
520 | ||
521 | /* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */ | |
522 | #define PHY_UNKNOWN_PHY 0x00000000 | |
523 | #define PHY_BCM5400_PHY_ID 0x60008040 | |
524 | #define PHY_BCM5401_PHY_ID 0x60008050 | |
525 | #define PHY_BCM5411_PHY_ID 0x60008070 | |
526 | #define PHY_BCM5701_PHY_ID 0x60008110 | |
527 | #define PHY_BCM5703_PHY_ID 0x60008160 | |
528 | #define PHY_BCM5704_PHY_ID 0x60008190 | |
529 | #define PHY_BCM8002_PHY_ID 0x60010140 | |
530 | ||
531 | #define PHY_BCM5401_B0_REV 0x1 | |
532 | #define PHY_BCM5401_B2_REV 0x3 | |
533 | #define PHY_BCM5401_C0_REV 0x6 | |
534 | ||
535 | #define PHY_ID_OUI_MASK 0xfffffc00 | |
536 | #define PHY_ID_MODEL_MASK 0x000003f0 | |
537 | #define PHY_ID_REV_MASK 0x0000000f | |
538 | #define PHY_ID_MASK (PHY_ID_OUI_MASK | \ | |
8bde7f77 | 539 | PHY_ID_MODEL_MASK) |
c609719b | 540 | |
c609719b | 541 | #define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ |
8bde7f77 WD |
542 | (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ |
543 | (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ | |
544 | (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ | |
545 | (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ | |
546 | (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ | |
547 | (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) | |
c609719b | 548 | |
c609719b WD |
549 | /* 1000Base-T control register. */ |
550 | #define BCM540X_1000BASET_CTRL_REG 0x09 | |
551 | ||
552 | #define BCM540X_AN_AD_1000BASET_HALF BIT_8 | |
553 | #define BCM540X_AN_AD_1000BASET_FULL BIT_9 | |
554 | #define BCM540X_CONFIG_AS_MASTER BIT_11 | |
555 | #define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 | |
556 | ||
c609719b WD |
557 | /* Extended control register. */ |
558 | #define BCM540X_EXT_CTRL_REG 0x10 | |
559 | ||
560 | #define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 | |
561 | #define BCM540X_EXT_CTRL_TBI BIT_15 | |
562 | ||
563 | /* PHY extended status register. */ | |
564 | #define BCM540X_EXT_STATUS_REG 0x11 | |
565 | ||
566 | #define BCM540X_EXT_STATUS_LINK_PASS BIT_8 | |
567 | ||
c609719b WD |
568 | /* DSP Coefficient Read/Write Port. */ |
569 | #define BCM540X_DSP_RW_PORT 0x15 | |
570 | ||
c609719b WD |
571 | /* DSP Coeficient Address Register. */ |
572 | #define BCM540X_DSP_ADDRESS_REG 0x17 | |
573 | ||
574 | #define BCM540X_DSP_TAP_NUMBER_MASK 0x00 | |
575 | #define BCM540X_DSP_AGC_A 0x00 | |
576 | #define BCM540X_DSP_AGC_B 0x01 | |
577 | #define BCM540X_DSP_MSE_PAIR_STATUS 0x02 | |
578 | #define BCM540X_DSP_SOFT_DECISION 0x03 | |
579 | #define BCM540X_DSP_PHASE_REG 0x04 | |
580 | #define BCM540X_DSP_SKEW 0x05 | |
581 | #define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 | |
582 | #define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 | |
583 | #define BCM540X_DSP_LAST_ECHO 0x08 | |
584 | #define BCM540X_DSP_FREQUENCY 0x09 | |
585 | #define BCM540X_DSP_PLL_BANDWIDTH 0x0a | |
586 | #define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b | |
587 | ||
588 | #define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) | |
589 | #define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) | |
590 | #define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) | |
591 | #define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) | |
592 | #define BCM540X_DSP_FILTER_FEXT0 BIT_11 | |
593 | #define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) | |
594 | #define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) | |
595 | #define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) | |
596 | #define BCM540X_DSP_FILTER_NEXT0 BIT_10 | |
597 | #define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) | |
598 | #define BCM540X_DSP_FILTER_DFE BIT_9 | |
599 | #define BCM540X_DSP_FILTER_FFE BIT_8 | |
600 | ||
601 | #define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 | |
602 | ||
603 | #define BCM540X_DSP_SEL_CH_0 BIT_NONE | |
604 | #define BCM540X_DSP_SEL_CH_1 BIT_13 | |
605 | #define BCM540X_DSP_SEL_CH_2 BIT_14 | |
606 | #define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) | |
607 | ||
608 | #define BCM540X_CONTROL_ALL_CHANNELS BIT_15 | |
609 | ||
c609719b WD |
610 | /* Auxilliary Control Register (Shadow Register) */ |
611 | #define BCM5401_AUX_CTRL 0x18 | |
612 | ||
613 | #define BCM5401_SHADOW_SEL_MASK 0x7 | |
614 | #define BCM5401_SHADOW_SEL_NORMAL 0x00 | |
615 | #define BCM5401_SHADOW_SEL_10BASET 0x01 | |
616 | #define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 | |
617 | #define BCM5401_SHADOW_SEL_IP_PHONE 0x03 | |
618 | #define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 | |
619 | #define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 | |
620 | #define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 | |
621 | ||
c609719b WD |
622 | /* Shadow register selector == '000' */ |
623 | #define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 | |
624 | #define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 | |
625 | #define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 | |
626 | #define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 | |
627 | #define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 | |
628 | #define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE | |
629 | #define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 | |
630 | #define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 | |
631 | #define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) | |
632 | #define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 | |
633 | #define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 | |
634 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE | |
635 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 | |
636 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 | |
637 | #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) | |
638 | #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 | |
639 | #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 | |
640 | ||
c609719b WD |
641 | /* Auxilliary status summary. */ |
642 | #define BCM540X_AUX_STATUS_REG 0x19 | |
643 | ||
644 | #define BCM540X_AUX_LINK_PASS BIT_2 | |
645 | #define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) | |
646 | #define BCM540X_AUX_10BASET_HD BIT_8 | |
647 | #define BCM540X_AUX_10BASET_FD BIT_9 | |
648 | #define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) | |
649 | #define BCM540X_AUX_100BASET4 BIT_10 | |
650 | #define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) | |
651 | #define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) | |
652 | #define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) | |
653 | ||
c609719b WD |
654 | /* Interrupt status. */ |
655 | #define BCM540X_INT_STATUS_REG 0x1a | |
656 | ||
657 | #define BCM540X_INT_LINK_CHANGE BIT_1 | |
658 | #define BCM540X_INT_SPEED_CHANGE BIT_2 | |
659 | #define BCM540X_INT_DUPLEX_CHANGE BIT_3 | |
660 | #define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 | |
661 | ||
c609719b WD |
662 | /* Interrupt mask register. */ |
663 | #define BCM540X_INT_MASK_REG 0x1b | |
664 | ||
c609719b WD |
665 | /******************************************************************************/ |
666 | /* Register definitions. */ | |
667 | /******************************************************************************/ | |
668 | ||
669 | typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER; | |
670 | typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; | |
671 | typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; | |
672 | ||
673 | typedef struct { | |
f539edc0 VB |
674 | /* Big endian format. */ |
675 | T3_32BIT_REGISTER High; | |
676 | T3_32BIT_REGISTER Low; | |
c609719b WD |
677 | } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; |
678 | ||
679 | typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; | |
680 | ||
681 | #define T3_NUM_OF_DMA_DESC 256 | |
682 | #define T3_NUM_OF_MBUF 768 | |
683 | ||
f539edc0 VB |
684 | typedef struct { |
685 | T3_64BIT_REGISTER host_addr; | |
686 | T3_32BIT_REGISTER nic_mbuf; | |
687 | T3_16BIT_REGISTER len; | |
688 | T3_16BIT_REGISTER cqid_sqid; | |
689 | T3_32BIT_REGISTER flags; | |
690 | T3_32BIT_REGISTER opaque1; | |
691 | T3_32BIT_REGISTER opaque2; | |
692 | T3_32BIT_REGISTER opaque3; | |
693 | } T3_DMA_DESC, *PT3_DMA_DESC; | |
c609719b | 694 | |
c609719b WD |
695 | /******************************************************************************/ |
696 | /* Ring control block. */ | |
697 | /******************************************************************************/ | |
698 | ||
699 | typedef struct { | |
f539edc0 | 700 | T3_64BIT_REGISTER HostRingAddr; |
c609719b | 701 | |
f539edc0 VB |
702 | union { |
703 | struct { | |
c609719b | 704 | #ifdef BIG_ENDIAN_HOST |
f539edc0 VB |
705 | T3_16BIT_REGISTER MaxLen; |
706 | T3_16BIT_REGISTER Flags; | |
707 | #else /* BIG_ENDIAN_HOST */ | |
708 | T3_16BIT_REGISTER Flags; | |
709 | T3_16BIT_REGISTER MaxLen; | |
c609719b | 710 | #endif |
f539edc0 | 711 | } s; |
c609719b | 712 | |
f539edc0 VB |
713 | T3_32BIT_REGISTER MaxLen_Flags; |
714 | } u; | |
c609719b | 715 | |
f539edc0 | 716 | T3_32BIT_REGISTER NicRingAddr; |
c609719b WD |
717 | } T3_RCB, *PT3_RCB; |
718 | ||
719 | #define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 | |
720 | #define T3_RCB_FLAG_RING_DISABLED BIT_1 | |
721 | ||
c609719b WD |
722 | /******************************************************************************/ |
723 | /* Status block. */ | |
724 | /******************************************************************************/ | |
725 | ||
726 | /* | |
727 | * Size of status block is actually 0x50 bytes. Use 0x80 bytes for | |
728 | * cache line alignment. | |
729 | */ | |
730 | #define T3_STATUS_BLOCK_SIZE 0x80 | |
731 | ||
732 | typedef struct { | |
f539edc0 VB |
733 | volatile LM_UINT32 Status; |
734 | #define STATUS_BLOCK_UPDATED BIT_0 | |
735 | #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 | |
736 | #define STATUS_BLOCK_ERROR BIT_2 | |
c609719b | 737 | |
f539edc0 | 738 | volatile LM_UINT32 StatusTag; |
c609719b WD |
739 | |
740 | #ifdef BIG_ENDIAN_HOST | |
f539edc0 VB |
741 | volatile LM_UINT16 RcvStdConIdx; |
742 | volatile LM_UINT16 RcvJumboConIdx; | |
743 | ||
744 | volatile LM_UINT16 Reserved2; | |
745 | volatile LM_UINT16 RcvMiniConIdx; | |
746 | ||
747 | struct { | |
748 | volatile LM_UINT16 SendConIdx; /* Send consumer index. */ | |
749 | volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ | |
750 | } Idx[16]; | |
751 | #else /* BIG_ENDIAN_HOST */ | |
752 | volatile LM_UINT16 RcvJumboConIdx; | |
753 | volatile LM_UINT16 RcvStdConIdx; | |
754 | ||
755 | volatile LM_UINT16 RcvMiniConIdx; | |
756 | volatile LM_UINT16 Reserved2; | |
757 | ||
758 | struct { | |
759 | volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ | |
760 | volatile LM_UINT16 SendConIdx; /* Send consumer index. */ | |
761 | } Idx[16]; | |
c609719b WD |
762 | #endif |
763 | } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; | |
764 | ||
c609719b WD |
765 | /******************************************************************************/ |
766 | /* Receive buffer descriptors. */ | |
767 | /******************************************************************************/ | |
768 | ||
769 | typedef struct { | |
f539edc0 | 770 | T3_64BIT_HOST_ADDR HostAddr; |
c609719b WD |
771 | |
772 | #ifdef BIG_ENDIAN_HOST | |
f539edc0 VB |
773 | volatile LM_UINT16 Index; |
774 | volatile LM_UINT16 Len; | |
c609719b | 775 | |
f539edc0 VB |
776 | volatile LM_UINT16 Type; |
777 | volatile LM_UINT16 Flags; | |
c609719b | 778 | |
f539edc0 VB |
779 | volatile LM_UINT16 IpCksum; |
780 | volatile LM_UINT16 TcpUdpCksum; | |
c609719b | 781 | |
f539edc0 VB |
782 | volatile LM_UINT16 ErrorFlag; |
783 | volatile LM_UINT16 VlanTag; | |
784 | #else /* BIG_ENDIAN_HOST */ | |
785 | volatile LM_UINT16 Len; | |
786 | volatile LM_UINT16 Index; | |
c609719b | 787 | |
f539edc0 VB |
788 | volatile LM_UINT16 Flags; |
789 | volatile LM_UINT16 Type; | |
c609719b | 790 | |
f539edc0 VB |
791 | volatile LM_UINT16 TcpUdpCksum; |
792 | volatile LM_UINT16 IpCksum; | |
c609719b | 793 | |
f539edc0 VB |
794 | volatile LM_UINT16 VlanTag; |
795 | volatile LM_UINT16 ErrorFlag; | |
c609719b WD |
796 | #endif |
797 | ||
f539edc0 VB |
798 | volatile LM_UINT32 Reserved; |
799 | volatile LM_UINT32 Opaque; | |
c609719b WD |
800 | } T3_RCV_BD, *PT3_RCV_BD; |
801 | ||
c609719b | 802 | typedef struct { |
f539edc0 | 803 | T3_64BIT_HOST_ADDR HostAddr[3]; |
c609719b WD |
804 | |
805 | #ifdef BIG_ENDIAN_HOST | |
f539edc0 VB |
806 | LM_UINT16 Len1; |
807 | LM_UINT16 Len2; | |
c609719b | 808 | |
f539edc0 VB |
809 | LM_UINT16 Len3; |
810 | LM_UINT16 Reserved1; | |
811 | #else /* BIG_ENDIAN_HOST */ | |
812 | LM_UINT16 Len2; | |
813 | LM_UINT16 Len1; | |
c609719b | 814 | |
f539edc0 VB |
815 | LM_UINT16 Reserved1; |
816 | LM_UINT16 Len3; | |
c609719b WD |
817 | #endif |
818 | ||
f539edc0 | 819 | T3_RCV_BD StdRcvBd; |
c609719b WD |
820 | } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; |
821 | ||
c609719b WD |
822 | /* Error flags. */ |
823 | #define RCV_BD_ERR_BAD_CRC 0x0001 | |
824 | #define RCV_BD_ERR_COLL_DETECT 0x0002 | |
825 | #define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004 | |
826 | #define RCV_BD_ERR_PHY_DECODE_ERR 0x0008 | |
827 | #define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010 | |
828 | #define RCV_BD_ERR_MAC_ABORT 0x0020 | |
829 | #define RCV_BD_ERR_LEN_LT_64 0x0040 | |
830 | #define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 | |
831 | #define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 | |
832 | ||
c609719b WD |
833 | /* Buffer descriptor flags. */ |
834 | #define RCV_BD_FLAG_END 0x0004 | |
835 | #define RCV_BD_FLAG_JUMBO_RING 0x0020 | |
836 | #define RCV_BD_FLAG_VLAN_TAG 0x0040 | |
837 | #define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400 | |
838 | #define RCV_BD_FLAG_MINI_RING 0x0800 | |
839 | #define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000 | |
840 | #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 | |
841 | #define RCV_BD_FLAG_TCP_PACKET 0x4000 | |
842 | ||
c609719b WD |
843 | /******************************************************************************/ |
844 | /* Send buffer descriptor. */ | |
845 | /******************************************************************************/ | |
846 | ||
847 | typedef struct { | |
f539edc0 | 848 | T3_64BIT_HOST_ADDR HostAddr; |
c609719b | 849 | |
f539edc0 VB |
850 | union { |
851 | struct { | |
c609719b | 852 | #ifdef BIG_ENDIAN_HOST |
f539edc0 VB |
853 | LM_UINT16 Len; |
854 | LM_UINT16 Flags; | |
855 | #else /* BIG_ENDIAN_HOST */ | |
856 | LM_UINT16 Flags; | |
857 | LM_UINT16 Len; | |
c609719b | 858 | #endif |
f539edc0 | 859 | } s1; |
c609719b | 860 | |
f539edc0 VB |
861 | LM_UINT32 Len_Flags; |
862 | } u1; | |
c609719b | 863 | |
f539edc0 VB |
864 | union { |
865 | struct { | |
c609719b | 866 | #ifdef BIG_ENDIAN_HOST |
f539edc0 VB |
867 | LM_UINT16 Reserved; |
868 | LM_UINT16 VlanTag; | |
869 | #else /* BIG_ENDIAN_HOST */ | |
870 | LM_UINT16 VlanTag; | |
871 | LM_UINT16 Reserved; | |
c609719b | 872 | #endif |
f539edc0 | 873 | } s2; |
c609719b | 874 | |
f539edc0 VB |
875 | LM_UINT32 VlanTag; |
876 | } u2; | |
c609719b WD |
877 | } T3_SND_BD, *PT3_SND_BD; |
878 | ||
c609719b WD |
879 | /* Send buffer descriptor flags. */ |
880 | #define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 | |
881 | #define SND_BD_FLAG_IP_CKSUM 0x0002 | |
882 | #define SND_BD_FLAG_END 0x0004 | |
883 | #define SND_BD_FLAG_IP_FRAG 0x0008 | |
884 | #define SND_BD_FLAG_IP_FRAG_END 0x0010 | |
885 | #define SND_BD_FLAG_VLAN_TAG 0x0040 | |
886 | #define SND_BD_FLAG_COAL_NOW 0x0080 | |
887 | #define SND_BD_FLAG_CPU_PRE_DMA 0x0100 | |
888 | #define SND_BD_FLAG_CPU_POST_DMA 0x0200 | |
889 | #define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000 | |
890 | #define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000 | |
891 | #define SND_BD_FLAG_DONT_GEN_CRC 0x8000 | |
892 | ||
893 | /* MBUFs */ | |
894 | typedef struct T3_MBUF_FRAME_DESC { | |
895 | #ifdef BIG_ENDIAN_HOST | |
f539edc0 VB |
896 | LM_UINT32 status_control; |
897 | union { | |
898 | struct { | |
899 | LM_UINT8 cqid; | |
900 | LM_UINT8 reserved1; | |
901 | LM_UINT16 length; | |
902 | } s1; | |
903 | LM_UINT32 word; | |
904 | } u1; | |
905 | union { | |
906 | struct { | |
907 | LM_UINT16 ip_hdr_start; | |
908 | LM_UINT16 tcp_udp_hdr_start; | |
909 | } s2; | |
910 | ||
911 | LM_UINT32 word; | |
912 | } u2; | |
913 | ||
914 | union { | |
915 | struct { | |
916 | LM_UINT16 data_start; | |
917 | LM_UINT16 vlan_id; | |
918 | } s3; | |
919 | ||
920 | LM_UINT32 word; | |
921 | } u3; | |
922 | ||
923 | union { | |
924 | struct { | |
925 | LM_UINT16 ip_checksum; | |
926 | LM_UINT16 tcp_udp_checksum; | |
927 | } s4; | |
928 | ||
929 | LM_UINT32 word; | |
930 | } u4; | |
931 | ||
932 | union { | |
933 | struct { | |
934 | LM_UINT16 pseudo_checksum; | |
935 | LM_UINT16 checksum_status; | |
936 | } s5; | |
937 | ||
938 | LM_UINT32 word; | |
939 | } u5; | |
940 | ||
941 | union { | |
942 | struct { | |
943 | LM_UINT16 rule_match; | |
944 | LM_UINT8 class; | |
945 | LM_UINT8 rupt; | |
946 | } s6; | |
947 | ||
948 | LM_UINT32 word; | |
949 | } u6; | |
950 | ||
951 | union { | |
952 | struct { | |
953 | LM_UINT16 reserved2; | |
954 | LM_UINT16 mbuf_num; | |
955 | } s7; | |
956 | ||
957 | LM_UINT32 word; | |
958 | } u7; | |
959 | ||
960 | LM_UINT32 reserved3; | |
961 | LM_UINT32 reserved4; | |
c609719b | 962 | #else |
f539edc0 VB |
963 | LM_UINT32 status_control; |
964 | union { | |
965 | struct { | |
966 | LM_UINT16 length; | |
967 | LM_UINT8 reserved1; | |
968 | LM_UINT8 cqid; | |
969 | } s1; | |
970 | LM_UINT32 word; | |
971 | } u1; | |
972 | union { | |
973 | struct { | |
974 | LM_UINT16 tcp_udp_hdr_start; | |
975 | LM_UINT16 ip_hdr_start; | |
976 | } s2; | |
977 | ||
978 | LM_UINT32 word; | |
979 | } u2; | |
980 | ||
981 | union { | |
982 | struct { | |
983 | LM_UINT16 vlan_id; | |
984 | LM_UINT16 data_start; | |
985 | } s3; | |
986 | ||
987 | LM_UINT32 word; | |
988 | } u3; | |
989 | ||
990 | union { | |
991 | struct { | |
992 | LM_UINT16 tcp_udp_checksum; | |
993 | LM_UINT16 ip_checksum; | |
994 | } s4; | |
995 | ||
996 | LM_UINT32 word; | |
997 | } u4; | |
998 | ||
999 | union { | |
1000 | struct { | |
1001 | LM_UINT16 checksum_status; | |
1002 | LM_UINT16 pseudo_checksum; | |
1003 | } s5; | |
1004 | ||
1005 | LM_UINT32 word; | |
1006 | } u5; | |
1007 | ||
1008 | union { | |
1009 | struct { | |
1010 | LM_UINT8 rupt; | |
1011 | LM_UINT8 class; | |
1012 | LM_UINT16 rule_match; | |
1013 | } s6; | |
1014 | ||
1015 | LM_UINT32 word; | |
1016 | } u6; | |
1017 | ||
1018 | union { | |
1019 | struct { | |
1020 | LM_UINT16 mbuf_num; | |
1021 | LM_UINT16 reserved2; | |
1022 | } s7; | |
1023 | ||
1024 | LM_UINT32 word; | |
1025 | } u7; | |
1026 | ||
1027 | LM_UINT32 reserved3; | |
1028 | LM_UINT32 reserved4; | |
c609719b | 1029 | #endif |
f539edc0 | 1030 | } T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC; |
c609719b WD |
1031 | |
1032 | typedef struct T3_MBUF_HDR { | |
f539edc0 VB |
1033 | union { |
1034 | struct { | |
1035 | unsigned int C:1; | |
1036 | unsigned int F:1; | |
1037 | unsigned int reserved1:7; | |
1038 | unsigned int next_mbuf:16; | |
1039 | unsigned int length:7; | |
1040 | } s1; | |
1041 | ||
1042 | LM_UINT32 word; | |
1043 | } u1; | |
1044 | ||
1045 | LM_UINT32 next_frame_ptr; | |
1046 | } T3_MBUF_HDR, *PT3_MBUF_HDR; | |
1047 | ||
1048 | typedef struct T3_MBUF { | |
1049 | T3_MBUF_HDR hdr; | |
1050 | union { | |
1051 | struct { | |
1052 | T3_MBUF_FRAME_DESC frame_hdr; | |
1053 | LM_UINT32 data[20]; | |
1054 | } s1; | |
1055 | ||
1056 | struct { | |
1057 | LM_UINT32 data[30]; | |
1058 | } s2; | |
1059 | } body; | |
1060 | } T3_MBUF, *PT3_MBUF; | |
c609719b WD |
1061 | |
1062 | #define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) | |
1063 | #define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) | |
1064 | ||
c609719b WD |
1065 | /******************************************************************************/ |
1066 | /* Statistics block. */ | |
1067 | /******************************************************************************/ | |
1068 | ||
1069 | typedef struct { | |
f539edc0 VB |
1070 | LM_UINT8 Reserved0[0x400 - 0x300]; |
1071 | ||
1072 | /* Statistics maintained by Receive MAC. */ | |
1073 | T3_64BIT_REGISTER ifHCInOctets; | |
1074 | T3_64BIT_REGISTER Reserved1; | |
1075 | T3_64BIT_REGISTER etherStatsFragments; | |
1076 | T3_64BIT_REGISTER ifHCInUcastPkts; | |
1077 | T3_64BIT_REGISTER ifHCInMulticastPkts; | |
1078 | T3_64BIT_REGISTER ifHCInBroadcastPkts; | |
1079 | T3_64BIT_REGISTER dot3StatsFCSErrors; | |
1080 | T3_64BIT_REGISTER dot3StatsAlignmentErrors; | |
1081 | T3_64BIT_REGISTER xonPauseFramesReceived; | |
1082 | T3_64BIT_REGISTER xoffPauseFramesReceived; | |
1083 | T3_64BIT_REGISTER macControlFramesReceived; | |
1084 | T3_64BIT_REGISTER xoffStateEntered; | |
1085 | T3_64BIT_REGISTER dot3StatsFramesTooLong; | |
1086 | T3_64BIT_REGISTER etherStatsJabbers; | |
1087 | T3_64BIT_REGISTER etherStatsUndersizePkts; | |
1088 | T3_64BIT_REGISTER inRangeLengthError; | |
1089 | T3_64BIT_REGISTER outRangeLengthError; | |
1090 | T3_64BIT_REGISTER etherStatsPkts64Octets; | |
1091 | T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; | |
1092 | T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; | |
1093 | T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; | |
1094 | T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; | |
1095 | T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; | |
1096 | T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; | |
1097 | T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; | |
1098 | T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; | |
1099 | T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; | |
1100 | ||
1101 | T3_64BIT_REGISTER Unused1[37]; | |
1102 | ||
1103 | /* Statistics maintained by Transmit MAC. */ | |
1104 | T3_64BIT_REGISTER ifHCOutOctets; | |
1105 | T3_64BIT_REGISTER Reserved2; | |
1106 | T3_64BIT_REGISTER etherStatsCollisions; | |
1107 | T3_64BIT_REGISTER outXonSent; | |
1108 | T3_64BIT_REGISTER outXoffSent; | |
1109 | T3_64BIT_REGISTER flowControlDone; | |
1110 | T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; | |
1111 | T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; | |
1112 | T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; | |
1113 | T3_64BIT_REGISTER dot3StatsDeferredTransmissions; | |
1114 | T3_64BIT_REGISTER Reserved3; | |
1115 | T3_64BIT_REGISTER dot3StatsExcessiveCollisions; | |
1116 | T3_64BIT_REGISTER dot3StatsLateCollisions; | |
1117 | T3_64BIT_REGISTER dot3Collided2Times; | |
1118 | T3_64BIT_REGISTER dot3Collided3Times; | |
1119 | T3_64BIT_REGISTER dot3Collided4Times; | |
1120 | T3_64BIT_REGISTER dot3Collided5Times; | |
1121 | T3_64BIT_REGISTER dot3Collided6Times; | |
1122 | T3_64BIT_REGISTER dot3Collided7Times; | |
1123 | T3_64BIT_REGISTER dot3Collided8Times; | |
1124 | T3_64BIT_REGISTER dot3Collided9Times; | |
1125 | T3_64BIT_REGISTER dot3Collided10Times; | |
1126 | T3_64BIT_REGISTER dot3Collided11Times; | |
1127 | T3_64BIT_REGISTER dot3Collided12Times; | |
1128 | T3_64BIT_REGISTER dot3Collided13Times; | |
1129 | T3_64BIT_REGISTER dot3Collided14Times; | |
1130 | T3_64BIT_REGISTER dot3Collided15Times; | |
1131 | T3_64BIT_REGISTER ifHCOutUcastPkts; | |
1132 | T3_64BIT_REGISTER ifHCOutMulticastPkts; | |
1133 | T3_64BIT_REGISTER ifHCOutBroadcastPkts; | |
1134 | T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; | |
1135 | T3_64BIT_REGISTER ifOutDiscards; | |
1136 | T3_64BIT_REGISTER ifOutErrors; | |
1137 | ||
1138 | T3_64BIT_REGISTER Unused2[31]; | |
1139 | ||
1140 | /* Statistics maintained by Receive List Placement. */ | |
1141 | T3_64BIT_REGISTER COSIfHCInPkts[16]; | |
1142 | T3_64BIT_REGISTER COSFramesDroppedDueToFilters; | |
1143 | T3_64BIT_REGISTER nicDmaWriteQueueFull; | |
1144 | T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; | |
1145 | T3_64BIT_REGISTER nicNoMoreRxBDs; | |
1146 | T3_64BIT_REGISTER ifInDiscards; | |
1147 | T3_64BIT_REGISTER ifInErrors; | |
1148 | T3_64BIT_REGISTER nicRecvThresholdHit; | |
1149 | ||
1150 | T3_64BIT_REGISTER Unused3[9]; | |
1151 | ||
1152 | /* Statistics maintained by Send Data Initiator. */ | |
1153 | T3_64BIT_REGISTER COSIfHCOutPkts[16]; | |
1154 | T3_64BIT_REGISTER nicDmaReadQueueFull; | |
1155 | T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; | |
1156 | T3_64BIT_REGISTER nicSendDataCompQueueFull; | |
1157 | ||
1158 | /* Statistics maintained by Host Coalescing. */ | |
1159 | T3_64BIT_REGISTER nicRingSetSendProdIndex; | |
1160 | T3_64BIT_REGISTER nicRingStatusUpdate; | |
1161 | T3_64BIT_REGISTER nicInterrupts; | |
1162 | T3_64BIT_REGISTER nicAvoidedInterrupts; | |
1163 | T3_64BIT_REGISTER nicSendThresholdHit; | |
1164 | ||
1165 | LM_UINT8 Reserved4[0xb00 - 0x9c0]; | |
c609719b WD |
1166 | } T3_STATS_BLOCK, *PT3_STATS_BLOCK; |
1167 | ||
c609719b WD |
1168 | /******************************************************************************/ |
1169 | /* PCI configuration registers. */ | |
1170 | /******************************************************************************/ | |
1171 | ||
1172 | typedef struct { | |
f539edc0 VB |
1173 | T3_16BIT_REGISTER VendorId; |
1174 | T3_16BIT_REGISTER DeviceId; | |
1175 | ||
1176 | T3_16BIT_REGISTER Command; | |
1177 | T3_16BIT_REGISTER Status; | |
1178 | ||
1179 | T3_32BIT_REGISTER ClassCodeRevId; | |
1180 | ||
1181 | T3_8BIT_REGISTER CacheLineSize; | |
1182 | T3_8BIT_REGISTER LatencyTimer; | |
1183 | T3_8BIT_REGISTER HeaderType; | |
1184 | T3_8BIT_REGISTER Bist; | |
1185 | ||
1186 | T3_32BIT_REGISTER MemBaseAddrLow; | |
1187 | T3_32BIT_REGISTER MemBaseAddrHigh; | |
1188 | ||
1189 | LM_UINT8 Unused1[20]; | |
1190 | ||
1191 | T3_16BIT_REGISTER SubsystemVendorId; | |
1192 | T3_16BIT_REGISTER SubsystemId; | |
1193 | ||
1194 | T3_32BIT_REGISTER RomBaseAddr; | |
1195 | ||
1196 | T3_8BIT_REGISTER PciXCapiblityPtr; | |
1197 | LM_UINT8 Unused2[7]; | |
1198 | ||
1199 | T3_8BIT_REGISTER IntLine; | |
1200 | T3_8BIT_REGISTER IntPin; | |
1201 | T3_8BIT_REGISTER MinGnt; | |
1202 | T3_8BIT_REGISTER MaxLat; | |
1203 | ||
1204 | T3_8BIT_REGISTER PciXCapabilities; | |
1205 | T3_8BIT_REGISTER PmCapabilityPtr; | |
1206 | T3_16BIT_REGISTER PciXCommand; | |
1207 | ||
1208 | T3_32BIT_REGISTER PciXStatus; | |
1209 | ||
1210 | T3_8BIT_REGISTER PmCapabilityId; | |
1211 | T3_8BIT_REGISTER VpdCapabilityPtr; | |
1212 | T3_16BIT_REGISTER PmCapabilities; | |
1213 | ||
1214 | T3_16BIT_REGISTER PmCtrlStatus; | |
1215 | #define PM_CTRL_PME_STATUS BIT_15 | |
1216 | #define PM_CTRL_PME_ENABLE BIT_8 | |
1217 | #define PM_CTRL_PME_POWER_STATE_D0 0 | |
1218 | #define PM_CTRL_PME_POWER_STATE_D1 1 | |
1219 | #define PM_CTRL_PME_POWER_STATE_D2 2 | |
1220 | #define PM_CTRL_PME_POWER_STATE_D3H 3 | |
1221 | ||
1222 | T3_8BIT_REGISTER BridgeSupportExt; | |
1223 | T3_8BIT_REGISTER PmData; | |
1224 | ||
1225 | T3_8BIT_REGISTER VpdCapabilityId; | |
1226 | T3_8BIT_REGISTER MsiCapabilityPtr; | |
1227 | T3_16BIT_REGISTER VpdAddrFlag; | |
1228 | #define VPD_FLAG_WRITE (1 << 15) | |
1229 | #define VPD_FLAG_RW_MASK (1 << 15) | |
1230 | #define VPD_FLAG_READ 0 | |
1231 | ||
1232 | T3_32BIT_REGISTER VpdData; | |
1233 | ||
1234 | T3_8BIT_REGISTER MsiCapabilityId; | |
1235 | T3_8BIT_REGISTER NextCapabilityPtr; | |
1236 | T3_16BIT_REGISTER MsiCtrl; | |
1237 | #define MSI_CTRL_64BIT_CAP (1 << 7) | |
1238 | #define MSI_CTRL_MSG_ENABLE(x) (x << 4) | |
1239 | #define MSI_CTRL_MSG_CAP(x) (x << 1) | |
1240 | #define MSI_CTRL_ENABLE (1 << 0) | |
1241 | ||
1242 | T3_32BIT_REGISTER MsiAddrLow; | |
1243 | T3_32BIT_REGISTER MsiAddrHigh; | |
1244 | ||
1245 | T3_16BIT_REGISTER MsiData; | |
1246 | T3_16BIT_REGISTER Unused3; | |
1247 | ||
1248 | T3_32BIT_REGISTER MiscHostCtrl; | |
1249 | #define MISC_HOST_CTRL_CLEAR_INT BIT_0 | |
1250 | #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 | |
1251 | #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 | |
1252 | #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 | |
1253 | #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 | |
1254 | #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 | |
1255 | #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 | |
1256 | #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 | |
1257 | #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 | |
1258 | #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 | |
1259 | ||
1260 | T3_32BIT_REGISTER DmaReadWriteCtrl; | |
1261 | #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) | |
1262 | #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 | |
1263 | #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 | |
1264 | #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 | |
1265 | #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) | |
1266 | #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 | |
1267 | #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) | |
1268 | #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) | |
1269 | #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) | |
1270 | #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 | |
1271 | ||
1272 | T3_32BIT_REGISTER PciState; | |
1273 | #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 | |
1274 | #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 | |
1275 | #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 | |
1276 | #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 | |
1277 | #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 | |
1278 | #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 | |
1279 | #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 | |
1280 | #define T3_PCI_STATE_FLAT_VIEW BIT_8 | |
1281 | #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 | |
1282 | ||
1283 | T3_32BIT_REGISTER ClockCtrl; | |
1284 | #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 | |
1285 | #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 | |
1286 | #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 | |
1287 | ||
1288 | T3_32BIT_REGISTER RegBaseAddr; | |
1289 | ||
1290 | T3_32BIT_REGISTER MemWindowBaseAddr; | |
c609719b WD |
1291 | |
1292 | #ifdef NIC_CPU_VIEW | |
f539edc0 VB |
1293 | /* These registers are ONLY visible to NIC CPU */ |
1294 | T3_32BIT_REGISTER PowerConsumed; | |
1295 | T3_32BIT_REGISTER PowerDissipated; | |
1296 | #else /* NIC_CPU_VIEW */ | |
1297 | T3_32BIT_REGISTER RegData; | |
1298 | T3_32BIT_REGISTER MemWindowData; | |
1299 | #endif /* !NIC_CPU_VIEW */ | |
c609719b | 1300 | |
f539edc0 | 1301 | T3_32BIT_REGISTER ModeCtrl; |
c609719b | 1302 | |
f539edc0 | 1303 | T3_32BIT_REGISTER MiscCfg; |
c609719b | 1304 | |
f539edc0 | 1305 | T3_32BIT_REGISTER MiscLocalCtrl; |
c609719b | 1306 | |
f539edc0 | 1307 | T3_32BIT_REGISTER Unused4; |
c609719b | 1308 | |
f539edc0 VB |
1309 | /* NOTE: Big/Little-endian clarification needed. Are these register */ |
1310 | /* in big or little endian formate. */ | |
1311 | T3_64BIT_REGISTER StdRingProdIdx; | |
1312 | T3_64BIT_REGISTER RcvRetRingConIdx; | |
1313 | T3_64BIT_REGISTER SndProdIdx; | |
c609719b | 1314 | |
f539edc0 | 1315 | LM_UINT8 Unused5[80]; |
c609719b WD |
1316 | } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; |
1317 | ||
1318 | #define PCIX_CMD_MAX_SPLIT_MASK 0x0070 | |
1319 | #define PCIX_CMD_MAX_SPLIT_SHL 4 | |
1320 | #define PCIX_CMD_MAX_BURST_MASK 0x000c | |
1321 | #define PCIX_CMD_MAX_BURST_SHL 2 | |
1322 | #define PCIX_CMD_MAX_BURST_CPIOB 2 | |
1323 | ||
1324 | /******************************************************************************/ | |
1325 | /* Mac control registers. */ | |
1326 | /******************************************************************************/ | |
1327 | ||
1328 | typedef struct { | |
f539edc0 VB |
1329 | /* MAC mode control. */ |
1330 | T3_32BIT_REGISTER Mode; | |
1331 | #define MAC_MODE_GLOBAL_RESET BIT_0 | |
1332 | #define MAC_MODE_HALF_DUPLEX BIT_1 | |
1333 | #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) | |
1334 | #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) | |
1335 | #define MAC_MODE_PORT_MODE_GMII BIT_3 | |
1336 | #define MAC_MODE_PORT_MODE_MII BIT_2 | |
1337 | #define MAC_MODE_PORT_MODE_NONE BIT_NONE | |
1338 | #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 | |
1339 | #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 | |
1340 | #define MAC_MODE_TX_BURSTING BIT_8 | |
1341 | #define MAC_MODE_MAX_DEFER BIT_9 | |
1342 | #define MAC_MODE_LINK_POLARITY BIT_10 | |
1343 | #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 | |
1344 | #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 | |
1345 | #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 | |
1346 | #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 | |
1347 | #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 | |
1348 | #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 | |
1349 | #define MAC_MODE_SEND_CONFIGS BIT_17 | |
1350 | #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 | |
1351 | #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 | |
1352 | #define MAC_MODE_ENABLE_MIP BIT_20 | |
1353 | #define MAC_MODE_ENABLE_TDE BIT_21 | |
1354 | #define MAC_MODE_ENABLE_RDE BIT_22 | |
1355 | #define MAC_MODE_ENABLE_FHDE BIT_23 | |
1356 | ||
1357 | /* MAC status */ | |
1358 | T3_32BIT_REGISTER Status; | |
1359 | #define MAC_STATUS_PCS_SYNCED BIT_0 | |
1360 | #define MAC_STATUS_SIGNAL_DETECTED BIT_1 | |
1361 | #define MAC_STATUS_RECEIVING_CFG BIT_2 | |
1362 | #define MAC_STATUS_CFG_CHANGED BIT_3 | |
1363 | #define MAC_STATUS_SYNC_CHANGED BIT_4 | |
1364 | #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 | |
1365 | #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 | |
1366 | #define MAC_STATUS_MI_COMPLETION BIT_22 | |
1367 | #define MAC_STATUS_MI_INTERRUPT BIT_23 | |
1368 | #define MAC_STATUS_AP_ERROR BIT_24 | |
1369 | #define MAC_STATUS_ODI_ERROR BIT_25 | |
1370 | #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 | |
1371 | #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 | |
1372 | ||
1373 | /* Event Enable */ | |
1374 | T3_32BIT_REGISTER MacEvent; | |
1375 | #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 | |
1376 | #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 | |
1377 | #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 | |
1378 | #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 | |
1379 | #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 | |
1380 | #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 | |
1381 | #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 | |
1382 | #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 | |
1383 | ||
1384 | /* Led control. */ | |
1385 | T3_32BIT_REGISTER LedCtrl; | |
1386 | #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 | |
1387 | #define LED_CTRL_1000MBPS_LED_ON BIT_1 | |
1388 | #define LED_CTRL_100MBPS_LED_ON BIT_2 | |
1389 | #define LED_CTRL_10MBPS_LED_ON BIT_3 | |
1390 | #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 | |
1391 | #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 | |
1392 | #define LED_CTRL_TRAFFIC_LED BIT_6 | |
1393 | #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 | |
1394 | #define LED_CTRL_100MBPS_LED_STATUS BIT_8 | |
1395 | #define LED_CTRL_10MBPS_LED_STATUS BIT_9 | |
1396 | #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 | |
1397 | #define LED_CTRL_MAC_MODE BIT_NONE | |
1398 | #define LED_CTRL_PHY_MODE_1 BIT_11 | |
1399 | #define LED_CTRL_PHY_MODE_2 BIT_12 | |
1400 | #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 | |
1401 | #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 | |
1402 | #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 | |
1403 | ||
1404 | /* MAC addresses. */ | |
1405 | struct { | |
1406 | T3_32BIT_REGISTER High; /* Upper 2 bytes. */ | |
1407 | T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ | |
1408 | } MacAddr[4]; | |
1409 | ||
1410 | /* ACPI Mbuf pointer. */ | |
1411 | T3_32BIT_REGISTER AcpiMbufPtr; | |
1412 | ||
1413 | /* ACPI Length and Offset. */ | |
1414 | T3_32BIT_REGISTER AcpiLengthOffset; | |
1415 | #define ACPI_LENGTH_MASK 0xffff | |
1416 | #define ACPI_OFFSET_MASK 0x0fff0000 | |
1417 | #define ACPI_LENGTH(x) x | |
1418 | #define ACPI_OFFSET(x) ((x) << 16) | |
1419 | ||
1420 | /* Transmit random backoff. */ | |
1421 | T3_32BIT_REGISTER TxBackoffSeed; | |
1422 | #define MAC_TX_BACKOFF_SEED_MASK 0x3ff | |
1423 | ||
1424 | /* Receive MTU */ | |
1425 | T3_32BIT_REGISTER MtuSize; | |
1426 | #define MAC_RX_MTU_MASK 0xffff | |
1427 | ||
1428 | /* Gigabit PCS Test. */ | |
1429 | T3_32BIT_REGISTER PcsTest; | |
1430 | #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff | |
1431 | #define MAC_PCS_TEST_ENABLE BIT_20 | |
1432 | ||
1433 | /* Transmit Gigabit Auto-Negotiation. */ | |
1434 | T3_32BIT_REGISTER TxAutoNeg; | |
1435 | #define MAC_AN_TX_AN_DATA_MASK 0xffff | |
1436 | ||
1437 | /* Receive Gigabit Auto-Negotiation. */ | |
1438 | T3_32BIT_REGISTER RxAutoNeg; | |
1439 | #define MAC_AN_RX_AN_DATA_MASK 0xffff | |
1440 | ||
1441 | /* MI Communication. */ | |
1442 | T3_32BIT_REGISTER MiCom; | |
1443 | #define MI_COM_CMD_MASK (BIT_26 | BIT_27) | |
1444 | #define MI_COM_CMD_WRITE BIT_26 | |
1445 | #define MI_COM_CMD_READ BIT_27 | |
1446 | #define MI_COM_READ_FAILED BIT_28 | |
1447 | #define MI_COM_START BIT_29 | |
1448 | #define MI_COM_BUSY BIT_29 | |
1449 | ||
1450 | #define MI_COM_PHY_ADDR_MASK 0x1f | |
1451 | #define MI_COM_FIRST_PHY_ADDR_BIT 21 | |
1452 | ||
1453 | #define MI_COM_PHY_REG_ADDR_MASK 0x1f | |
1454 | #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 | |
1455 | ||
1456 | #define MI_COM_PHY_DATA_MASK 0xffff | |
1457 | ||
1458 | /* MI Status. */ | |
1459 | T3_32BIT_REGISTER MiStatus; | |
1460 | #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 | |
1461 | ||
1462 | /* MI Mode. */ | |
1463 | T3_32BIT_REGISTER MiMode; | |
1464 | #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 | |
1465 | #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 | |
1466 | #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 | |
1467 | #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 | |
1468 | ||
1469 | /* Auto-polling status. */ | |
1470 | T3_32BIT_REGISTER AutoPollStatus; | |
1471 | #define AUTO_POLL_ERROR BIT_0 | |
1472 | ||
1473 | /* Transmit MAC mode. */ | |
1474 | T3_32BIT_REGISTER TxMode; | |
1475 | #define TX_MODE_RESET BIT_0 | |
1476 | #define TX_MODE_ENABLE BIT_1 | |
1477 | #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 | |
1478 | #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 | |
1479 | #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 | |
1480 | ||
1481 | /* Transmit MAC status. */ | |
1482 | T3_32BIT_REGISTER TxStatus; | |
1483 | #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 | |
1484 | #define TX_STATUS_SENT_XOFF BIT_1 | |
1485 | #define TX_STATUS_SENT_XON BIT_2 | |
1486 | #define TX_STATUS_LINK_UP BIT_3 | |
1487 | #define TX_STATUS_ODI_UNDERRUN BIT_4 | |
1488 | #define TX_STATUS_ODI_OVERRUN BIT_5 | |
1489 | ||
1490 | /* Transmit MAC length. */ | |
1491 | T3_32BIT_REGISTER TxLengths; | |
1492 | #define TX_LEN_SLOT_TIME_MASK 0xff | |
1493 | #define TX_LEN_IPG_MASK 0x0f00 | |
1494 | #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) | |
1495 | ||
1496 | /* Receive MAC mode. */ | |
1497 | T3_32BIT_REGISTER RxMode; | |
1498 | #define RX_MODE_RESET BIT_0 | |
1499 | #define RX_MODE_ENABLE BIT_1 | |
1500 | #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 | |
1501 | #define RX_MODE_KEEP_MAC_CONTROL BIT_3 | |
1502 | #define RX_MODE_KEEP_PAUSE BIT_4 | |
1503 | #define RX_MODE_ACCEPT_OVERSIZED BIT_5 | |
1504 | #define RX_MODE_ACCEPT_RUNTS BIT_6 | |
1505 | #define RX_MODE_LENGTH_CHECK BIT_7 | |
1506 | #define RX_MODE_PROMISCUOUS_MODE BIT_8 | |
1507 | #define RX_MODE_NO_CRC_CHECK BIT_9 | |
1508 | #define RX_MODE_KEEP_VLAN_TAG BIT_10 | |
1509 | ||
1510 | /* Receive MAC status. */ | |
1511 | T3_32BIT_REGISTER RxStatus; | |
1512 | #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 | |
1513 | #define RX_STATUS_XOFF_RECEIVED BIT_1 | |
1514 | #define RX_STATUS_XON_RECEIVED BIT_2 | |
1515 | ||
1516 | /* Hash registers. */ | |
1517 | T3_32BIT_REGISTER HashReg[4]; | |
1518 | ||
1519 | /* Receive placement rules registers. */ | |
1520 | struct { | |
1521 | T3_32BIT_REGISTER Rule; | |
1522 | T3_32BIT_REGISTER Value; | |
1523 | } RcvRules[16]; | |
1524 | ||
1525 | #define RCV_DISABLE_RULE_MASK 0x7fffffff | |
1526 | ||
1527 | #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 | |
1528 | #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 | |
1529 | #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff | |
1530 | ||
1531 | #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 | |
1532 | #define REJECT_BROADCAST_RULE2_RULE 0x86000004 | |
1533 | #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff | |
c609719b WD |
1534 | |
1535 | #if INCLUDE_5701_AX_FIX | |
f539edc0 | 1536 | #define RCV_LAST_RULE_IDX 0x04 |
c609719b | 1537 | #else |
f539edc0 | 1538 | #define RCV_LAST_RULE_IDX 0x02 |
c609719b WD |
1539 | #endif |
1540 | ||
f539edc0 VB |
1541 | T3_32BIT_REGISTER RcvRuleCfg; |
1542 | #define RX_RULE_DEFAULT_CLASS (1 << 3) | |
c609719b | 1543 | |
f539edc0 | 1544 | LM_UINT8 Reserved1[140]; |
c609719b | 1545 | |
f539edc0 VB |
1546 | T3_32BIT_REGISTER SerdesCfg; |
1547 | T3_32BIT_REGISTER SerdesStatus; | |
c609719b | 1548 | |
f539edc0 | 1549 | LM_UINT8 Reserved2[104]; |
c609719b | 1550 | |
f539edc0 VB |
1551 | volatile LM_UINT8 TxMacState[16]; |
1552 | volatile LM_UINT8 RxMacState[20]; | |
c609719b | 1553 | |
f539edc0 | 1554 | LM_UINT8 Reserved3[476]; |
c609719b | 1555 | |
f539edc0 | 1556 | T3_32BIT_REGISTER RxStats[26]; |
c609719b | 1557 | |
f539edc0 | 1558 | LM_UINT8 Reserved4[24]; |
c609719b | 1559 | |
f539edc0 | 1560 | T3_32BIT_REGISTER TxStats[28]; |
c609719b | 1561 | |
f539edc0 | 1562 | LM_UINT8 Reserved5[784]; |
c609719b WD |
1563 | } T3_MAC_CONTROL, *PT3_MAC_CONTROL; |
1564 | ||
c609719b WD |
1565 | /******************************************************************************/ |
1566 | /* Send data initiator control registers. */ | |
1567 | /******************************************************************************/ | |
1568 | ||
1569 | typedef struct { | |
f539edc0 VB |
1570 | T3_32BIT_REGISTER Mode; |
1571 | #define T3_SND_DATA_IN_MODE_RESET BIT_0 | |
1572 | #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 | |
1573 | #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 | |
1574 | ||
1575 | T3_32BIT_REGISTER Status; | |
1576 | #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 | |
1577 | ||
1578 | T3_32BIT_REGISTER StatsCtrl; | |
1579 | #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 | |
1580 | #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 | |
1581 | #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 | |
1582 | #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 | |
1583 | #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 | |
1584 | ||
1585 | T3_32BIT_REGISTER StatsEnableMask; | |
1586 | T3_32BIT_REGISTER StatsIncMask; | |
1587 | ||
1588 | LM_UINT8 Reserved[108]; | |
c609719b | 1589 | |
f539edc0 VB |
1590 | T3_32BIT_REGISTER ClassOfServCnt[16]; |
1591 | T3_32BIT_REGISTER DmaReadQFullCnt; | |
1592 | T3_32BIT_REGISTER DmaPriorityReadQFullCnt; | |
1593 | T3_32BIT_REGISTER SdcQFullCnt; | |
1594 | ||
1595 | T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; | |
1596 | T3_32BIT_REGISTER StatusUpdatedCnt; | |
1597 | T3_32BIT_REGISTER InterruptsCnt; | |
1598 | T3_32BIT_REGISTER AvoidInterruptsCnt; | |
1599 | T3_32BIT_REGISTER SendThresholdHitCnt; | |
1600 | ||
1601 | /* Unused space. */ | |
1602 | LM_UINT8 Unused[800]; | |
1603 | } T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; | |
c609719b | 1604 | |
c609719b WD |
1605 | /******************************************************************************/ |
1606 | /* Send data completion control registers. */ | |
1607 | /******************************************************************************/ | |
1608 | ||
1609 | typedef struct { | |
f539edc0 VB |
1610 | T3_32BIT_REGISTER Mode; |
1611 | #define SND_DATA_COMP_MODE_RESET BIT_0 | |
1612 | #define SND_DATA_COMP_MODE_ENABLE BIT_1 | |
c609719b | 1613 | |
f539edc0 VB |
1614 | /* Unused space. */ |
1615 | LM_UINT8 Unused[1020]; | |
c609719b WD |
1616 | } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; |
1617 | ||
c609719b WD |
1618 | /******************************************************************************/ |
1619 | /* Send BD Ring Selector Control Registers. */ | |
1620 | /******************************************************************************/ | |
1621 | ||
1622 | typedef struct { | |
f539edc0 VB |
1623 | T3_32BIT_REGISTER Mode; |
1624 | #define SND_BD_SEL_MODE_RESET BIT_0 | |
1625 | #define SND_BD_SEL_MODE_ENABLE BIT_1 | |
1626 | #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 | |
c609719b | 1627 | |
f539edc0 VB |
1628 | T3_32BIT_REGISTER Status; |
1629 | #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 | |
c609719b | 1630 | |
f539edc0 | 1631 | T3_32BIT_REGISTER HwDiag; |
c609719b | 1632 | |
f539edc0 VB |
1633 | /* Unused space. */ |
1634 | LM_UINT8 Unused1[52]; | |
c609719b | 1635 | |
f539edc0 VB |
1636 | /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ |
1637 | T3_32BIT_REGISTER NicSendBdSelConIdx[16]; | |
c609719b | 1638 | |
f539edc0 VB |
1639 | /* Unused space. */ |
1640 | LM_UINT8 Unused2[896]; | |
c609719b WD |
1641 | } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; |
1642 | ||
c609719b WD |
1643 | /******************************************************************************/ |
1644 | /* Send BD initiator control registers. */ | |
1645 | /******************************************************************************/ | |
1646 | ||
1647 | typedef struct { | |
f539edc0 VB |
1648 | T3_32BIT_REGISTER Mode; |
1649 | #define SND_BD_IN_MODE_RESET BIT_0 | |
1650 | #define SND_BD_IN_MODE_ENABLE BIT_1 | |
1651 | #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 | |
c609719b | 1652 | |
f539edc0 VB |
1653 | T3_32BIT_REGISTER Status; |
1654 | #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 | |
c609719b | 1655 | |
f539edc0 VB |
1656 | /* Send BD initiator local NIC send BD producer index. */ |
1657 | T3_32BIT_REGISTER NicSendBdInProdIdx[16]; | |
c609719b | 1658 | |
f539edc0 VB |
1659 | /* Unused space. */ |
1660 | LM_UINT8 Unused2[952]; | |
c609719b WD |
1661 | } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; |
1662 | ||
c609719b WD |
1663 | /******************************************************************************/ |
1664 | /* Send BD Completion Control. */ | |
1665 | /******************************************************************************/ | |
1666 | ||
1667 | typedef struct { | |
f539edc0 VB |
1668 | T3_32BIT_REGISTER Mode; |
1669 | #define SND_BD_COMP_MODE_RESET BIT_0 | |
1670 | #define SND_BD_COMP_MODE_ENABLE BIT_1 | |
1671 | #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 | |
c609719b | 1672 | |
f539edc0 VB |
1673 | /* Unused space. */ |
1674 | LM_UINT8 Unused2[1020]; | |
c609719b WD |
1675 | } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; |
1676 | ||
c609719b WD |
1677 | /******************************************************************************/ |
1678 | /* Receive list placement control registers. */ | |
1679 | /******************************************************************************/ | |
1680 | ||
1681 | typedef struct { | |
f539edc0 VB |
1682 | /* Mode. */ |
1683 | T3_32BIT_REGISTER Mode; | |
1684 | #define RCV_LIST_PLMT_MODE_RESET BIT_0 | |
1685 | #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 | |
1686 | #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 | |
1687 | #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 | |
1688 | #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 | |
1689 | ||
1690 | /* Status. */ | |
1691 | T3_32BIT_REGISTER Status; | |
1692 | #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 | |
1693 | #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 | |
1694 | #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 | |
1695 | ||
1696 | /* Receive selector list lock register. */ | |
1697 | T3_32BIT_REGISTER Lock; | |
1698 | #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff | |
1699 | #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 | |
1700 | ||
1701 | /* Selector non-empty bits. */ | |
1702 | T3_32BIT_REGISTER NonEmptyBits; | |
1703 | #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff | |
1704 | ||
1705 | /* Receive list placement configuration register. */ | |
1706 | T3_32BIT_REGISTER Config; | |
1707 | ||
1708 | /* Receive List Placement statistics Control. */ | |
1709 | T3_32BIT_REGISTER StatsCtrl; | |
c609719b WD |
1710 | #define RCV_LIST_STATS_ENABLE BIT_0 |
1711 | #define RCV_LIST_STATS_FAST_UPDATE BIT_1 | |
1712 | ||
f539edc0 VB |
1713 | /* Receive List Placement statistics Enable Mask. */ |
1714 | T3_32BIT_REGISTER StatsEnableMask; | |
c609719b | 1715 | |
f539edc0 VB |
1716 | /* Receive List Placement statistics Increment Mask. */ |
1717 | T3_32BIT_REGISTER StatsIncMask; | |
c609719b | 1718 | |
8bde7f77 | 1719 | /* Unused space. */ |
f539edc0 | 1720 | LM_UINT8 Unused1[224]; |
c609719b | 1721 | |
f539edc0 VB |
1722 | struct { |
1723 | T3_32BIT_REGISTER Head; | |
1724 | T3_32BIT_REGISTER Tail; | |
1725 | T3_32BIT_REGISTER Count; | |
1726 | ||
1727 | /* Unused space. */ | |
1728 | LM_UINT8 Unused[4]; | |
1729 | } RcvSelectorList[16]; | |
1730 | ||
1731 | /* Local statistics counter. */ | |
1732 | T3_32BIT_REGISTER ClassOfServCnt[16]; | |
1733 | ||
1734 | T3_32BIT_REGISTER DropDueToFilterCnt; | |
1735 | T3_32BIT_REGISTER DmaWriteQFullCnt; | |
1736 | T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; | |
1737 | T3_32BIT_REGISTER NoMoreReceiveBdCnt; | |
1738 | T3_32BIT_REGISTER IfInDiscardsCnt; | |
1739 | T3_32BIT_REGISTER IfInErrorsCnt; | |
1740 | T3_32BIT_REGISTER RcvThresholdHitCnt; | |
1741 | ||
1742 | /* Another unused space. */ | |
1743 | LM_UINT8 Unused2[420]; | |
1744 | } T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; | |
c609719b | 1745 | |
c609719b WD |
1746 | /******************************************************************************/ |
1747 | /* Receive Data and Receive BD Initiator Control. */ | |
1748 | /******************************************************************************/ | |
1749 | ||
1750 | typedef struct { | |
f539edc0 VB |
1751 | /* Mode. */ |
1752 | T3_32BIT_REGISTER Mode; | |
1753 | #define RCV_DATA_BD_IN_MODE_RESET BIT_0 | |
1754 | #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 | |
1755 | #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 | |
1756 | #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 | |
1757 | #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 | |
1758 | ||
1759 | /* Status. */ | |
1760 | T3_32BIT_REGISTER Status; | |
1761 | #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 | |
1762 | #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 | |
1763 | #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 | |
1764 | ||
1765 | /* Split frame minium size. */ | |
1766 | T3_32BIT_REGISTER SplitFrameMinSize; | |
1767 | ||
1768 | /* Unused space. */ | |
1769 | LM_UINT8 Unused1[0x2440 - 0x240c]; | |
1770 | ||
1771 | /* Receive RCBs. */ | |
1772 | T3_RCB JumboRcvRcb; | |
1773 | T3_RCB StdRcvRcb; | |
1774 | T3_RCB MiniRcvRcb; | |
1775 | ||
1776 | /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ | |
1777 | /* BD Consumber Index. */ | |
1778 | T3_32BIT_REGISTER NicJumboConIdx; | |
1779 | T3_32BIT_REGISTER NicStdConIdx; | |
1780 | T3_32BIT_REGISTER NicMiniConIdx; | |
1781 | ||
1782 | /* Unused space. */ | |
1783 | LM_UINT8 Unused2[4]; | |
1784 | ||
1785 | /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ | |
1786 | T3_32BIT_REGISTER RcvDataBdProdIdx[16]; | |
c609719b | 1787 | |
f539edc0 VB |
1788 | /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ |
1789 | T3_32BIT_REGISTER HwDiag; | |
1790 | ||
1791 | /* Unused space. */ | |
1792 | LM_UINT8 Unused3[828]; | |
1793 | } T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; | |
c609719b | 1794 | |
c609719b WD |
1795 | /******************************************************************************/ |
1796 | /* Receive Data Completion Control Registes. */ | |
1797 | /******************************************************************************/ | |
1798 | ||
1799 | typedef struct { | |
f539edc0 VB |
1800 | T3_32BIT_REGISTER Mode; |
1801 | #define RCV_DATA_COMP_MODE_RESET BIT_0 | |
1802 | #define RCV_DATA_COMP_MODE_ENABLE BIT_1 | |
1803 | #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 | |
c609719b | 1804 | |
f539edc0 VB |
1805 | /* Unused spaced. */ |
1806 | LM_UINT8 Unused[1020]; | |
c609719b WD |
1807 | } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; |
1808 | ||
c609719b WD |
1809 | /******************************************************************************/ |
1810 | /* Receive BD Initiator Control. */ | |
1811 | /******************************************************************************/ | |
1812 | ||
1813 | typedef struct { | |
f539edc0 VB |
1814 | T3_32BIT_REGISTER Mode; |
1815 | #define RCV_BD_IN_MODE_RESET BIT_0 | |
1816 | #define RCV_BD_IN_MODE_ENABLE BIT_1 | |
1817 | #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 | |
c609719b | 1818 | |
f539edc0 VB |
1819 | T3_32BIT_REGISTER Status; |
1820 | #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 | |
c609719b | 1821 | |
f539edc0 VB |
1822 | T3_32BIT_REGISTER NicJumboRcvProdIdx; |
1823 | T3_32BIT_REGISTER NicStdRcvProdIdx; | |
1824 | T3_32BIT_REGISTER NicMiniRcvProdIdx; | |
c609719b | 1825 | |
f539edc0 VB |
1826 | T3_32BIT_REGISTER MiniRcvThreshold; |
1827 | T3_32BIT_REGISTER StdRcvThreshold; | |
1828 | T3_32BIT_REGISTER JumboRcvThreshold; | |
c609719b | 1829 | |
f539edc0 VB |
1830 | /* Unused space. */ |
1831 | LM_UINT8 Unused[992]; | |
c609719b WD |
1832 | } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; |
1833 | ||
c609719b WD |
1834 | /******************************************************************************/ |
1835 | /* Receive BD Completion Control Registers. */ | |
1836 | /******************************************************************************/ | |
1837 | ||
1838 | typedef struct { | |
f539edc0 VB |
1839 | T3_32BIT_REGISTER Mode; |
1840 | #define RCV_BD_COMP_MODE_RESET BIT_0 | |
1841 | #define RCV_BD_COMP_MODE_ENABLE BIT_1 | |
1842 | #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 | |
c609719b | 1843 | |
f539edc0 VB |
1844 | T3_32BIT_REGISTER Status; |
1845 | #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 | |
c609719b | 1846 | |
f539edc0 VB |
1847 | T3_32BIT_REGISTER NicJumboRcvBdProdIdx; |
1848 | T3_32BIT_REGISTER NicStdRcvBdProdIdx; | |
1849 | T3_32BIT_REGISTER NicMiniRcvBdProdIdx; | |
c609719b | 1850 | |
f539edc0 VB |
1851 | /* Unused space. */ |
1852 | LM_UINT8 Unused[1004]; | |
c609719b WD |
1853 | } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; |
1854 | ||
c609719b WD |
1855 | /******************************************************************************/ |
1856 | /* Receive list selector control register. */ | |
1857 | /******************************************************************************/ | |
1858 | ||
1859 | typedef struct { | |
f539edc0 VB |
1860 | T3_32BIT_REGISTER Mode; |
1861 | #define RCV_LIST_SEL_MODE_RESET BIT_0 | |
1862 | #define RCV_LIST_SEL_MODE_ENABLE BIT_1 | |
1863 | #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 | |
c609719b | 1864 | |
f539edc0 VB |
1865 | T3_32BIT_REGISTER Status; |
1866 | #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 | |
c609719b | 1867 | |
f539edc0 VB |
1868 | /* Unused space. */ |
1869 | LM_UINT8 Unused[1016]; | |
c609719b WD |
1870 | } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; |
1871 | ||
c609719b WD |
1872 | /******************************************************************************/ |
1873 | /* Mbuf cluster free registers. */ | |
1874 | /******************************************************************************/ | |
1875 | ||
1876 | typedef struct { | |
f539edc0 | 1877 | T3_32BIT_REGISTER Mode; |
c609719b WD |
1878 | #define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 |
1879 | #define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 | |
1880 | ||
f539edc0 | 1881 | T3_32BIT_REGISTER Status; |
c609719b | 1882 | |
f539edc0 VB |
1883 | /* Unused space. */ |
1884 | LM_UINT8 Unused[1016]; | |
c609719b WD |
1885 | } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; |
1886 | ||
c609719b WD |
1887 | /******************************************************************************/ |
1888 | /* Host coalescing control registers. */ | |
1889 | /******************************************************************************/ | |
1890 | ||
1891 | typedef struct { | |
f539edc0 VB |
1892 | /* Mode. */ |
1893 | T3_32BIT_REGISTER Mode; | |
1894 | #define HOST_COALESCE_RESET BIT_0 | |
1895 | #define HOST_COALESCE_ENABLE BIT_1 | |
1896 | #define HOST_COALESCE_ATTN BIT_2 | |
1897 | #define HOST_COALESCE_NOW BIT_3 | |
1898 | #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE | |
1899 | #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 | |
1900 | #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 | |
1901 | #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 | |
1902 | #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 | |
1903 | #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 | |
1904 | #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 | |
c609719b | 1905 | |
f539edc0 VB |
1906 | /* Status. */ |
1907 | T3_32BIT_REGISTER Status; | |
1908 | #define HOST_COALESCE_ERROR_ATTN BIT_2 | |
c609719b | 1909 | |
f539edc0 VB |
1910 | /* Receive coalescing ticks. */ |
1911 | T3_32BIT_REGISTER RxCoalescingTicks; | |
c609719b | 1912 | |
f539edc0 VB |
1913 | /* Send coalescing ticks. */ |
1914 | T3_32BIT_REGISTER TxCoalescingTicks; | |
c609719b | 1915 | |
f539edc0 VB |
1916 | /* Receive max coalesced frames. */ |
1917 | T3_32BIT_REGISTER RxMaxCoalescedFrames; | |
c609719b | 1918 | |
f539edc0 VB |
1919 | /* Send max coalesced frames. */ |
1920 | T3_32BIT_REGISTER TxMaxCoalescedFrames; | |
c609719b | 1921 | |
f539edc0 VB |
1922 | /* Receive coalescing ticks during interrupt. */ |
1923 | T3_32BIT_REGISTER RxCoalescedTickDuringInt; | |
c609719b | 1924 | |
f539edc0 VB |
1925 | /* Send coalescing ticks during interrupt. */ |
1926 | T3_32BIT_REGISTER TxCoalescedTickDuringInt; | |
c609719b | 1927 | |
f539edc0 VB |
1928 | /* Receive max coalesced frames during interrupt. */ |
1929 | T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; | |
c609719b | 1930 | |
f539edc0 VB |
1931 | /* Send max coalesced frames during interrupt. */ |
1932 | T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; | |
c609719b | 1933 | |
f539edc0 VB |
1934 | /* Statistics tick. */ |
1935 | T3_32BIT_REGISTER StatsCoalescingTicks; | |
c609719b | 1936 | |
f539edc0 VB |
1937 | /* Unused space. */ |
1938 | LM_UINT8 Unused2[4]; | |
c609719b | 1939 | |
f539edc0 VB |
1940 | /* Statistics host address. */ |
1941 | T3_64BIT_REGISTER StatsBlkHostAddr; | |
c609719b | 1942 | |
f539edc0 VB |
1943 | /* Status block host address. */ |
1944 | T3_64BIT_REGISTER StatusBlkHostAddr; | |
c609719b | 1945 | |
f539edc0 VB |
1946 | /* Statistics NIC address. */ |
1947 | T3_32BIT_REGISTER StatsBlkNicAddr; | |
c609719b | 1948 | |
f539edc0 VB |
1949 | /* Statust block NIC address. */ |
1950 | T3_32BIT_REGISTER StatusBlkNicAddr; | |
c609719b | 1951 | |
f539edc0 VB |
1952 | /* Flow attention registers. */ |
1953 | T3_32BIT_REGISTER FlowAttn; | |
c609719b | 1954 | |
f539edc0 VB |
1955 | /* Unused space. */ |
1956 | LM_UINT8 Unused3[4]; | |
c609719b | 1957 | |
f539edc0 VB |
1958 | T3_32BIT_REGISTER NicJumboRcvBdConIdx; |
1959 | T3_32BIT_REGISTER NicStdRcvBdConIdx; | |
1960 | T3_32BIT_REGISTER NicMiniRcvBdConIdx; | |
c609719b | 1961 | |
f539edc0 VB |
1962 | /* Unused space. */ |
1963 | LM_UINT8 Unused4[36]; | |
c609719b | 1964 | |
f539edc0 VB |
1965 | T3_32BIT_REGISTER NicRetProdIdx[16]; |
1966 | T3_32BIT_REGISTER NicSndBdConIdx[16]; | |
c609719b | 1967 | |
f539edc0 VB |
1968 | /* Unused space. */ |
1969 | LM_UINT8 Unused5[768]; | |
c609719b WD |
1970 | } T3_HOST_COALESCING, *PT3_HOST_COALESCING; |
1971 | ||
c609719b WD |
1972 | /******************************************************************************/ |
1973 | /* Memory arbiter registers. */ | |
1974 | /******************************************************************************/ | |
1975 | ||
1976 | typedef struct { | |
f539edc0 | 1977 | T3_32BIT_REGISTER Mode; |
c609719b WD |
1978 | #define T3_MEM_ARBITER_MODE_RESET BIT_0 |
1979 | #define T3_MEM_ARBITER_MODE_ENABLE BIT_1 | |
1980 | ||
f539edc0 | 1981 | T3_32BIT_REGISTER Status; |
c609719b | 1982 | |
f539edc0 VB |
1983 | T3_32BIT_REGISTER ArbTrapAddrLow; |
1984 | T3_32BIT_REGISTER ArbTrapAddrHigh; | |
c609719b | 1985 | |
f539edc0 VB |
1986 | /* Unused space. */ |
1987 | LM_UINT8 Unused[1008]; | |
c609719b WD |
1988 | } T3_MEM_ARBITER, *PT3_MEM_ARBITER; |
1989 | ||
c609719b WD |
1990 | /******************************************************************************/ |
1991 | /* Buffer manager control register. */ | |
1992 | /******************************************************************************/ | |
1993 | ||
1994 | typedef struct { | |
f539edc0 VB |
1995 | T3_32BIT_REGISTER Mode; |
1996 | #define BUFMGR_MODE_RESET BIT_0 | |
1997 | #define BUFMGR_MODE_ENABLE BIT_1 | |
1998 | #define BUFMGR_MODE_ATTN_ENABLE BIT_2 | |
1999 | #define BUFMGR_MODE_BM_TEST BIT_3 | |
2000 | #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 | |
2001 | ||
2002 | T3_32BIT_REGISTER Status; | |
2003 | #define BUFMGR_STATUS_ERROR BIT_2 | |
2004 | #define BUFMGR_STATUS_MBUF_LOW BIT_4 | |
2005 | ||
2006 | T3_32BIT_REGISTER MbufPoolAddr; | |
2007 | T3_32BIT_REGISTER MbufPoolSize; | |
2008 | T3_32BIT_REGISTER MbufReadDmaLowWaterMark; | |
2009 | T3_32BIT_REGISTER MbufMacRxLowWaterMark; | |
2010 | T3_32BIT_REGISTER MbufHighWaterMark; | |
2011 | ||
2012 | T3_32BIT_REGISTER RxCpuMbufAllocReq; | |
2013 | #define BUFMGR_MBUF_ALLOC_BIT BIT_31 | |
2014 | T3_32BIT_REGISTER RxCpuMbufAllocResp; | |
2015 | T3_32BIT_REGISTER TxCpuMbufAllocReq; | |
2016 | T3_32BIT_REGISTER TxCpuMbufAllocResp; | |
2017 | ||
2018 | T3_32BIT_REGISTER DmaDescPoolAddr; | |
2019 | T3_32BIT_REGISTER DmaDescPoolSize; | |
2020 | T3_32BIT_REGISTER DmaLowWaterMark; | |
2021 | T3_32BIT_REGISTER DmaHighWaterMark; | |
2022 | ||
2023 | T3_32BIT_REGISTER RxCpuDmaAllocReq; | |
2024 | T3_32BIT_REGISTER RxCpuDmaAllocResp; | |
2025 | T3_32BIT_REGISTER TxCpuDmaAllocReq; | |
2026 | T3_32BIT_REGISTER TxCpuDmaAllocResp; | |
2027 | ||
2028 | T3_32BIT_REGISTER Hwdiag[3]; | |
c609719b | 2029 | |
f539edc0 VB |
2030 | /* Unused space. */ |
2031 | LM_UINT8 Unused[936]; | |
2032 | } T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; | |
c609719b | 2033 | |
c609719b WD |
2034 | /******************************************************************************/ |
2035 | /* Read DMA control registers. */ | |
2036 | /******************************************************************************/ | |
2037 | ||
2038 | typedef struct { | |
f539edc0 VB |
2039 | T3_32BIT_REGISTER Mode; |
2040 | #define DMA_READ_MODE_RESET BIT_0 | |
2041 | #define DMA_READ_MODE_ENABLE BIT_1 | |
2042 | #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 | |
2043 | #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 | |
2044 | #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 | |
2045 | #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 | |
2046 | #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 | |
2047 | #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 | |
2048 | #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 | |
2049 | #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 | |
2050 | #define DMA_READ_MODE_SPLIT_ENABLE BIT_11 | |
2051 | #define DMA_READ_MODE_SPLIT_RESET BIT_12 | |
2052 | ||
2053 | T3_32BIT_REGISTER Status; | |
2054 | #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 | |
2055 | #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 | |
2056 | #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 | |
2057 | #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 | |
2058 | #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 | |
2059 | #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 | |
2060 | #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 | |
2061 | #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 | |
2062 | ||
2063 | /* Unused space. */ | |
2064 | LM_UINT8 Unused[1016]; | |
c609719b WD |
2065 | } T3_DMA_READ, *PT3_DMA_READ; |
2066 | ||
f539edc0 VB |
2067 | typedef union T3_CPU { |
2068 | struct { | |
2069 | T3_32BIT_REGISTER mode; | |
2070 | #define CPU_MODE_HALT BIT_10 | |
2071 | #define CPU_MODE_RESET BIT_0 | |
2072 | T3_32BIT_REGISTER state; | |
2073 | T3_32BIT_REGISTER EventMask; | |
2074 | T3_32BIT_REGISTER reserved1[4]; | |
2075 | T3_32BIT_REGISTER PC; | |
2076 | T3_32BIT_REGISTER Instruction; | |
2077 | T3_32BIT_REGISTER SpadUnderflow; | |
2078 | T3_32BIT_REGISTER WatchdogClear; | |
2079 | T3_32BIT_REGISTER WatchdogVector; | |
2080 | T3_32BIT_REGISTER WatchdogSavedPC; | |
2081 | T3_32BIT_REGISTER HardwareBp; | |
2082 | T3_32BIT_REGISTER reserved2[3]; | |
2083 | T3_32BIT_REGISTER WatchdogSavedState; | |
2084 | T3_32BIT_REGISTER LastBrchAddr; | |
2085 | T3_32BIT_REGISTER SpadUnderflowSet; | |
2086 | T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4]; | |
2087 | T3_32BIT_REGISTER Regs[32]; | |
2088 | T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4]; | |
2089 | } reg; | |
2090 | } T3_CPU, *PT3_CPU; | |
c609719b WD |
2091 | |
2092 | /******************************************************************************/ | |
2093 | /* Write DMA control registers. */ | |
2094 | /******************************************************************************/ | |
2095 | ||
2096 | typedef struct { | |
f539edc0 VB |
2097 | T3_32BIT_REGISTER Mode; |
2098 | #define DMA_WRITE_MODE_RESET BIT_0 | |
2099 | #define DMA_WRITE_MODE_ENABLE BIT_1 | |
2100 | #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 | |
2101 | #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 | |
2102 | #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 | |
2103 | #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 | |
2104 | #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 | |
2105 | #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 | |
2106 | #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 | |
2107 | #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 | |
2108 | ||
2109 | T3_32BIT_REGISTER Status; | |
2110 | #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 | |
2111 | #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 | |
2112 | #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 | |
2113 | #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 | |
2114 | #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 | |
2115 | #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 | |
2116 | #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 | |
2117 | #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 | |
c609719b | 2118 | |
f539edc0 VB |
2119 | /* Unused space. */ |
2120 | LM_UINT8 Unused[1016]; | |
2121 | } T3_DMA_WRITE, *PT3_DMA_WRITE; | |
c609719b | 2122 | |
c609719b WD |
2123 | /******************************************************************************/ |
2124 | /* Mailbox registers. */ | |
2125 | /******************************************************************************/ | |
2126 | ||
2127 | typedef struct { | |
f539edc0 VB |
2128 | /* Interrupt mailbox registers. */ |
2129 | T3_64BIT_REGISTER Interrupt[4]; | |
c609719b | 2130 | |
f539edc0 VB |
2131 | /* General mailbox registers. */ |
2132 | T3_64BIT_REGISTER General[8]; | |
c609719b | 2133 | |
f539edc0 VB |
2134 | /* Reload statistics mailbox. */ |
2135 | T3_64BIT_REGISTER ReloadStat; | |
c609719b | 2136 | |
f539edc0 VB |
2137 | /* Receive BD ring producer index registers. */ |
2138 | T3_64BIT_REGISTER RcvStdProdIdx; | |
2139 | T3_64BIT_REGISTER RcvJumboProdIdx; | |
2140 | T3_64BIT_REGISTER RcvMiniProdIdx; | |
c609719b | 2141 | |
f539edc0 VB |
2142 | /* Receive return ring consumer index registers. */ |
2143 | T3_64BIT_REGISTER RcvRetConIdx[16]; | |
c609719b | 2144 | |
f539edc0 VB |
2145 | /* Send BD ring host producer index registers. */ |
2146 | T3_64BIT_REGISTER SendHostProdIdx[16]; | |
c609719b | 2147 | |
f539edc0 VB |
2148 | /* Send BD ring nic producer index registers. */ |
2149 | T3_64BIT_REGISTER SendNicProdIdx[16]; | |
2150 | } T3_MAILBOX, *PT3_MAILBOX; | |
c609719b WD |
2151 | |
2152 | typedef struct { | |
f539edc0 | 2153 | T3_MAILBOX Mailbox; |
c609719b | 2154 | |
f539edc0 VB |
2155 | /* Priority mailbox registers. */ |
2156 | T3_32BIT_REGISTER HighPriorityEventVector; | |
2157 | T3_32BIT_REGISTER HighPriorityEventMask; | |
2158 | T3_32BIT_REGISTER LowPriorityEventVector; | |
2159 | T3_32BIT_REGISTER LowPriorityEventMask; | |
c609719b | 2160 | |
f539edc0 VB |
2161 | /* Unused space. */ |
2162 | LM_UINT8 Unused[496]; | |
c609719b WD |
2163 | } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; |
2164 | ||
c609719b WD |
2165 | /******************************************************************************/ |
2166 | /* Flow through queues. */ | |
2167 | /******************************************************************************/ | |
2168 | ||
2169 | typedef struct { | |
f539edc0 VB |
2170 | T3_32BIT_REGISTER Reset; |
2171 | ||
2172 | LM_UINT8 Unused[12]; | |
2173 | ||
2174 | T3_32BIT_REGISTER DmaNormalReadFtqCtrl; | |
2175 | T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; | |
2176 | T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; | |
2177 | T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; | |
2178 | ||
2179 | T3_32BIT_REGISTER DmaHighReadFtqCtrl; | |
2180 | T3_32BIT_REGISTER DmaHighReadFtqFullCnt; | |
2181 | T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; | |
2182 | T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; | |
2183 | ||
2184 | T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; | |
2185 | T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; | |
2186 | T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; | |
2187 | T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; | |
2188 | ||
2189 | T3_32BIT_REGISTER SendBdCompFtqCtrl; | |
2190 | T3_32BIT_REGISTER SendBdCompFtqFullCnt; | |
2191 | T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; | |
2192 | T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; | |
2193 | ||
2194 | T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; | |
2195 | T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; | |
2196 | T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; | |
2197 | T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; | |
2198 | ||
2199 | T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; | |
2200 | T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; | |
2201 | T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; | |
2202 | T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; | |
2203 | ||
2204 | T3_32BIT_REGISTER DmaHighWriteFtqCtrl; | |
2205 | T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; | |
2206 | T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; | |
2207 | T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; | |
2208 | ||
2209 | T3_32BIT_REGISTER SwType1FtqCtrl; | |
2210 | T3_32BIT_REGISTER SwType1FtqFullCnt; | |
2211 | T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; | |
2212 | T3_32BIT_REGISTER SwType1FtqFifoWritePeek; | |
2213 | ||
2214 | T3_32BIT_REGISTER SendDataCompFtqCtrl; | |
2215 | T3_32BIT_REGISTER SendDataCompFtqFullCnt; | |
2216 | T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; | |
2217 | T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; | |
2218 | ||
2219 | T3_32BIT_REGISTER HostCoalesceFtqCtrl; | |
2220 | T3_32BIT_REGISTER HostCoalesceFtqFullCnt; | |
2221 | T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; | |
2222 | T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; | |
2223 | ||
2224 | T3_32BIT_REGISTER MacTxFtqCtrl; | |
2225 | T3_32BIT_REGISTER MacTxFtqFullCnt; | |
2226 | T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; | |
2227 | T3_32BIT_REGISTER MacTxFtqFifoWritePeek; | |
2228 | ||
2229 | T3_32BIT_REGISTER MbufClustFreeFtqCtrl; | |
2230 | T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; | |
2231 | T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; | |
2232 | T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; | |
2233 | ||
2234 | T3_32BIT_REGISTER RcvBdCompFtqCtrl; | |
2235 | T3_32BIT_REGISTER RcvBdCompFtqFullCnt; | |
2236 | T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; | |
2237 | T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; | |
2238 | ||
2239 | T3_32BIT_REGISTER RcvListPlmtFtqCtrl; | |
2240 | T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; | |
2241 | T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; | |
2242 | T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; | |
2243 | ||
2244 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; | |
2245 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; | |
2246 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; | |
2247 | T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; | |
2248 | ||
2249 | T3_32BIT_REGISTER RcvDataCompFtqCtrl; | |
2250 | T3_32BIT_REGISTER RcvDataCompFtqFullCnt; | |
2251 | T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; | |
2252 | T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; | |
2253 | ||
2254 | T3_32BIT_REGISTER SwType2FtqCtrl; | |
2255 | T3_32BIT_REGISTER SwType2FtqFullCnt; | |
2256 | T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; | |
2257 | T3_32BIT_REGISTER SwType2FtqFifoWritePeek; | |
c609719b | 2258 | |
f539edc0 VB |
2259 | /* Unused space. */ |
2260 | LM_UINT8 Unused2[736]; | |
2261 | } T3_FTQ, *PT3_FTQ; | |
c609719b | 2262 | |
c609719b WD |
2263 | /******************************************************************************/ |
2264 | /* Message signaled interrupt registers. */ | |
2265 | /******************************************************************************/ | |
2266 | ||
2267 | typedef struct { | |
f539edc0 | 2268 | T3_32BIT_REGISTER Mode; |
c609719b WD |
2269 | #define MSI_MODE_RESET BIT_0 |
2270 | #define MSI_MODE_ENABLE BIT_1 | |
f539edc0 | 2271 | T3_32BIT_REGISTER Status; |
c609719b | 2272 | |
f539edc0 | 2273 | T3_32BIT_REGISTER MsiFifoAccess; |
c609719b | 2274 | |
f539edc0 VB |
2275 | /* Unused space. */ |
2276 | LM_UINT8 Unused[1012]; | |
c609719b WD |
2277 | } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; |
2278 | ||
c609719b WD |
2279 | /******************************************************************************/ |
2280 | /* DMA Completion registes. */ | |
2281 | /******************************************************************************/ | |
2282 | ||
2283 | typedef struct { | |
f539edc0 VB |
2284 | T3_32BIT_REGISTER Mode; |
2285 | #define DMA_COMP_MODE_RESET BIT_0 | |
2286 | #define DMA_COMP_MODE_ENABLE BIT_1 | |
c609719b | 2287 | |
f539edc0 VB |
2288 | /* Unused space. */ |
2289 | LM_UINT8 Unused[1020]; | |
c609719b WD |
2290 | } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; |
2291 | ||
c609719b WD |
2292 | /******************************************************************************/ |
2293 | /* GRC registers. */ | |
2294 | /******************************************************************************/ | |
2295 | ||
2296 | typedef struct { | |
f539edc0 VB |
2297 | /* Mode control register. */ |
2298 | T3_32BIT_REGISTER Mode; | |
2299 | #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 | |
2300 | #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 | |
2301 | #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 | |
2302 | #define GRC_MODE_BYTE_SWAP_DATA BIT_4 | |
2303 | #define GRC_MODE_WORD_SWAP_DATA BIT_5 | |
2304 | #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 | |
2305 | #define GRC_MODE_NO_FRAME_CRACKING BIT_9 | |
2306 | #define GRC_MODE_INCLUDE_CRC BIT_10 | |
2307 | #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 | |
2308 | #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 | |
2309 | #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 | |
2310 | #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 | |
2311 | #define GRC_MODE_HOST_STACK_UP BIT_16 | |
2312 | #define GRC_MODE_HOST_SEND_BDS BIT_17 | |
2313 | #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 | |
2314 | #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 | |
2315 | #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 | |
2316 | #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 | |
2317 | #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 | |
2318 | #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 | |
2319 | #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 | |
2320 | #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 | |
2321 | #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 | |
2322 | ||
2323 | /* Misc configuration register. */ | |
2324 | T3_32BIT_REGISTER MiscCfg; | |
2325 | #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 | |
2326 | #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe | |
2327 | #define GRC_MISC_BD_ID_MASK 0x0001e000 | |
2328 | #define GRC_MISC_BD_ID_5700 0x0001e000 | |
2329 | #define GRC_MISC_BD_ID_5701 0x00000000 | |
2330 | #define GRC_MISC_BD_ID_5703 0x00000000 | |
2331 | #define GRC_MISC_BD_ID_5703S 0x00002000 | |
2332 | #define GRC_MISC_BD_ID_5702FE 0x00004000 | |
2333 | #define GRC_MISC_BD_ID_5704 0x00000000 | |
2334 | #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 | |
2335 | ||
2336 | /* Miscellaneous local control register. */ | |
2337 | T3_32BIT_REGISTER LocalCtrl; | |
2338 | #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 | |
2339 | #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 | |
2340 | #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 | |
2341 | #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 | |
2342 | #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 | |
2343 | #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 | |
2344 | #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 | |
2345 | #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 | |
2346 | #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 | |
2347 | #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 | |
2348 | #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 | |
2349 | #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 | |
2350 | #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 | |
2351 | #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 | |
2352 | #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 | |
2353 | #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 | |
2354 | ||
2355 | #define GRC_MISC_MEMSIZE_256K 0 | |
2356 | #define GRC_MISC_MEMSIZE_512K (1 << 18) | |
2357 | #define GRC_MISC_MEMSIZE_1024K (2 << 18) | |
2358 | #define GRC_MISC_MEMSIZE_2048K (3 << 18) | |
2359 | #define GRC_MISC_MEMSIZE_4096K (4 << 18) | |
2360 | #define GRC_MISC_MEMSIZE_8192K (5 << 18) | |
2361 | #define GRC_MISC_MEMSIZE_16M (6 << 18) | |
2362 | #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 | |
2363 | ||
2364 | T3_32BIT_REGISTER Timer; | |
2365 | ||
2366 | T3_32BIT_REGISTER RxCpuEvent; | |
2367 | T3_32BIT_REGISTER RxTimerRef; | |
2368 | T3_32BIT_REGISTER RxCpuSemaphore; | |
2369 | T3_32BIT_REGISTER RemoteRxCpuAttn; | |
2370 | ||
2371 | T3_32BIT_REGISTER TxCpuEvent; | |
2372 | T3_32BIT_REGISTER TxTimerRef; | |
2373 | T3_32BIT_REGISTER TxCpuSemaphore; | |
2374 | T3_32BIT_REGISTER RemoteTxCpuAttn; | |
2375 | ||
2376 | T3_64BIT_REGISTER MemoryPowerUp; | |
2377 | ||
2378 | T3_32BIT_REGISTER EepromAddr; | |
2379 | #define SEEPROM_ADDR_WRITE 0 | |
2380 | #define SEEPROM_ADDR_READ (1 << 31) | |
2381 | #define SEEPROM_ADDR_RW_MASK 0x80000000 | |
2382 | #define SEEPROM_ADDR_COMPLETE (1 << 30) | |
2383 | #define SEEPROM_ADDR_FSM_RESET (1 << 29) | |
2384 | #define SEEPROM_ADDR_DEV_ID(x) (x << 26) | |
2385 | #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 | |
2386 | #define SEEPROM_ADDR_START (1 << 25) | |
2387 | #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) | |
2388 | #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) | |
2389 | #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff | |
2390 | ||
2391 | #define SEEPROM_CLOCK_PERIOD 60 | |
2392 | #define SEEPROM_CHIP_SIZE (64 * 1024) | |
2393 | ||
2394 | T3_32BIT_REGISTER EepromData; | |
2395 | T3_32BIT_REGISTER EepromCtrl; | |
2396 | ||
2397 | T3_32BIT_REGISTER MdiCtrl; | |
2398 | T3_32BIT_REGISTER SepromDelay; | |
c609719b | 2399 | |
f539edc0 VB |
2400 | /* Unused space. */ |
2401 | LM_UINT8 Unused[948]; | |
2402 | } T3_GRC, *PT3_GRC; | |
c609719b WD |
2403 | |
2404 | /******************************************************************************/ | |
2405 | /* NVRAM control registers. */ | |
2406 | /******************************************************************************/ | |
2407 | ||
f539edc0 VB |
2408 | typedef struct { |
2409 | T3_32BIT_REGISTER Cmd; | |
2410 | #define NVRAM_CMD_RESET BIT_0 | |
2411 | #define NVRAM_CMD_DONE BIT_3 | |
2412 | #define NVRAM_CMD_DO_IT BIT_4 | |
2413 | #define NVRAM_CMD_WR BIT_5 | |
2414 | #define NVRAM_CMD_RD BIT_NONE | |
2415 | #define NVRAM_CMD_ERASE BIT_6 | |
2416 | #define NVRAM_CMD_FIRST BIT_7 | |
2417 | #define NVRAM_CMD_LAST BIT_8 | |
2418 | ||
2419 | T3_32BIT_REGISTER Status; | |
2420 | T3_32BIT_REGISTER WriteData; | |
2421 | ||
2422 | T3_32BIT_REGISTER Addr; | |
2423 | #define NVRAM_ADDRESS_MASK 0xffffff | |
2424 | ||
2425 | T3_32BIT_REGISTER ReadData; | |
2426 | ||
2427 | /* Flash config 1 register. */ | |
2428 | T3_32BIT_REGISTER Config1; | |
2429 | #define FLASH_INTERFACE_ENABLE BIT_0 | |
2430 | #define FLASH_SSRAM_BUFFERRED_MODE BIT_1 | |
2431 | #define FLASH_PASS_THRU_MODE BIT_2 | |
2432 | #define FLASH_BIT_BANG_MODE BIT_3 | |
2433 | #define FLASH_COMPAT_BYPASS BIT_31 | |
2434 | ||
2435 | /* Buffered flash (Atmel: AT45DB011B) specific information */ | |
2436 | #define BUFFERED_FLASH_PAGE_POS 9 | |
2437 | #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1) | |
2438 | #define BUFFERED_FLASH_PAGE_SIZE 264 | |
2439 | #define BUFFERED_FLASH_PHY_PAGE_SIZE 512 | |
2440 | ||
2441 | T3_32BIT_REGISTER Config2; | |
2442 | T3_32BIT_REGISTER Config3; | |
2443 | T3_32BIT_REGISTER SwArb; | |
2444 | #define SW_ARB_REQ_SET0 BIT_0 | |
2445 | #define SW_ARB_REQ_SET1 BIT_1 | |
2446 | #define SW_ARB_REQ_SET2 BIT_2 | |
2447 | #define SW_ARB_REQ_SET3 BIT_3 | |
2448 | #define SW_ARB_REQ_CLR0 BIT_4 | |
2449 | #define SW_ARB_REQ_CLR1 BIT_5 | |
2450 | #define SW_ARB_REQ_CLR2 BIT_6 | |
2451 | #define SW_ARB_REQ_CLR3 BIT_7 | |
2452 | #define SW_ARB_GNT0 BIT_8 | |
2453 | #define SW_ARB_GNT1 BIT_9 | |
2454 | #define SW_ARB_GNT2 BIT_10 | |
2455 | #define SW_ARB_GNT3 BIT_11 | |
2456 | #define SW_ARB_REQ0 BIT_12 | |
2457 | #define SW_ARB_REQ1 BIT_13 | |
2458 | #define SW_ARB_REQ2 BIT_14 | |
2459 | #define SW_ARB_REQ3 BIT_15 | |
c609719b | 2460 | |
f539edc0 VB |
2461 | /* Unused space. */ |
2462 | LM_UINT8 Unused[988]; | |
2463 | } T3_NVRAM, *PT3_NVRAM; | |
c609719b WD |
2464 | |
2465 | /******************************************************************************/ | |
2466 | /* NIC's internal memory. */ | |
2467 | /******************************************************************************/ | |
2468 | ||
2469 | typedef struct { | |
f539edc0 VB |
2470 | /* Page zero for the internal CPUs. */ |
2471 | LM_UINT8 PageZero[0x100]; /* 0x0000 */ | |
c609719b | 2472 | |
f539edc0 VB |
2473 | /* Send RCBs. */ |
2474 | T3_RCB SendRcb[16]; /* 0x0100 */ | |
c609719b | 2475 | |
f539edc0 VB |
2476 | /* Receive Return RCBs. */ |
2477 | T3_RCB RcvRetRcb[16]; /* 0x0200 */ | |
c609719b | 2478 | |
f539edc0 VB |
2479 | /* Statistics block. */ |
2480 | T3_STATS_BLOCK StatsBlk; /* 0x0300 */ | |
c609719b | 2481 | |
f539edc0 VB |
2482 | /* Status block. */ |
2483 | T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */ | |
c609719b | 2484 | |
f539edc0 VB |
2485 | /* Reserved for software. */ |
2486 | LM_UINT8 Reserved[1200]; /* 0x0b50 */ | |
c609719b | 2487 | |
f539edc0 VB |
2488 | /* Unmapped region. */ |
2489 | LM_UINT8 Unmapped[4096]; /* 0x1000 */ | |
c609719b | 2490 | |
f539edc0 VB |
2491 | /* DMA descriptors. */ |
2492 | LM_UINT8 DmaDesc[8192]; /* 0x2000 */ | |
c609719b | 2493 | |
f539edc0 VB |
2494 | /* Buffer descriptors. */ |
2495 | LM_UINT8 BufferDesc[16384]; /* 0x4000 */ | |
c609719b WD |
2496 | } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM; |
2497 | ||
c609719b WD |
2498 | /******************************************************************************/ |
2499 | /* Memory layout. */ | |
2500 | /******************************************************************************/ | |
2501 | ||
2502 | typedef struct { | |
f539edc0 VB |
2503 | /* PCI configuration registers. */ |
2504 | T3_PCI_CONFIGURATION PciCfg; | |
c609719b | 2505 | |
f539edc0 VB |
2506 | /* Unused. */ |
2507 | LM_UINT8 Unused1[0x100]; /* 0x0100 */ | |
c609719b | 2508 | |
f539edc0 VB |
2509 | /* Mailbox . */ |
2510 | T3_MAILBOX Mailbox; /* 0x0200 */ | |
c609719b | 2511 | |
f539edc0 VB |
2512 | /* MAC control registers. */ |
2513 | T3_MAC_CONTROL MacCtrl; /* 0x0400 */ | |
c609719b | 2514 | |
f539edc0 VB |
2515 | /* Send data initiator control registers. */ |
2516 | T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */ | |
c609719b | 2517 | |
f539edc0 VB |
2518 | /* Send data completion Control registers. */ |
2519 | T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */ | |
c609719b | 2520 | |
f539edc0 VB |
2521 | /* Send BD ring selector. */ |
2522 | T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */ | |
c609719b | 2523 | |
f539edc0 VB |
2524 | /* Send BD initiator control registers. */ |
2525 | T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */ | |
c609719b | 2526 | |
f539edc0 VB |
2527 | /* Send BD completion control registers. */ |
2528 | T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */ | |
c609719b | 2529 | |
f539edc0 VB |
2530 | /* Receive list placement control registers. */ |
2531 | T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */ | |
c609719b | 2532 | |
f539edc0 VB |
2533 | /* Receive Data and Receive BD Initiator Control. */ |
2534 | T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */ | |
c609719b | 2535 | |
f539edc0 VB |
2536 | /* Receive Data Completion Control */ |
2537 | T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */ | |
c609719b | 2538 | |
f539edc0 VB |
2539 | /* Receive BD Initiator Control Registers. */ |
2540 | T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */ | |
c609719b | 2541 | |
f539edc0 VB |
2542 | /* Receive BD Completion Control Registers. */ |
2543 | T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */ | |
c609719b | 2544 | |
f539edc0 VB |
2545 | /* Receive list selector control registers. */ |
2546 | T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */ | |
c609719b | 2547 | |
f539edc0 VB |
2548 | /* Mbuf cluster free registers. */ |
2549 | T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */ | |
c609719b | 2550 | |
f539edc0 VB |
2551 | /* Host coalescing control registers. */ |
2552 | T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */ | |
c609719b | 2553 | |
f539edc0 VB |
2554 | /* Memory arbiter control registers. */ |
2555 | T3_MEM_ARBITER MemArbiter; /* 0x4000 */ | |
c609719b | 2556 | |
f539edc0 VB |
2557 | /* Buffer manger control registers. */ |
2558 | T3_BUFFER_MANAGER BufMgr; /* 0x4400 */ | |
c609719b | 2559 | |
f539edc0 VB |
2560 | /* Read DMA control registers. */ |
2561 | T3_DMA_READ DmaRead; /* 0x4800 */ | |
c609719b | 2562 | |
f539edc0 VB |
2563 | /* Write DMA control registers. */ |
2564 | T3_DMA_WRITE DmaWrite; /* 0x4c00 */ | |
c609719b | 2565 | |
f539edc0 VB |
2566 | T3_CPU rxCpu; /* 0x5000 */ |
2567 | T3_CPU txCpu; /* 0x5400 */ | |
c609719b | 2568 | |
f539edc0 VB |
2569 | /* Mailboxes. */ |
2570 | T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */ | |
c609719b | 2571 | |
f539edc0 VB |
2572 | /* Flow Through queues. */ |
2573 | T3_FTQ Ftq; /* 0x5c00 */ | |
c609719b | 2574 | |
f539edc0 VB |
2575 | /* Message signaled interrupt registes. */ |
2576 | T3_MSG_SIGNALED_INT Msi; /* 0x6000 */ | |
c609719b | 2577 | |
f539edc0 VB |
2578 | /* DMA completion registers. */ |
2579 | T3_DMA_COMPLETION DmaComp; /* 0x6400 */ | |
c609719b | 2580 | |
f539edc0 VB |
2581 | /* GRC registers. */ |
2582 | T3_GRC Grc; /* 0x6800 */ | |
c609719b | 2583 | |
f539edc0 VB |
2584 | /* Unused space. */ |
2585 | LM_UINT8 Unused2[1024]; /* 0x6c00 */ | |
c609719b | 2586 | |
f539edc0 VB |
2587 | /* NVRAM registers. */ |
2588 | T3_NVRAM Nvram; /* 0x7000 */ | |
c609719b | 2589 | |
f539edc0 VB |
2590 | /* Unused space. */ |
2591 | LM_UINT8 Unused3[3072]; /* 0x7400 */ | |
2592 | ||
2593 | /* The 32k memory window into the NIC's */ | |
2594 | /* internal memory. The memory window is */ | |
2595 | /* controlled by the Memory Window Base */ | |
2596 | /* Address register. This register is located */ | |
2597 | /* in the PCI configuration space. */ | |
2598 | union { /* 0x8000 */ | |
2599 | T3_FIRST_32K_SRAM First32k; | |
2600 | ||
2601 | /* Use the memory window base address register to determine the */ | |
2602 | /* MBUF segment. */ | |
2603 | LM_UINT32 Mbuf[32768 / 4]; | |
2604 | LM_UINT32 MemBlock32K[32768 / 4]; | |
2605 | } uIntMem; | |
c609719b WD |
2606 | } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP; |
2607 | ||
c609719b WD |
2608 | /******************************************************************************/ |
2609 | /* Adapter info. */ | |
2610 | /******************************************************************************/ | |
2611 | ||
f539edc0 VB |
2612 | typedef struct { |
2613 | LM_UINT16 Svid; | |
2614 | LM_UINT16 Ssid; | |
2615 | LM_UINT32 PhyId; | |
2616 | LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */ | |
c609719b WD |
2617 | } LM_ADAPTER_INFO, *PLM_ADAPTER_INFO; |
2618 | ||
c609719b WD |
2619 | /******************************************************************************/ |
2620 | /* Packet queues. */ | |
2621 | /******************************************************************************/ | |
2622 | ||
f539edc0 VB |
2623 | DECLARE_QUEUE_TYPE (LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT); |
2624 | DECLARE_QUEUE_TYPE (LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT); | |
c609719b | 2625 | |
c609719b WD |
2626 | /******************************************************************************/ |
2627 | /* Tx counters. */ | |
2628 | /******************************************************************************/ | |
2629 | ||
2630 | typedef struct { | |
f539edc0 VB |
2631 | LM_COUNTER TxPacketGoodCnt; |
2632 | LM_COUNTER TxBytesGoodCnt; | |
2633 | LM_COUNTER TxPacketAbortedCnt; | |
2634 | LM_COUNTER NoSendBdLeftCnt; | |
2635 | LM_COUNTER NoMapRegisterLeftCnt; | |
2636 | LM_COUNTER TooManyFragmentsCnt; | |
2637 | LM_COUNTER NoTxPacketDescCnt; | |
c609719b WD |
2638 | } LM_TX_COUNTERS, *PLM_TX_COUNTERS; |
2639 | ||
c609719b WD |
2640 | /******************************************************************************/ |
2641 | /* Rx counters. */ | |
2642 | /******************************************************************************/ | |
2643 | ||
2644 | typedef struct { | |
f539edc0 VB |
2645 | LM_COUNTER RxPacketGoodCnt; |
2646 | LM_COUNTER RxBytesGoodCnt; | |
2647 | LM_COUNTER RxPacketErrCnt; | |
2648 | LM_COUNTER RxErrCrcCnt; | |
2649 | LM_COUNTER RxErrCollCnt; | |
2650 | LM_COUNTER RxErrLinkLostCnt; | |
2651 | LM_COUNTER RxErrPhyDecodeCnt; | |
2652 | LM_COUNTER RxErrOddNibbleCnt; | |
2653 | LM_COUNTER RxErrMacAbortCnt; | |
2654 | LM_COUNTER RxErrShortPacketCnt; | |
2655 | LM_COUNTER RxErrNoResourceCnt; | |
2656 | LM_COUNTER RxErrLargePacketCnt; | |
c609719b WD |
2657 | } LM_RX_COUNTERS, *PLM_RX_COUNTERS; |
2658 | ||
c609719b WD |
2659 | /******************************************************************************/ |
2660 | /* Receive producer rings. */ | |
2661 | /******************************************************************************/ | |
2662 | ||
2663 | typedef enum { | |
f539edc0 VB |
2664 | T3_UNKNOWN_RCV_PROD_RING = 0, |
2665 | T3_STD_RCV_PROD_RING = 1, | |
2666 | T3_MINI_RCV_PROD_RING = 2, | |
2667 | T3_JUMBO_RCV_PROD_RING = 3 | |
c609719b WD |
2668 | } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING; |
2669 | ||
c609719b WD |
2670 | /******************************************************************************/ |
2671 | /* Packet descriptor. */ | |
2672 | /******************************************************************************/ | |
2673 | ||
2674 | #define LM_PACKET_SIGNATURE_TX 0x6861766b | |
2675 | #define LM_PACKET_SIGNATURE_RX 0x6b766168 | |
2676 | ||
2677 | typedef struct _LM_PACKET { | |
f539edc0 VB |
2678 | /* Set in LM. */ |
2679 | LM_STATUS PacketStatus; | |
c609719b | 2680 | |
f539edc0 VB |
2681 | /* Set in LM for Rx, in UM for Tx. */ |
2682 | LM_UINT32 PacketSize; | |
c609719b | 2683 | |
f539edc0 | 2684 | LM_UINT16 Flags; |
c609719b | 2685 | |
f539edc0 | 2686 | LM_UINT16 VlanTag; |
c609719b | 2687 | |
f539edc0 VB |
2688 | union { |
2689 | /* Send info. */ | |
2690 | struct { | |
2691 | /* Set up by UM. */ | |
2692 | LM_UINT32 FragCount; | |
c609719b | 2693 | |
f539edc0 | 2694 | } Tx; |
c609719b | 2695 | |
f539edc0 VB |
2696 | /* Receive info. */ |
2697 | struct { | |
2698 | /* This descriptor belongs to either Std, Mini, or Jumbo ring. */ | |
2699 | T3_RCV_PROD_RING RcvProdRing; | |
c609719b | 2700 | |
f539edc0 VB |
2701 | /* Receive buffer size */ |
2702 | LM_UINT32 RxBufferSize; | |
c609719b | 2703 | |
f539edc0 VB |
2704 | /* Checksum information. */ |
2705 | LM_UINT16 IpChecksum; | |
2706 | LM_UINT16 TcpUdpChecksum; | |
c609719b | 2707 | |
f539edc0 VB |
2708 | } Rx; |
2709 | } u; | |
c609719b WD |
2710 | } LM_PACKET; |
2711 | ||
c609719b WD |
2712 | /******************************************************************************/ |
2713 | /* Tigon3 device block. */ | |
2714 | /******************************************************************************/ | |
2715 | ||
2716 | typedef struct _LM_DEVICE_BLOCK { | |
f539edc0 VB |
2717 | int index; /* Device ID */ |
2718 | /* Memory view. */ | |
2719 | PT3_STD_MEM_MAP pMemView; | |
c609719b | 2720 | |
f539edc0 VB |
2721 | /* Base address of the block of memory in which the LM_PACKET descriptors */ |
2722 | /* are allocated from. */ | |
2723 | PLM_VOID pPacketDescBase; | |
c609719b | 2724 | |
f539edc0 VB |
2725 | LM_UINT32 MiscHostCtrl; |
2726 | LM_UINT32 GrcLocalCtrl; | |
2727 | LM_UINT32 DmaReadWriteCtrl; | |
2728 | LM_UINT32 PciState; | |
c609719b | 2729 | |
f539edc0 VB |
2730 | /* Rx info */ |
2731 | LM_UINT32 RxStdDescCnt; | |
2732 | LM_UINT32 RxStdQueuedCnt; | |
2733 | LM_UINT32 RxStdProdIdx; | |
c609719b | 2734 | |
f539edc0 VB |
2735 | PT3_RCV_BD pRxStdBdVirt; |
2736 | LM_PHYSICAL_ADDRESS RxStdBdPhy; | |
c609719b | 2737 | |
f539edc0 VB |
2738 | LM_UINT32 RxPacketDescCnt; |
2739 | LM_RX_PACKET_Q RxPacketFreeQ; | |
2740 | LM_RX_PACKET_Q RxPacketReceivedQ; | |
c609719b | 2741 | |
f539edc0 VB |
2742 | /* Receive info. */ |
2743 | PT3_RCV_BD pRcvRetBdVirt; | |
2744 | LM_PHYSICAL_ADDRESS RcvRetBdPhy; | |
2745 | LM_UINT32 RcvRetConIdx; | |
c609719b WD |
2746 | |
2747 | #if T3_JUMBO_RCV_RCB_ENTRY_COUNT | |
f539edc0 VB |
2748 | LM_UINT32 RxJumboDescCnt; |
2749 | LM_UINT32 RxJumboBufferSize; | |
2750 | LM_UINT32 RxJumboQueuedCnt; | |
2751 | ||
2752 | LM_UINT32 RxJumboProdIdx; | |
2753 | ||
2754 | PT3_RCV_BD pRxJumboBdVirt; | |
2755 | LM_PHYSICAL_ADDRESS RxJumboBdPhy; | |
2756 | #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ | |
c609719b | 2757 | |
f539edc0 VB |
2758 | /* These values are used by the upper module to inform the protocol */ |
2759 | /* of the maximum transmit/receive packet size. */ | |
2760 | LM_UINT32 TxMtu; /* Does not include CRC. */ | |
2761 | LM_UINT32 RxMtu; /* Does not include CRC. */ | |
c609719b | 2762 | |
f539edc0 VB |
2763 | /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */ |
2764 | /* we may have problems reading any MAC registers in 10mb mode. */ | |
2765 | LM_UINT32 MacMode; | |
2766 | LM_UINT32 RxMode; | |
2767 | LM_UINT32 TxMode; | |
c609719b | 2768 | |
f539edc0 VB |
2769 | /* MiMode register. */ |
2770 | LM_UINT32 MiMode; | |
c609719b | 2771 | |
f539edc0 VB |
2772 | /* Host coalesce mode register. */ |
2773 | LM_UINT32 CoalesceMode; | |
c609719b | 2774 | |
f539edc0 VB |
2775 | /* Send info. */ |
2776 | LM_UINT32 TxPacketDescCnt; | |
2777 | ||
2778 | /* Tx info. */ | |
2779 | LM_TX_PACKET_Q TxPacketFreeQ; | |
2780 | LM_TX_PACKET_Q TxPacketActiveQ; | |
2781 | LM_TX_PACKET_Q TxPacketXmittedQ; | |
2782 | ||
2783 | /* Pointers to SendBd. */ | |
2784 | PT3_SND_BD pSendBdVirt; | |
2785 | LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */ | |
2786 | ||
2787 | /* Send producer and consumer indices. */ | |
2788 | LM_UINT32 SendProdIdx; | |
2789 | LM_UINT32 SendConIdx; | |
2790 | ||
2791 | /* Number of BD left. */ | |
2792 | atomic_t SendBdLeft; | |
2793 | ||
2794 | T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT]; | |
2795 | ||
2796 | /* Counters. */ | |
2797 | LM_RX_COUNTERS RxCounters; | |
2798 | LM_TX_COUNTERS TxCounters; | |
2799 | ||
2800 | /* Host coalescing parameters. */ | |
2801 | LM_UINT32 RxCoalescingTicks; | |
2802 | LM_UINT32 TxCoalescingTicks; | |
2803 | LM_UINT32 RxMaxCoalescedFrames; | |
2804 | LM_UINT32 TxMaxCoalescedFrames; | |
2805 | LM_UINT32 StatsCoalescingTicks; | |
2806 | LM_UINT32 RxCoalescingTicksDuringInt; | |
2807 | LM_UINT32 TxCoalescingTicksDuringInt; | |
2808 | LM_UINT32 RxMaxCoalescedFramesDuringInt; | |
2809 | LM_UINT32 TxMaxCoalescedFramesDuringInt; | |
2810 | ||
2811 | /* DMA water marks. */ | |
2812 | LM_UINT32 DmaMbufLowMark; | |
2813 | LM_UINT32 RxMacMbufLowMark; | |
2814 | LM_UINT32 MbufHighMark; | |
2815 | ||
2816 | /* Status block. */ | |
2817 | PT3_STATUS_BLOCK pStatusBlkVirt; | |
2818 | LM_PHYSICAL_ADDRESS StatusBlkPhy; | |
2819 | ||
2820 | /* Statistics block. */ | |
2821 | PT3_STATS_BLOCK pStatsBlkVirt; | |
2822 | LM_PHYSICAL_ADDRESS StatsBlkPhy; | |
2823 | ||
2824 | /* Current receive mask. */ | |
2825 | LM_UINT32 ReceiveMask; | |
2826 | ||
2827 | /* Task offload capabilities. */ | |
2828 | LM_TASK_OFFLOAD TaskOffloadCap; | |
2829 | ||
2830 | /* Task offload selected. */ | |
2831 | LM_TASK_OFFLOAD TaskToOffload; | |
2832 | ||
2833 | /* Wake up capability. */ | |
2834 | LM_WAKE_UP_MODE WakeUpModeCap; | |
2835 | ||
2836 | /* Wake up capability. */ | |
2837 | LM_WAKE_UP_MODE WakeUpMode; | |
2838 | ||
2839 | /* Flow control. */ | |
2840 | LM_FLOW_CONTROL FlowControlCap; | |
2841 | LM_FLOW_CONTROL FlowControl; | |
2842 | ||
2843 | /* Enable or disable PCI MWI. */ | |
2844 | LM_UINT32 EnableMWI; | |
2845 | ||
2846 | /* Enable 5701 tagged status mode. */ | |
2847 | LM_UINT32 UseTaggedStatus; | |
2848 | ||
2849 | /* NIC will not compute the pseudo header checksum. The driver or OS */ | |
2850 | /* must seed the checksum field with the pseudo checksum. */ | |
2851 | LM_UINT32 NoTxPseudoHdrChksum; | |
2852 | ||
2853 | /* The receive checksum in the BD does not include the pseudo checksum. */ | |
2854 | /* The OS or the driver must calculate the pseudo checksum and add it to */ | |
2855 | /* the checksum in the BD. */ | |
2856 | LM_UINT32 NoRxPseudoHdrChksum; | |
2857 | ||
2858 | /* Current node address. */ | |
2859 | LM_UINT8 NodeAddress[8]; | |
2860 | ||
2861 | /* The adapter's node address. */ | |
2862 | LM_UINT8 PermanentNodeAddress[8]; | |
2863 | ||
2864 | /* Adapter info. */ | |
2865 | LM_UINT16 BusNum; | |
2866 | LM_UINT8 DevNum; | |
2867 | LM_UINT8 FunctNum; | |
2868 | LM_UINT16 PciVendorId; | |
2869 | LM_UINT16 PciDeviceId; | |
2870 | LM_UINT32 BondId; | |
2871 | LM_UINT8 Irq; | |
2872 | LM_UINT8 IntPin; | |
2873 | LM_UINT8 CacheLineSize; | |
2874 | LM_UINT8 PciRevId; | |
c609719b WD |
2875 | #if PCIX_TARGET_WORKAROUND |
2876 | LM_UINT32 EnablePciXFix; | |
2877 | #endif | |
f539edc0 VB |
2878 | LM_UINT32 UndiFix; /* new, jimmy */ |
2879 | LM_UINT32 PciCommandStatusWords; | |
2880 | LM_UINT32 ChipRevId; | |
2881 | LM_UINT16 SubsystemVendorId; | |
2882 | LM_UINT16 SubsystemId; | |
2883 | #if 0 /* Jimmy, deleted in new driver */ | |
2884 | LM_UINT32 MemBaseLow; | |
2885 | LM_UINT32 MemBaseHigh; | |
2886 | LM_UINT32 MemBaseSize; | |
c609719b | 2887 | #endif |
f539edc0 | 2888 | PLM_UINT8 pMappedMemBase; |
c609719b | 2889 | |
f539edc0 VB |
2890 | /* Saved PCI configuration registers for restoring after a reset. */ |
2891 | LM_UINT32 SavedCacheLineReg; | |
c609719b | 2892 | |
f539edc0 VB |
2893 | /* Phy info. */ |
2894 | LM_UINT32 PhyAddr; | |
2895 | LM_UINT32 PhyId; | |
c609719b | 2896 | |
f539edc0 VB |
2897 | /* Requested phy settings. */ |
2898 | LM_REQUESTED_MEDIA_TYPE RequestedMediaType; | |
c609719b | 2899 | |
f539edc0 VB |
2900 | /* Disable auto-negotiation. */ |
2901 | LM_UINT32 DisableAutoNeg; | |
c609719b | 2902 | |
f539edc0 VB |
2903 | /* Ways for the MAC to get link change interrupt. */ |
2904 | LM_UINT32 PhyIntMode; | |
2905 | #define T3_PHY_INT_MODE_AUTO 0 | |
2906 | #define T3_PHY_INT_MODE_MI_INTERRUPT 1 | |
2907 | #define T3_PHY_INT_MODE_LINK_READY 2 | |
2908 | #define T3_PHY_INT_MODE_AUTO_POLLING 3 | |
c609719b | 2909 | |
f539edc0 VB |
2910 | /* Ways to determine link change status. */ |
2911 | LM_UINT32 LinkChngMode; | |
2912 | #define T3_LINK_CHNG_MODE_AUTO 0 | |
2913 | #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1 | |
2914 | #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2 | |
c609719b | 2915 | |
f539edc0 VB |
2916 | /* LED mode. */ |
2917 | LM_UINT32 LedMode; | |
c609719b | 2918 | |
f539edc0 | 2919 | #define LED_MODE_AUTO 0 |
c609719b | 2920 | |
f539edc0 VB |
2921 | /* 5700/01 LED mode. */ |
2922 | #define LED_MODE_THREE_LINK 1 | |
2923 | #define LED_MODE_LINK10 2 | |
c609719b | 2924 | |
f539edc0 VB |
2925 | /* 5703/02/04 LED mode. */ |
2926 | #define LED_MODE_OPEN_DRAIN 1 | |
2927 | #define LED_MODE_OUTPUT 2 | |
c609719b | 2928 | |
f539edc0 VB |
2929 | /* WOL Speed */ |
2930 | LM_UINT32 WolSpeed; | |
2931 | #define WOL_SPEED_10MB 1 | |
2932 | #define WOL_SPEED_100MB 2 | |
c609719b | 2933 | |
f539edc0 VB |
2934 | /* Reset the PHY on initialization. */ |
2935 | LM_UINT32 ResetPhyOnInit; | |
c609719b | 2936 | |
f539edc0 VB |
2937 | LM_UINT32 RestoreOnWakeUp; |
2938 | LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType; | |
2939 | LM_UINT32 WakeUpDisableAutoNeg; | |
c609719b | 2940 | |
f539edc0 VB |
2941 | /* Current phy settings. */ |
2942 | LM_MEDIA_TYPE MediaType; | |
2943 | LM_LINE_SPEED LineSpeed; | |
2944 | LM_LINE_SPEED OldLineSpeed; | |
2945 | LM_DUPLEX_MODE DuplexMode; | |
2946 | LM_STATUS LinkStatus; | |
2947 | LM_UINT32 advertising; /* Jimmy, new! */ | |
2948 | LM_UINT32 advertising1000; /* Jimmy, new! */ | |
c609719b | 2949 | |
f539edc0 VB |
2950 | /* Multicast address list. */ |
2951 | LM_UINT32 McEntryCount; | |
2952 | LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE]; | |
c609719b | 2953 | |
f539edc0 VB |
2954 | /* Use NIC or Host based send BD. */ |
2955 | LM_UINT32 NicSendBd; | |
c609719b | 2956 | |
f539edc0 VB |
2957 | /* Athlon fix. */ |
2958 | LM_UINT32 DelayPciGrant; | |
c609719b | 2959 | |
f539edc0 VB |
2960 | /* Enable OneDmaAtOnce */ |
2961 | LM_UINT32 OneDmaAtOnce; | |
c609719b | 2962 | |
f539edc0 VB |
2963 | /* Split Mode flags, Jimmy new */ |
2964 | LM_UINT32 SplitModeEnable; | |
2965 | LM_UINT32 SplitModeMaxReq; | |
c609719b | 2966 | |
f539edc0 VB |
2967 | /* Init flag. */ |
2968 | LM_BOOL InitDone; | |
c609719b | 2969 | |
f539edc0 VB |
2970 | /* Shutdown flag. Set by the upper module. */ |
2971 | LM_BOOL ShuttingDown; | |
c609719b | 2972 | |
f539edc0 VB |
2973 | /* Flag to determine whether to call LM_QueueRxPackets or not in */ |
2974 | /* LM_ResetAdapter routine. */ | |
2975 | LM_BOOL QueueRxPackets; | |
c609719b | 2976 | |
f539edc0 VB |
2977 | LM_UINT32 MbufBase; |
2978 | LM_UINT32 MbufSize; | |
c609719b | 2979 | |
f539edc0 VB |
2980 | /* TRUE if we have a SERDES PHY. */ |
2981 | LM_UINT32 EnableTbi; | |
c609719b | 2982 | |
f539edc0 VB |
2983 | /* Ethernet@WireSpeed. */ |
2984 | LM_UINT32 EnableWireSpeed; | |
c609719b | 2985 | |
f539edc0 | 2986 | LM_UINT32 EepromWp; |
c609719b WD |
2987 | |
2988 | #if INCLUDE_TBI_SUPPORT | |
f539edc0 VB |
2989 | /* Autoneg state info. */ |
2990 | AN_STATE_INFO AnInfo; | |
2991 | LM_UINT32 PollTbiLink; | |
2992 | LM_UINT32 IgnoreTbiLinkChange; | |
c609719b | 2993 | #endif |
f539edc0 VB |
2994 | char PartNo[24]; |
2995 | char BootCodeVer[16]; | |
2996 | char BusSpeedStr[24]; /* Jimmy, new! */ | |
2997 | LM_UINT32 PhyCrcCount; | |
c609719b WD |
2998 | } LM_DEVICE_BLOCK; |
2999 | ||
c609719b WD |
3000 | #define T3_REG_CPU_VIEW 0xc0000000 |
3001 | ||
3002 | #define T3_BLOCK_DMA_RD (1 << 0) | |
3003 | #define T3_BLOCK_DMA_COMP (1 << 1) | |
3004 | #define T3_BLOCK_RX_BD_INITIATOR (1 << 2) | |
3005 | #define T3_BLOCK_RX_BD_COMP (1 << 3) | |
3006 | #define T3_BLOCK_DMA_WR (1 << 4) | |
3007 | #define T3_BLOCK_MSI_HANDLER (1 << 5) | |
3008 | #define T3_BLOCK_RX_LIST_PLMT (1 << 6) | |
3009 | #define T3_BLOCK_RX_LIST_SELECTOR (1 << 7) | |
3010 | #define T3_BLOCK_RX_DATA_INITIATOR (1 << 8) | |
3011 | #define T3_BLOCK_RX_DATA_COMP (1 << 9) | |
3012 | #define T3_BLOCK_HOST_COALESING (1 << 10) | |
3013 | #define T3_BLOCK_MAC_RX_ENGINE (1 << 11) | |
3014 | #define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12) | |
3015 | #define T3_BLOCK_SEND_BD_INITIATOR (1 << 13) | |
3016 | #define T3_BLOCK_SEND_BD_COMP (1 << 14) | |
3017 | #define T3_BLOCK_SEND_BD_SELECTOR (1 << 15) | |
3018 | #define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16) | |
3019 | #define T3_BLOCK_SEND_DATA_COMP (1 << 17) | |
3020 | #define T3_BLOCK_MAC_TX_ENGINE (1 << 18) | |
3021 | #define T3_BLOCK_MEM_ARBITOR (1 << 19) | |
3022 | #define T3_BLOCK_MBUF_MANAGER (1 << 20) | |
3023 | #define T3_BLOCK_MAC_GLOBAL (1 << 21) | |
3024 | ||
3025 | #define LM_ENABLE 1 | |
3026 | #define LM_DISABLE 2 | |
3027 | ||
3028 | #define RX_CPU_EVT_SW0 0 | |
3029 | #define RX_CPU_EVT_SW1 1 | |
3030 | #define RX_CPU_EVT_RLP 2 | |
3031 | #define RX_CPU_EVT_SW3 3 | |
3032 | #define RX_CPU_EVT_RLS 4 | |
3033 | #define RX_CPU_EVT_SW4 5 | |
3034 | #define RX_CPU_EVT_RX_BD_COMP 6 | |
3035 | #define RX_CPU_EVT_SW5 7 | |
3036 | #define RX_CPU_EVT_RDI 8 | |
3037 | #define RX_CPU_EVT_DMA_WR 9 | |
3038 | #define RX_CPU_EVT_DMA_RD 10 | |
3039 | #define RX_CPU_EVT_SWQ 11 | |
3040 | #define RX_CPU_EVT_SW6 12 | |
3041 | #define RX_CPU_EVT_RDC 13 | |
3042 | #define RX_CPU_EVT_SW7 14 | |
3043 | #define RX_CPU_EVT_HOST_COALES 15 | |
3044 | #define RX_CPU_EVT_SW8 16 | |
3045 | #define RX_CPU_EVT_HIGH_DMA_WR 17 | |
3046 | #define RX_CPU_EVT_HIGH_DMA_RD 18 | |
3047 | #define RX_CPU_EVT_SW9 19 | |
3048 | #define RX_CPU_EVT_DMA_ATTN 20 | |
3049 | #define RX_CPU_EVT_LOW_P_MBOX 21 | |
3050 | #define RX_CPU_EVT_HIGH_P_MBOX 22 | |
3051 | #define RX_CPU_EVT_SW10 23 | |
3052 | #define RX_CPU_EVT_TX_CPU_ATTN 24 | |
3053 | #define RX_CPU_EVT_MAC_ATTN 25 | |
3054 | #define RX_CPU_EVT_RX_CPU_ATTN 26 | |
3055 | #define RX_CPU_EVT_FLOW_ATTN 27 | |
3056 | #define RX_CPU_EVT_SW11 28 | |
3057 | #define RX_CPU_EVT_TIMER 29 | |
3058 | #define RX_CPU_EVT_SW12 30 | |
3059 | #define RX_CPU_EVT_SW13 31 | |
3060 | ||
3061 | /* RX-CPU event */ | |
3062 | #define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0) | |
3063 | #define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1) | |
3064 | #define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP) | |
3065 | #define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3) | |
3066 | #define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS) | |
3067 | #define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4) | |
3068 | #define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP) | |
3069 | #define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5) | |
3070 | #define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI) | |
3071 | #define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR) | |
3072 | #define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD) | |
3073 | #define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ) | |
3074 | #define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6) | |
3075 | #define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC) | |
3076 | #define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7) | |
3077 | #define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES) | |
3078 | #define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8) | |
3079 | #define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR) | |
3080 | #define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD) | |
3081 | #define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9) | |
3082 | #define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN) | |
3083 | #define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX) | |
3084 | #define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX) | |
3085 | #define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10) | |
3086 | #define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN) | |
3087 | #define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN) | |
3088 | #define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN) | |
3089 | #define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN) | |
3090 | #define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11) | |
3091 | #define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER) | |
3092 | #define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12) | |
3093 | #define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13) | |
3094 | ||
3095 | #define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \ | |
3096 | RX_CPU_EVENT_RLP | \ | |
3097 | RX_CPU_EVENT_RDI | \ | |
3098 | RX_CPU_EVENT_RDC) | |
3099 | ||
3100 | #define TX_CPU_EVT_SW0 0 | |
3101 | #define TX_CPU_EVT_SW1 1 | |
3102 | #define TX_CPU_EVT_SW2 2 | |
3103 | #define TX_CPU_EVT_SW3 3 | |
3104 | #define TX_CPU_EVT_TX_MAC 4 | |
3105 | #define TX_CPU_EVT_SW4 5 | |
3106 | #define TX_CPU_EVT_SBDC 6 | |
3107 | #define TX_CPU_EVT_SW5 7 | |
3108 | #define TX_CPU_EVT_SDI 8 | |
3109 | #define TX_CPU_EVT_DMA_WR 9 | |
3110 | #define TX_CPU_EVT_DMA_RD 10 | |
3111 | #define TX_CPU_EVT_SWQ 11 | |
3112 | #define TX_CPU_EVT_SW6 12 | |
3113 | #define TX_CPU_EVT_SDC 13 | |
3114 | #define TX_CPU_EVT_SW7 14 | |
3115 | #define TX_CPU_EVT_HOST_COALES 15 | |
3116 | #define TX_CPU_EVT_SW8 16 | |
3117 | #define TX_CPU_EVT_HIGH_DMA_WR 17 | |
3118 | #define TX_CPU_EVT_HIGH_DMA_RD 18 | |
3119 | #define TX_CPU_EVT_SW9 19 | |
3120 | #define TX_CPU_EVT_DMA_ATTN 20 | |
3121 | #define TX_CPU_EVT_LOW_P_MBOX 21 | |
3122 | #define TX_CPU_EVT_HIGH_P_MBOX 22 | |
3123 | #define TX_CPU_EVT_SW10 23 | |
3124 | #define TX_CPU_EVT_RX_CPU_ATTN 24 | |
3125 | #define TX_CPU_EVT_MAC_ATTN 25 | |
3126 | #define TX_CPU_EVT_TX_CPU_ATTN 26 | |
3127 | #define TX_CPU_EVT_FLOW_ATTN 27 | |
3128 | #define TX_CPU_EVT_SW11 28 | |
3129 | #define TX_CPU_EVT_TIMER 29 | |
3130 | #define TX_CPU_EVT_SW12 30 | |
3131 | #define TX_CPU_EVT_SW13 31 | |
3132 | ||
c609719b WD |
3133 | /* TX-CPU event */ |
3134 | #define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0) | |
3135 | #define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1) | |
3136 | #define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2) | |
3137 | #define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3) | |
3138 | #define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC) | |
3139 | #define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4) | |
3140 | #define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC) | |
3141 | #define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5) | |
3142 | #define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI) | |
3143 | #define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR) | |
3144 | #define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD) | |
3145 | #define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ) | |
3146 | #define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6) | |
3147 | #define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC) | |
3148 | #define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7) | |
3149 | #define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES) | |
3150 | #define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8) | |
3151 | #define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR) | |
3152 | #define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD) | |
3153 | #define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9) | |
3154 | #define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN) | |
3155 | #define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX) | |
3156 | #define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX) | |
3157 | #define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10) | |
3158 | #define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN) | |
3159 | #define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN) | |
3160 | #define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN) | |
3161 | #define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN) | |
3162 | #define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11) | |
3163 | #define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER) | |
3164 | #define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12) | |
3165 | #define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13) | |
3166 | ||
c609719b WD |
3167 | #define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \ |
3168 | TX_CPU_EVENT_SDI | \ | |
3169 | TX_CPU_EVENT_SDC) | |
3170 | ||
c609719b WD |
3171 | #define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29) |
3172 | #define T3_FTQ_TYPE1_PASS_BIT (1 << 30) | |
3173 | #define T3_FTQ_TYPE1_SKIP_BIT (1 << 31) | |
3174 | ||
3175 | #define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13) | |
3176 | #define T3_FTQ_TYPE2_PASS_BIT (1 << 14) | |
3177 | #define T3_FTQ_TYPE2_SKIP_BIT (1 << 15) | |
3178 | ||
3179 | #define T3_QID_DMA_READ 1 | |
3180 | #define T3_QID_DMA_HIGH_PRI_READ 2 | |
3181 | #define T3_QID_DMA_COMP_DX 3 | |
3182 | #define T3_QID_SEND_BD_COMP 4 | |
3183 | #define T3_QID_SEND_DATA_INITIATOR 5 | |
3184 | #define T3_QID_DMA_WRITE 6 | |
3185 | #define T3_QID_DMA_HIGH_PRI_WRITE 7 | |
3186 | #define T3_QID_SW_TYPE_1 8 | |
3187 | #define T3_QID_SEND_DATA_COMP 9 | |
3188 | #define T3_QID_HOST_COALESCING 10 | |
3189 | #define T3_QID_MAC_TX 11 | |
3190 | #define T3_QID_MBUF_CLUSTER_FREE 12 | |
3191 | #define T3_QID_RX_BD_COMP 13 | |
3192 | #define T3_QID_RX_LIST_PLM 14 | |
3193 | #define T3_QID_RX_DATA_BD_INITIATOR 15 | |
3194 | #define T3_QID_RX_DATA_COMP 16 | |
3195 | #define T3_QID_SW_TYPE2 17 | |
3196 | ||
f539edc0 VB |
3197 | LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice, |
3198 | PT3_FWIMG_INFO pFwImg, | |
3199 | LM_UINT32 LoadCpu, LM_UINT32 StartCpu); | |
c609719b WD |
3200 | |
3201 | /******************************************************************************/ | |
3202 | /* NIC register read/write macros. */ | |
3203 | /******************************************************************************/ | |
3204 | ||
f539edc0 | 3205 | #if 0 /* Jimmy */ |
c609719b | 3206 | /* MAC register access. */ |
f539edc0 VB |
3207 | LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); |
3208 | LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, | |
3209 | LM_UINT32 Value32); | |
c609719b WD |
3210 | |
3211 | /* MAC memory access. */ | |
f539edc0 VB |
3212 | LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); |
3213 | LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, | |
3214 | LM_UINT32 Value32); | |
c609719b WD |
3215 | |
3216 | #if PCIX_TARGET_WORKAROUND | |
3217 | ||
3218 | /* use memory-mapped accesses for mailboxes and reads, UNDI accesses | |
3219 | for writes to all other registers */ | |
3220 | #define REG_RD(pDevice, OffsetName) \ | |
3221 | readl(&((pDevice)->pMemView->OffsetName)) | |
3222 | ||
3223 | #define REG_WR(pDevice, OffsetName, Value32) \ | |
3224 | (((OFFSETOF(T3_STD_MEM_MAP, OffsetName) >=0x200 ) && \ | |
3225 | (OFFSETOF(T3_STD_MEM_MAP, OffsetName) <0x400)) || \ | |
3226 | ((pDevice)->EnablePciXFix == FALSE)) ? \ | |
3227 | (void) writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ | |
3228 | LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) | |
3229 | ||
3230 | #define MB_REG_RD(pDevice, OffsetName) \ | |
3231 | readl(&((pDevice)->pMemView->OffsetName)) | |
3232 | ||
3233 | #define MB_REG_WR(pDevice, OffsetName, Value32) \ | |
3234 | writel(Value32, &((pDevice)->pMemView->OffsetName)) | |
3235 | ||
3236 | #define REG_RD_OFFSET(pDevice, Offset) \ | |
3237 | readl(&((LM_UINT8 *) (pDevice)->pMemView + Offset)) | |
3238 | ||
3239 | #define REG_WR_OFFSET(pDevice, Offset, Value32) \ | |
3240 | (((Offset >=0x200 ) && (Offset < 0x400)) || \ | |
53677ef1 | 3241 | ((pDevice)->EnablePciXFix == FALSE)) ? \ |
c609719b WD |
3242 | (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \ |
3243 | LM_RegWrInd(pDevice, Offset, Value32) | |
3244 | ||
3245 | #define MEM_RD(pDevice, AddrName) \ | |
3246 | LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) | |
3247 | #define MEM_WR(pDevice, AddrName, Value32) \ | |
3248 | LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) | |
3249 | ||
3250 | #define MEM_RD_OFFSET(pDevice, Offset) \ | |
3251 | LM_MemRdInd(pDevice, Offset) | |
3252 | #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ | |
3253 | LM_MemWrInd(pDevice, Offset, Value32) | |
3254 | ||
f539edc0 | 3255 | #else /* normal target access path below */ |
c609719b WD |
3256 | |
3257 | /* Register access. */ | |
3258 | #define REG_RD(pDevice, OffsetName) \ | |
3259 | readl(&((pDevice)->pMemView->OffsetName)) | |
3260 | #define REG_WR(pDevice, OffsetName, Value32) \ | |
3261 | writel(Value32, &((pDevice)->pMemView->OffsetName)) | |
3262 | ||
3263 | #define REG_RD_OFFSET(pDevice, Offset) \ | |
3264 | readl(((LM_UINT8 *) (pDevice)->pMemView + Offset)) | |
3265 | #define REG_WR_OFFSET(pDevice, Offset, Value32) \ | |
3266 | writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) | |
3267 | ||
c609719b WD |
3268 | /* There could be problem access the memory window directly. For now, */ |
3269 | /* we have to go through the PCI configuration register. */ | |
3270 | #define MEM_RD(pDevice, AddrName) \ | |
3271 | LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) | |
3272 | #define MEM_WR(pDevice, AddrName, Value32) \ | |
3273 | LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) | |
3274 | ||
3275 | #define MEM_RD_OFFSET(pDevice, Offset) \ | |
3276 | LM_MemRdInd(pDevice, Offset) | |
3277 | #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ | |
3278 | LM_MemWrInd(pDevice, Offset, Value32) | |
3279 | ||
f539edc0 | 3280 | #endif /* PCIX_TARGET_WORKAROUND */ |
c609719b | 3281 | |
f539edc0 | 3282 | #endif /* Jimmy, merging */ |
c609719b WD |
3283 | |
3284 | /* Jimmy...rest of file is new stuff! */ | |
3285 | /******************************************************************************/ | |
3286 | /* NIC register read/write macros. */ | |
3287 | /******************************************************************************/ | |
3288 | ||
3289 | /* MAC register access. */ | |
f539edc0 VB |
3290 | LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); |
3291 | LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, | |
3292 | LM_UINT32 Value32); | |
c609719b WD |
3293 | |
3294 | /* MAC memory access. */ | |
f539edc0 VB |
3295 | LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); |
3296 | LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, | |
3297 | LM_UINT32 Value32); | |
c609719b WD |
3298 | |
3299 | #define MB_REG_WR(pDevice, OffsetName, Value32) \ | |
3300 | ((pDevice)->UndiFix) ? \ | |
8bde7f77 WD |
3301 | LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ |
3302 | Value32) : \ | |
3303 | (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) | |
c609719b WD |
3304 | |
3305 | #define MB_REG_RD(pDevice, OffsetName) \ | |
3306 | (((pDevice)->UndiFix) ? \ | |
8bde7f77 WD |
3307 | LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ |
3308 | __raw_readl(&((pDevice)->pMemView->OffsetName))) | |
c609719b WD |
3309 | |
3310 | #define REG_RD(pDevice, OffsetName) \ | |
3311 | (((pDevice)->UndiFix) ? \ | |
8bde7f77 WD |
3312 | LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \ |
3313 | __raw_readl(&((pDevice)->pMemView->OffsetName))) | |
c609719b WD |
3314 | |
3315 | #if PCIX_TARGET_WORKAROUND | |
3316 | ||
3317 | #define REG_WR(pDevice, OffsetName, Value32) \ | |
3318 | ((pDevice)->EnablePciXFix == FALSE) ? \ | |
3319 | (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ | |
3320 | LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) | |
3321 | ||
3322 | #else | |
3323 | ||
3324 | #define REG_WR(pDevice, OffsetName, Value32) \ | |
3325 | __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) | |
3326 | ||
3327 | #endif | |
3328 | ||
3329 | #define MEM_RD(pDevice, AddrName) \ | |
3330 | LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) | |
3331 | #define MEM_WR(pDevice, AddrName, Value32) \ | |
3332 | LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) | |
3333 | ||
3334 | #define MEM_RD_OFFSET(pDevice, Offset) \ | |
3335 | LM_MemRdInd(pDevice, Offset) | |
3336 | #define MEM_WR_OFFSET(pDevice, Offset, Value32) \ | |
3337 | LM_MemWrInd(pDevice, Offset, Value32) | |
3338 | ||
f539edc0 | 3339 | #endif /* TIGON3_H */ |