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1f103105 1/*
0ef91193 2 * Copyright 2007, 2010 Freescale Semiconductor, Inc.
1f103105
RZ		 3 *
4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
5 *
6 * Description:
7 * ULI 526x Ethernet port driver.
8 * Based on the Linux driver: drivers/net/tulip/uli526x.c
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
1f103105
RZ		 11 */
12
13#include <common.h>
14#include <malloc.h>
15#include <net.h>
89973f8a 16#include <netdev.h>
1f103105
RZ		 17#include <asm/io.h>
18#include <pci.h>
19#include <miiphy.h>
20
21/* some kernel function compatible define */
22
1f103105
RZ		 23#undef DEBUG
24
25/* Board/System/Debug information/definition */
26#define ULI_VENDOR_ID 0x10B9
27#define ULI5261_DEVICE_ID 0x5261
28#define ULI5263_DEVICE_ID 0x5263
29/* ULi M5261 ID*/
e845e07e 30#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
1f103105 31/* ULi M5263 ID*/
e845e07e 32#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
1f103105
RZ		 33
34#define ULI526X_IO_SIZE 0x100
35#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
36#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
37#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
38#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
39#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
40#define TX_BUF_ALLOC 0x300
41#define RX_ALLOC_SIZE PKTSIZE
42#define ULI526X_RESET 1
43#define CR0_DEFAULT 0
44#define CR6_DEFAULT 0x22200000
45#define CR7_DEFAULT 0x180c1
46#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
47#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
48#define MAX_PACKET_SIZE 1514
49#define ULI5261_MAX_MULTICAST 14
50#define RX_COPY_SIZE 100
51#define MAX_CHECK_PACKET 0x8000
52
53#define ULI526X_10MHF 0
54#define ULI526X_100MHF 1
55#define ULI526X_10MFD 4
56#define ULI526X_100MFD 5
57#define ULI526X_AUTO 8
58
59#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
60#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
61#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
62#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
63#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
64#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
65
66/* CR9 definition: SROM/MII */
67#define CR9_SROM_READ 0x4800
68#define CR9_SRCS 0x1
69#define CR9_SRCLK 0x2
70#define CR9_CRDOUT 0x8
71#define SROM_DATA_0 0x0
72#define SROM_DATA_1 0x4
73#define PHY_DATA_1 0x20000
74#define PHY_DATA_0 0x00000
75#define MDCLKH 0x10000
76
77#define PHY_POWER_DOWN 0x800
78
79#define SROM_V41_CODE 0x14
80
81#define SROM_CLK_WRITE(data, ioaddr) do { \
82 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
83 udelay(5); \
84 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
85 udelay(5); \
86 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
87 udelay(5); \
88 } while (0)
89
90/* Structure/enum declaration */
91
92struct tx_desc {
93 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
94 char *tx_buf_ptr; /* Data for us */
95 struct tx_desc *next_tx_desc;
96};
97
98struct rx_desc {
99 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
100 char *rx_buf_ptr; /* Data for us */
101 struct rx_desc *next_rx_desc;
102};
103
104struct uli526x_board_info {
105 u32 chip_id; /* Chip vendor/Device ID */
106 pci_dev_t pdev;
107
108 long ioaddr; /* I/O base address */
109 u32 cr0_data;
110 u32 cr5_data;
111 u32 cr6_data;
112 u32 cr7_data;
113 u32 cr15_data;
114
115 /* pointer for memory physical address */
116 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
117 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
118 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
119 dma_addr_t first_tx_desc_dma;
120 dma_addr_t first_rx_desc_dma;
121
122 /* descriptor pointer */
123 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
124 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
125 unsigned char *desc_pool_ptr; /* descriptor pool memory */
126 struct tx_desc *first_tx_desc;
127 struct tx_desc *tx_insert_ptr;
128 struct tx_desc *tx_remove_ptr;
129 struct rx_desc *first_rx_desc;
130 struct rx_desc *rx_ready_ptr; /* packet come pointer */
131 unsigned long tx_packet_cnt; /* transmitted packet count */
132
133 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
134
135 u8 media_mode; /* user specify media mode */
136 u8 op_mode; /* real work dedia mode */
137 u8 phy_addr;
138
139 /* NIC SROM data */
140 unsigned char srom[128];
141};
142
143enum uli526x_offsets {
144 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
145 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
146 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
147 DCR15 = 0x78
148};
149
150enum uli526x_CR6_bits {
151 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
152 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
153 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
154};
155
156/* Global variable declaration -- */
157
158static unsigned char uli526x_media_mode = ULI526X_AUTO;
159
160static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
161 __attribute__ ((aligned(32)));
162static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
163
164/* For module input parameter */
165static int mode = 8;
166
167/* function declaration -- */
4b942150 168static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
1f103105
RZ		 169static const struct ethtool_ops netdev_ethtool_ops;
170static u16 read_srom_word(long, int);
171static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
172static void allocate_rx_buffer(struct uli526x_board_info *);
173static void update_cr6(u32, unsigned long);
09c04c20 174static u16 uli_phy_read(unsigned long, u8, u8, u32);
1f103105 175static u16 phy_readby_cr10(unsigned long, u8, u8);
09c04c20 176static void uli_phy_write(unsigned long, u8, u8, u16, u32);
1f103105
RZ		 177static void phy_writeby_cr10(unsigned long, u8, u8, u16);
178static void phy_write_1bit(unsigned long, u32, u32);
179static u16 phy_read_1bit(unsigned long, u32);
180static int uli526x_rx_packet(struct eth_device *);
181static void uli526x_free_tx_pkt(struct eth_device *,
182 struct uli526x_board_info *);
183static void uli526x_reuse_buf(struct rx_desc *);
184static void uli526x_init(struct eth_device *);
185static void uli526x_set_phyxcer(struct uli526x_board_info *);
186
187
188static int uli526x_init_one(struct eth_device *, bd_t *);
189static void uli526x_disable(struct eth_device *);
190static void set_mac_addr(struct eth_device *);
191
192static struct pci_device_id uli526x_pci_tbl[] = {
193 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
194 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
195 {}
196};
197
198/* ULI526X network board routine */
199
200/*
201 * Search ULI526X board, register it
202 */
203
204int uli526x_initialize(bd_t *bis)
205{
206 pci_dev_t devno;
207 int card_number = 0;
208 struct eth_device *dev;
209 struct uli526x_board_info *db; /* board information structure */
210
211 u32 iobase;
212 int idx = 0;
213
214 while (1) {
215 /* Find PCI device */
216 devno = pci_find_devices(uli526x_pci_tbl, idx++);
217 if (devno < 0)
218 break;
219
220 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
221 iobase &= ~0xf;
222
223 dev = (struct eth_device *)malloc(sizeof *dev);
fe7f1883
NI		 224 if (!dev) {
225 printf("uli526x: Can not allocate memory\n");
226 break;
227 }
228 memset(dev, 0, sizeof(*dev));
ec0d879f 229 sprintf(dev->name, "uli526x#%d", card_number);
1f103105
RZ		 230 db = (struct uli526x_board_info *)
231 malloc(sizeof(struct uli526x_board_info));
232
233 dev->priv = db;
234 db->pdev = devno;
235 dev->iobase = iobase;
236
237 dev->init = uli526x_init_one;
238 dev->halt = uli526x_disable;
239 dev->send = uli526x_start_xmit;
240 dev->recv = uli526x_rx_packet;
241
242 /* init db */
243 db->ioaddr = dev->iobase;
244 /* get chip id */
245
246 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
247#ifdef DEBUG
248 printf("uli526x: uli526x @0x%x\n", iobase);
249 printf("uli526x: chip_id%x\n", db->chip_id);
250#endif
251 eth_register(dev);
252 card_number++;
253 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
254 udelay(10 * 1000);
255 }
256 return card_number;
257}
258
259static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
260{
261
262 struct uli526x_board_info *db = dev->priv;
263 int i;
264
265 switch (mode) {
266 case ULI526X_10MHF:
267 case ULI526X_100MHF:
268 case ULI526X_10MFD:
269 case ULI526X_100MFD:
270 uli526x_media_mode = mode;
271 break;
272 default:
273 uli526x_media_mode = ULI526X_AUTO;
274 break;
275 }
276
277 /* Allocate Tx/Rx descriptor memory */
278 db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
279 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
280 if (db->desc_pool_ptr == NULL)
422b1a01 281 return -1;
1f103105 282
e845e07e 283 db->buf_pool_ptr = (uchar *)&buf_pool[0];
1f103105
RZ		 284 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
285 if (db->buf_pool_ptr == NULL)
422b1a01 286 return -1;
1f103105
RZ		 287
288 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
289 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
290
291 db->buf_pool_start = db->buf_pool_ptr;
292 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
293
294#ifdef DEBUG
295 printf("%s(): db->ioaddr= 0x%x\n",
296 __FUNCTION__, db->ioaddr);
297 printf("%s(): media_mode= 0x%x\n",
298 __FUNCTION__, uli526x_media_mode);
299 printf("%s(): db->desc_pool_ptr= 0x%x\n",
300 __FUNCTION__, db->desc_pool_ptr);
301 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
302 __FUNCTION__, db->desc_pool_dma_ptr);
303 printf("%s(): db->buf_pool_ptr= 0x%x\n",
304 __FUNCTION__, db->buf_pool_ptr);
305 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
306 __FUNCTION__, db->buf_pool_dma_ptr);
307#endif
308
309 /* read 64 word srom data */
310 for (i = 0; i < 64; i++)
311 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
312 i));
313
314 /* Set Node address */
0ef91193
KG		 315 if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
316 ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
1f103105
RZ		 317 /* SROM absent, so write MAC address to ID Table */
318 set_mac_addr(dev);
319 else { /*Exist SROM*/
320 for (i = 0; i < 6; i++)
321 dev->enetaddr[i] = db->srom[20 + i];
322 }
323#ifdef DEBUG
324 for (i = 0; i < 6; i++)
325 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
326#endif
327 db->PHY_reg4 = 0x1e0;
328
329 /* system variable init */
330 db->cr6_data = CR6_DEFAULT ;
331 db->cr6_data |= ULI526X_TXTH_256;
332 db->cr0_data = CR0_DEFAULT;
333 uli526x_init(dev);
422b1a01 334 return 0;
1f103105
RZ		 335}
336
337static void uli526x_disable(struct eth_device *dev)
338{
339#ifdef DEBUG
340 printf("uli526x_disable\n");
341#endif
342 struct uli526x_board_info *db = dev->priv;
343
344 if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
345 /* Reset & stop ULI526X board */
346 outl(ULI526X_RESET, db->ioaddr + DCR0);
347 udelay(5);
09c04c20 348 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
1f103105
RZ		 349
350 /* reset the board */
351 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
352 update_cr6(db->cr6_data, dev->iobase);
353 outl(0, dev->iobase + DCR7); /* Disable Interrupt */
354 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
355 }
356}
357
358/* Initialize ULI526X board
359 * Reset ULI526X board
360 * Initialize TX/Rx descriptor chain structure
361 * Send the set-up frame
362 * Enable Tx/Rx machine
363 */
364
365static void uli526x_init(struct eth_device *dev)
366{
367
368 struct uli526x_board_info *db = dev->priv;
369 u8 phy_tmp;
370 u16 phy_value;
371 u16 phy_reg_reset;
372
373 /* Reset M526x MAC controller */
374 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
375 udelay(100);
376 outl(db->cr0_data, db->ioaddr + DCR0);
377 udelay(5);
378
379 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
380 db->phy_addr = 1;
381 db->tx_packet_cnt = 0;
382 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
383 /* peer add */
09c04c20 384 phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
1f103105
RZ		 385 if (phy_value != 0xffff && phy_value != 0) {
386 db->phy_addr = phy_tmp;
387 break;
388 }
389 }
390
391#ifdef DEBUG
392 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
393 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
394#endif
395 if (phy_tmp == 32)
396 printf("Can not find the phy address!!!");
397
398 /* Parser SROM and media mode */
399 db->media_mode = uli526x_media_mode;
400
401 if (!(inl(db->ioaddr + DCR12) & 0x8)) {
402 /* Phyxcer capability setting */
09c04c20 403 phy_reg_reset = uli_phy_read(db->ioaddr,
1f103105
RZ		 404 db->phy_addr, 0, db->chip_id);
405 phy_reg_reset = (phy_reg_reset | 0x8000);
09c04c20 406 uli_phy_write(db->ioaddr, db->phy_addr, 0,
1f103105
RZ		 407 phy_reg_reset, db->chip_id);
408 udelay(500);
409
410 /* Process Phyxcer Media Mode */
411 uli526x_set_phyxcer(db);
412 }
413 /* Media Mode Process */
414 if (!(db->media_mode & ULI526X_AUTO))
53677ef1 415 db->op_mode = db->media_mode; /* Force Mode */
1f103105
RZ		 416
417 /* Initialize Transmit/Receive decriptor and CR3/4 */
418 uli526x_descriptor_init(db, db->ioaddr);
419
420 /* Init CR6 to program M526X operation */
421 update_cr6(db->cr6_data, db->ioaddr);
422
423 /* Init CR7, interrupt active bit */
424 db->cr7_data = CR7_DEFAULT;
425 outl(db->cr7_data, db->ioaddr + DCR7);
426
427 /* Init CR15, Tx jabber and Rx watchdog timer */
428 outl(db->cr15_data, db->ioaddr + DCR15);
429
430 /* Enable ULI526X Tx/Rx function */
431 db->cr6_data |= CR6_RXSC | CR6_TXSC;
432 update_cr6(db->cr6_data, db->ioaddr);
433 while (!(inl(db->ioaddr + DCR12) & 0x8))
434 udelay(10);
435}
436
437/*
438 * Hardware start transmission.
439 * Send a packet to media from the upper layer.
440 */
441
4b942150 442static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
1f103105
RZ		 443{
444 struct uli526x_board_info *db = dev->priv;
445 struct tx_desc *txptr;
446 unsigned int len = length;
447 /* Too large packet check */
448 if (len > MAX_PACKET_SIZE) {
449 printf(": big packet = %d\n", len);
450 return 0;
451 }
452
453 /* No Tx resource check, it never happen nromally */
454 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
455 printf("No Tx resource %ld\n", db->tx_packet_cnt);
456 return 0;
457 }
458
459 /* Disable NIC interrupt */
460 outl(0, dev->iobase + DCR7);
461
462 /* transmit this packet */
463 txptr = db->tx_insert_ptr;
464 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
465 txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
466
467 /* Point to next transmit free descriptor */
468 db->tx_insert_ptr = txptr->next_tx_desc;
469
470 /* Transmit Packet Process */
471 if ((db->tx_packet_cnt < TX_DESC_CNT)) {
472 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
473 db->tx_packet_cnt++; /* Ready to send */
474 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
475 }
476
477 /* Got ULI526X status */
478 db->cr5_data = inl(db->ioaddr + DCR5);
479 outl(db->cr5_data, db->ioaddr + DCR5);
480
481#ifdef TX_DEBUG
482 printf("%s(): length = 0x%x\n", __FUNCTION__, length);
483 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
484#endif
485
486 outl(db->cr7_data, dev->iobase + DCR7);
487 uli526x_free_tx_pkt(dev, db);
488
489 return length;
490}
491
492/*
493 * Free TX resource after TX complete
494 */
495
496static void uli526x_free_tx_pkt(struct eth_device *dev,
497 struct uli526x_board_info *db)
498{
499 struct tx_desc *txptr;
500 u32 tdes0;
501
502 txptr = db->tx_remove_ptr;
503 while (db->tx_packet_cnt) {
504 tdes0 = le32_to_cpu(txptr->tdes0);
505 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
506 if (tdes0 & 0x80000000)
507 break;
508
509 /* A packet sent completed */
510 db->tx_packet_cnt--;
511
512 if (tdes0 != 0x7fffffff) {
513#ifdef TX_DEBUG
514 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
515#endif
516 if (tdes0 & TDES0_ERR_MASK) {
517 if (tdes0 & 0x0002) { /* UnderRun */
518 if (!(db->cr6_data & CR6_SFT)) {
519 db->cr6_data = db->cr6_data |
520 CR6_SFT;
521 update_cr6(db->cr6_data,
522 db->ioaddr);
523 }
524 }
525 }
526 }
527
528 txptr = txptr->next_tx_desc;
529 }/* End of while */
530
531 /* Update TX remove pointer to next */
532 db->tx_remove_ptr = txptr;
533}
534
535
536/*
537 * Receive the come packet and pass to upper layer
538 */
539
540static int uli526x_rx_packet(struct eth_device *dev)
541{
542 struct uli526x_board_info *db = dev->priv;
543 struct rx_desc *rxptr;
544 int rxlen = 0;
545 u32 rdes0;
546
547 rxptr = db->rx_ready_ptr;
548
549 rdes0 = le32_to_cpu(rxptr->rdes0);
550#ifdef RX_DEBUG
551 printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
552#endif
553 if (!(rdes0 & 0x80000000)) { /* packet owner check */
554 if ((rdes0 & 0x300) != 0x300) {
555 /* A packet without First/Last flag */
556 /* reuse this buf */
557 printf("A packet without First/Last flag");
558 uli526x_reuse_buf(rxptr);
559 } else {
560 /* A packet with First/Last flag */
561 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
562#ifdef RX_DEBUG
563 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
564#endif
565 /* error summary bit check */
566 if (rdes0 & 0x8000) {
567 /* This is a error packet */
9b55a253 568 printf("Error: rdes0: %x\n", rdes0);
1f103105
RZ		 569 }
570
571 if (!(rdes0 & 0x8000) ||
572 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
573
574#ifdef RX_DEBUG
575 printf("%s(): rx_skb_ptr =%x\n",
576 __FUNCTION__, rxptr->rx_buf_ptr);
577 printf("%s(): rxlen =%x\n",
578 __FUNCTION__, rxlen);
579
580 printf("%s(): buf addr =%x\n",
581 __FUNCTION__, rxptr->rx_buf_ptr);
582 printf("%s(): rxlen =%x\n",
583 __FUNCTION__, rxlen);
584 int i;
585 for (i = 0; i < 0x20; i++)
586 printf("%s(): data[%x] =%x\n",
587 __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
588#endif
589
e845e07e 590 NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen);
1f103105
RZ		 591 uli526x_reuse_buf(rxptr);
592
593 } else {
594 /* Reuse SKB buffer when the packet is error */
595 printf("Reuse buffer, rdes0");
596 uli526x_reuse_buf(rxptr);
597 }
598 }
599
600 rxptr = rxptr->next_rx_desc;
601 }
602
603 db->rx_ready_ptr = rxptr;
604 return rxlen;
605}
606
607/*
608 * Reuse the RX buffer
609 */
610
611static void uli526x_reuse_buf(struct rx_desc *rxptr)
612{
613
614 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
615 rxptr->rdes0 = cpu_to_le32(0x80000000);
616 else
617 printf("Buffer reuse method error");
618}
619/*
620 * Initialize transmit/Receive descriptor
621 * Using Chain structure, and allocate Tx/Rx buffer
622 */
623
624static void uli526x_descriptor_init(struct uli526x_board_info *db,
625 unsigned long ioaddr)
626{
627 struct tx_desc *tmp_tx;
628 struct rx_desc *tmp_rx;
629 unsigned char *tmp_buf;
630 dma_addr_t tmp_tx_dma, tmp_rx_dma;
631 dma_addr_t tmp_buf_dma;
632 int i;
633 /* tx descriptor start pointer */
634 db->tx_insert_ptr = db->first_tx_desc;
635 db->tx_remove_ptr = db->first_tx_desc;
636
637 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
638
639 /* rx descriptor start pointer */
640 db->first_rx_desc = (void *)db->first_tx_desc +
641 sizeof(struct tx_desc) * TX_DESC_CNT;
642 db->first_rx_desc_dma = db->first_tx_desc_dma +
643 sizeof(struct tx_desc) * TX_DESC_CNT;
644 db->rx_ready_ptr = db->first_rx_desc;
645 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
646#ifdef DEBUG
647 printf("%s(): db->first_tx_desc= 0x%x\n",
648 __FUNCTION__, db->first_tx_desc);
649 printf("%s(): db->first_rx_desc_dma= 0x%x\n",
650 __FUNCTION__, db->first_rx_desc_dma);
651#endif
652 /* Init Transmit chain */
653 tmp_buf = db->buf_pool_start;
654 tmp_buf_dma = db->buf_pool_dma_start;
655 tmp_tx_dma = db->first_tx_desc_dma;
656 for (tmp_tx = db->first_tx_desc, i = 0;
657 i < TX_DESC_CNT; i++, tmp_tx++) {
e845e07e 658 tmp_tx->tx_buf_ptr = (char *)tmp_buf;
1f103105
RZ		 659 tmp_tx->tdes0 = cpu_to_le32(0);
660 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
661 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
662 tmp_tx_dma += sizeof(struct tx_desc);
663 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
664 tmp_tx->next_tx_desc = tmp_tx + 1;
665 tmp_buf = tmp_buf + TX_BUF_ALLOC;
666 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
667 }
668 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
669 tmp_tx->next_tx_desc = db->first_tx_desc;
670
671 /* Init Receive descriptor chain */
672 tmp_rx_dma = db->first_rx_desc_dma;
673 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
674 i++, tmp_rx++) {
675 tmp_rx->rdes0 = cpu_to_le32(0);
676 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
677 tmp_rx_dma += sizeof(struct rx_desc);
678 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
679 tmp_rx->next_rx_desc = tmp_rx + 1;
680 }
681 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
682 tmp_rx->next_rx_desc = db->first_rx_desc;
683
684 /* pre-allocate Rx buffer */
685 allocate_rx_buffer(db);
686}
687
688/*
689 * Update CR6 value
690 * Firstly stop ULI526X, then written value and start
691 */
692
693static void update_cr6(u32 cr6_data, unsigned long ioaddr)
694{
695
696 outl(cr6_data, ioaddr + DCR6);
697 udelay(5);
698}
699
700/*
701 * Allocate rx buffer,
702 */
703
704static void allocate_rx_buffer(struct uli526x_board_info *db)
705{
706 int index;
707 struct rx_desc *rxptr;
708 rxptr = db->first_rx_desc;
709 u32 addr;
710
711 for (index = 0; index < RX_DESC_CNT; index++) {
712 addr = (u32)NetRxPackets[index];
713 addr += (16 - (addr & 15));
714 rxptr->rx_buf_ptr = (char *) addr;
715 rxptr->rdes2 = cpu_to_le32(addr);
716 rxptr->rdes0 = cpu_to_le32(0x80000000);
717#ifdef DEBUG
718 printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
719 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
720 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
721 printf("%s(): rxptr buf address = 0x%x\n", \
722 __FUNCTION__, rxptr->rx_buf_ptr);
723 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
724#endif
725 rxptr = rxptr->next_rx_desc;
726 }
727}
728
729/*
730 * Read one word data from the serial ROM
731 */
732
733static u16 read_srom_word(long ioaddr, int offset)
734{
735 int i;
736 u16 srom_data = 0;
737 long cr9_ioaddr = ioaddr + DCR9;
738
739 outl(CR9_SROM_READ, cr9_ioaddr);
740 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
741
742 /* Send the Read Command 110b */
743 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
744 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
745 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
746
747 /* Send the offset */
748 for (i = 5; i >= 0; i--) {
749 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
750 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
751 }
752
753 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
754
755 for (i = 16; i > 0; i--) {
756 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
757 udelay(5);
758 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
759 ? 1 : 0);
760 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
761 udelay(5);
762 }
763
764 outl(CR9_SROM_READ, cr9_ioaddr);
765 return srom_data;
766}
767
768/*
769 * Set 10/100 phyxcer capability
770 * AUTO mode : phyxcer register4 is NIC capability
771 * Force mode: phyxcer register4 is the force media
772 */
773
774static void uli526x_set_phyxcer(struct uli526x_board_info *db)
775{
776 u16 phy_reg;
777
778 /* Phyxcer capability setting */
09c04c20
AF		 779 phy_reg = uli_phy_read(db->ioaddr,
780 db->phy_addr, 4, db->chip_id) & ~0x01e0;
1f103105
RZ		 781
782 if (db->media_mode & ULI526X_AUTO) {
783 /* AUTO Mode */
784 phy_reg |= db->PHY_reg4;
785 } else {
786 /* Force Mode */
787 switch (db->media_mode) {
788 case ULI526X_10MHF: phy_reg |= 0x20; break;
789 case ULI526X_10MFD: phy_reg |= 0x40; break;
790 case ULI526X_100MHF: phy_reg |= 0x80; break;
791 case ULI526X_100MFD: phy_reg |= 0x100; break;
792 }
793
794 }
795
796 /* Write new capability to Phyxcer Reg4 */
797 if (!(phy_reg & 0x01e0)) {
798 phy_reg |= db->PHY_reg4;
799 db->media_mode |= ULI526X_AUTO;
800 }
09c04c20 801 uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1f103105
RZ		 802
803 /* Restart Auto-Negotiation */
09c04c20 804 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1f103105
RZ		 805 udelay(50);
806}
807
808/*
809 * Write a word to Phy register
810 */
811
09c04c20 812static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1f103105
RZ		 813 u16 phy_data, u32 chip_id)
814{
815 u16 i;
816 unsigned long ioaddr;
817
818 if (chip_id == PCI_ULI5263_ID) {
819 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
820 return;
821 }
822 /* M5261/M5263 Chip */
823 ioaddr = iobase + DCR9;
824
825 /* Send 33 synchronization clock to Phy controller */
826 for (i = 0; i < 35; i++)
827 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
828
829 /* Send start command(01) to Phy */
830 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
831 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
832
833 /* Send write command(01) to Phy */
834 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
835 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
836
837 /* Send Phy address */
838 for (i = 0x10; i > 0; i = i >> 1)
839 phy_write_1bit(ioaddr, phy_addr & i ?
840 PHY_DATA_1 : PHY_DATA_0, chip_id);
841
842 /* Send register address */
843 for (i = 0x10; i > 0; i = i >> 1)
844 phy_write_1bit(ioaddr, offset & i ?
845 PHY_DATA_1 : PHY_DATA_0, chip_id);
846
847 /* written trasnition */
848 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
849 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
850
851 /* Write a word data to PHY controller */
852 for (i = 0x8000; i > 0; i >>= 1)
853 phy_write_1bit(ioaddr, phy_data & i ?
854 PHY_DATA_1 : PHY_DATA_0, chip_id);
855}
856
857/*
858 * Read a word data from phy register
859 */
860
09c04c20
AF		 861static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
862 u32 chip_id)
1f103105
RZ		 863{
864 int i;
865 u16 phy_data;
866 unsigned long ioaddr;
867
868 if (chip_id == PCI_ULI5263_ID)
869 return phy_readby_cr10(iobase, phy_addr, offset);
870 /* M5261/M5263 Chip */
871 ioaddr = iobase + DCR9;
872
873 /* Send 33 synchronization clock to Phy controller */
874 for (i = 0; i < 35; i++)
875 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
876
877 /* Send start command(01) to Phy */
878 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
879 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
880
881 /* Send read command(10) to Phy */
882 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
883 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
884
885 /* Send Phy address */
886 for (i = 0x10; i > 0; i = i >> 1)
887 phy_write_1bit(ioaddr, phy_addr & i ?
888 PHY_DATA_1 : PHY_DATA_0, chip_id);
889
890 /* Send register address */
891 for (i = 0x10; i > 0; i = i >> 1)
892 phy_write_1bit(ioaddr, offset & i ?
893 PHY_DATA_1 : PHY_DATA_0, chip_id);
894
895 /* Skip transition state */
896 phy_read_1bit(ioaddr, chip_id);
897
898 /* read 16bit data */
899 for (phy_data = 0, i = 0; i < 16; i++) {
900 phy_data <<= 1;
901 phy_data |= phy_read_1bit(ioaddr, chip_id);
902 }
903
904 return phy_data;
905}
906
907static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
908{
909 unsigned long ioaddr, cr10_value;
910
911 ioaddr = iobase + DCR10;
912 cr10_value = phy_addr;
913 cr10_value = (cr10_value<<5) + offset;
914 cr10_value = (cr10_value<<16) + 0x08000000;
915 outl(cr10_value, ioaddr);
916 udelay(1);
917 while (1) {
918 cr10_value = inl(ioaddr);
919 if (cr10_value & 0x10000000)
920 break;
921 }
922 return (cr10_value&0x0ffff);
923}
924
925static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
926 u8 offset, u16 phy_data)
927{
928 unsigned long ioaddr, cr10_value;
929
930 ioaddr = iobase + DCR10;
931 cr10_value = phy_addr;
932 cr10_value = (cr10_value<<5) + offset;
933 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
934 outl(cr10_value, ioaddr);
935 udelay(1);
936}
937/*
938 * Write one bit data to Phy Controller
939 */
940
941static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
942{
943 outl(phy_data , ioaddr); /* MII Clock Low */
944 udelay(1);
945 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
946 udelay(1);
947 outl(phy_data , ioaddr); /* MII Clock Low */
948 udelay(1);
949}
950
951/*
952 * Read one bit phy data from PHY controller
953 */
954
955static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
956{
957 u16 phy_data;
958
959 outl(0x50000 , ioaddr);
960 udelay(1);
961 phy_data = (inl(ioaddr) >> 19) & 0x1;
962 outl(0x40000 , ioaddr);
963 udelay(1);
964
965 return phy_data;
966}
967
968/*
969 * Set MAC address to ID Table
970 */
971
972static void set_mac_addr(struct eth_device *dev)
973{
974 int i;
975 u16 addr;
976 struct uli526x_board_info *db = dev->priv;
977 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
978 /* Reset dianostic pointer port */
979 outl(0x1c0, db->ioaddr + DCR13);
980 outl(0, db->ioaddr + DCR14); /* Clear reset port */
981 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
982 outl(0, db->ioaddr + DCR14); /* Clear reset port */
983 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
984 /* Select ID Table access port */
985 outl(0x1b0, db->ioaddr + DCR13);
986 /* Read MAC address from CR14 */
987 for (i = 0; i < 3; i++) {
988 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
989 outl(addr, db->ioaddr + DCR14);
990 }
991 /* write end */
992 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
993 outl(0, db->ioaddr + DCR0); /* Clear CR0 */
994 udelay(10);
995 return;
996}
"Das U-Boot" Source Tree