[people/ms/u-boot.git] / drivers / net / xilinx_emaclite.c

/*
 * (C) Copyright 2007-2009 Michal Simek
 * (C) Copyright 2003 Xilinx Inc.
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <malloc.h>
#include <asm/io.h>
#include <fdtdec.h>

DECLARE_GLOBAL_DATA_PTR;

#undef DEBUG

#define ENET_ADDR_LENGTH	6

/* EmacLite constants */
#define XEL_BUFFER_OFFSET	0x0800	/* Next buffer's offset */
#define XEL_TPLR_OFFSET		0x07F4	/* Tx packet length */
#define XEL_TSR_OFFSET		0x07FC	/* Tx status */
#define XEL_RSR_OFFSET		0x17FC	/* Rx status */
#define XEL_RXBUFF_OFFSET	0x1000	/* Receive Buffer */

/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK	0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK		0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL

/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK		0x00000008UL

struct xemaclite {
	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
	u32 txpp;		/* TX ping pong buffer */
	u32 rxpp;		/* RX ping pong buffer */
};

static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;

	/* Word aligned buffer, no correction needed. */
	to32ptr = (u32 *) destptr;
	while (bytecount > 3) {
		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}
	to8ptr = (u8 *) to32ptr;

	alignbuffer = *from32ptr++;
	from8ptr = (u8 *) &alignbuffer;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;
}

static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr = (u32 *) destptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;
	while (bytecount > 3) {

		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}

	alignbuffer = 0;
	to8ptr = (u8 *) &alignbuffer;
	from8ptr = (u8 *) from32ptr;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;

	*to32ptr++ = alignbuffer;
}

static void emaclite_halt(struct eth_device *dev)
{
	debug("eth_halt\n");
}

static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
	struct xemaclite *emaclite = dev->priv;
	debug("EmacLite Initialization Started\n");

/*
 * TX - TX_PING & TX_PONG initialization
 */
	/* Restart PING TX */
	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
	/* Copy MAC address */
	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
	/* Set the length */
	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
	/* Update the MAC address in the EMAC Lite */
	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
	/* Wait for EMAC Lite to finish with the MAC address update */
	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
		XEL_TSR_PROG_MAC_ADDR) != 0)
		;

	if (emaclite->txpp) {
		/* The same operation with PONG TX */
		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
		xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
			XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
		out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
		out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
			XEL_TSR_PROG_MAC_ADDR);
		while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
			XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
			;
	}

/*
 * RX - RX_PING & RX_PONG initialization
 */
	/* Write out the value to flush the RX buffer */
	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);

	if (emaclite->rxpp)
		out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
			XEL_RSR_RECV_IE_MASK);

	debug("EmacLite Initialization complete\n");
	return 0;
}

static int xemaclite_txbufferavailable(struct eth_device *dev)
{
	u32 reg;
	u32 txpingbusy;
	u32 txpongbusy;
	struct xemaclite *emaclite = dev->priv;

	/*
	 * Read the other buffer register
	 * and determine if the other buffer is available
	 */
	reg = in_be32 (dev->iobase +
			emaclite->nexttxbuffertouse + 0);
	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
			XEL_TSR_XMIT_BUSY_MASK);

	reg = in_be32 (dev->iobase +
			(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
			XEL_TSR_XMIT_BUSY_MASK);

	return !(txpingbusy && txpongbusy);
}

static int emaclite_send(struct eth_device *dev, void *ptr, int len)
{
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	u32 maxtry = 1000;

	if (len > PKTSIZE)
		len = PKTSIZE;

	while (!xemaclite_txbufferavailable(dev) && maxtry) {
		udelay(10);
		maxtry--;
	}

	if (!maxtry) {
		printf("Error: Timeout waiting for ethernet TX buffer\n");
		/* Restart PING TX */
		out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
		if (emaclite->txpp) {
			out_be32 (dev->iobase + XEL_TSR_OFFSET +
				XEL_BUFFER_OFFSET, 0);
		}
		return -1;
	}

	/* Determine the expected TX buffer address */
	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);

	/* Determine if the expected buffer address is empty */
	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {

		if (emaclite->txpp)
			emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;

		debug("Send packet from 0x%x\n", baseaddress);
		/* Write the frame to the buffer */
		xemaclite_alignedwrite(ptr, baseaddress, len);
		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		reg |= XEL_TSR_XMIT_BUSY_MASK;
		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
		return 0;
	}

	if (emaclite->txpp) {
		/* Switch to second buffer */
		baseaddress ^= XEL_BUFFER_OFFSET;
		/* Determine if the expected buffer address is empty */
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
			&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
				& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
			debug("Send packet from 0x%x\n", baseaddress);
			/* Write the frame to the buffer */
			xemaclite_alignedwrite(ptr, baseaddress, len);
			out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
				(XEL_TPLR_LENGTH_MASK_HI |
					XEL_TPLR_LENGTH_MASK_LO)));
			reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
			reg |= XEL_TSR_XMIT_BUSY_MASK;
			if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
				reg |= XEL_TSR_XMIT_ACTIVE_MASK;
			out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
			return 0;
		}
	}

	puts("Error while sending frame\n");
	return -1;
}

static int emaclite_recv(struct eth_device *dev)
{
	u32 length;
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	debug("Testing data at address 0x%x\n", baseaddress);
	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
		if (emaclite->rxpp)
			emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
	} else {

		if (!emaclite->rxpp) {
			debug("No data was available - address 0x%x\n",
								baseaddress);
			return 0;
		} else {
			baseaddress ^= XEL_BUFFER_OFFSET;
			reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
			if ((reg & XEL_RSR_RECV_DONE_MASK) !=
						XEL_RSR_RECV_DONE_MASK) {
				debug("No data was available - address 0x%x\n",
						baseaddress);
				return 0;
			}
		}
	}
	/* Get the length of the frame that arrived */
	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
			0xFFFF0000 ) >> 16) {
		case 0x806:
			length = 42 + 20; /* FIXME size of ARP */
			debug("ARP Packet\n");
			break;
		case 0x800:
			length = 14 + 14 +
			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
						0x10))) & 0xFFFF0000) >> 16);
			/* FIXME size of IP packet */
			debug ("IP Packet\n");
			break;
		default:
			debug("Other Packet\n");
			length = PKTSIZE;
			break;
	}

	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
			etherrxbuff, length);

	/* Acknowledge the frame */
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	reg &= ~XEL_RSR_RECV_DONE_MASK;
	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);

	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
	NetReceive((uchar *) etherrxbuff, length);
	return length;

}

int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
							int txpp, int rxpp)
{
	struct eth_device *dev;
	struct xemaclite *emaclite;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	emaclite = calloc(1, sizeof(struct xemaclite));
	if (emaclite == NULL) {
		free(dev);
		return -1;
	}

	dev->priv = emaclite;

	emaclite->txpp = txpp;
	emaclite->rxpp = rxpp;

	sprintf(dev->name, "Xelite.%lx", base_addr);

	dev->iobase = base_addr;
	dev->init = emaclite_init;
	dev->halt = emaclite_halt;
	dev->send = emaclite_send;
	dev->recv = emaclite_recv;

	eth_register(dev);

	return 1;
}

#ifdef CONFIG_OF_CONTROL
int xilinx_emaclite_init(bd_t *bis)
{
	int offset = 0;
	u32 ret = 0;
	u32 reg;

	do {
		offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
					"xlnx,xps-ethernetlite-1.00.a");
		if (offset != -1) {
			reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
			if (reg != FDT_ADDR_T_NONE) {
				u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
							"xlnx,rx-ping-pong", 0);
				u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
							"xlnx,tx-ping-pong", 0);
				ret |= xilinx_emaclite_initialize(bis, reg,
								txpp, rxpp);
			}
		}
	} while (offset != -1);

	return ret;
}
#endif
Commit	Line	Data
78d19a39 MS	1	/*
	2	* (C) Copyright 2007-2009 Michal Simek
	3	* (C) Copyright 2003 Xilinx Inc.
89c53891	4	*
89c53891 MS	5	* Michal SIMEK <monstr@monstr.eu>
89c53891 MS	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
78d19a39	8	*/
89c53891 MS	9
	10	#include <common.h>
	11	#include <net.h>
	12	#include <config.h>
042272a6	13	#include <malloc.h>
89c53891	14	#include <asm/io.h>
7fd70820 MS	15	#include <fdtdec.h>
	16
	17	DECLARE_GLOBAL_DATA_PTR;
89c53891 MS	18
	19	#undef DEBUG
	20
89c53891 MS	21	#define ENET_ADDR_LENGTH 6
	22
	23	/* EmacLite constants */
	24	#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
	25	#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
	26	#define XEL_TSR_OFFSET 0x07FC /* Tx status */
	27	#define XEL_RSR_OFFSET 0x17FC /* Rx status */
	28	#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
	29
	30	/* Xmit complete */
	31	#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
	32	/* Xmit interrupt enable bit */
	33	#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
	34	/* Buffer is active, SW bit only */
	35	#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
	36	/* Program the MAC address */
	37	#define XEL_TSR_PROGRAM_MASK 0x00000002UL
	38	/* define for programming the MAC address into the EMAC Lite */
	39	#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)
	40
	41	/* Transmit packet length upper byte */
	42	#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
	43	/* Transmit packet length lower byte */
	44	#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
	45
	46	/* Recv complete */
	47	#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
	48	/* Recv interrupt enable bit */
	49	#define XEL_RSR_RECV_IE_MASK 0x00000008UL
	50
773cfa8d	51	struct xemaclite {
042272a6 MS	52	u32 nexttxbuffertouse; /* Next TX buffer to write to */
042272a6 MS	53	u32 nextrxbuffertouse; /* Next RX buffer to read from */
947324b9 MS	54	u32 txpp; /* TX ping pong buffer */
947324b9 MS	55	u32 rxpp; /* RX ping pong buffer */
773cfa8d	56	};
89c53891	57
f2a7806f	58	static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
89c53891	59
5ac83801	60	static void xemaclite_alignedread(u32 srcptr, void destptr, u32 bytecount)
89c53891	61	{
042272a6	62	u32 i;
89c53891 MS	63	u32 alignbuffer;
	64	u32 *to32ptr;
	65	u32 *from32ptr;
	66	u8 *to8ptr;
	67	u8 *from8ptr;
	68
	69	from32ptr = (u32 *) srcptr;
	70
	71	/* Word aligned buffer, no correction needed. */
	72	to32ptr = (u32 *) destptr;
	73	while (bytecount > 3) {
	74	to32ptr++ = from32ptr++;
	75	bytecount -= 4;
	76	}
	77	to8ptr = (u8 *) to32ptr;
	78
	79	alignbuffer = *from32ptr++;
5ac83801	80	from8ptr = (u8 *) &alignbuffer;
89c53891	81
5ac83801	82	for (i = 0; i < bytecount; i++)
89c53891	83	to8ptr++ = from8ptr++;
89c53891 MS	84	}
89c53891 MS	85
5ac83801	86	static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
89c53891	87	{
042272a6	88	u32 i;
89c53891 MS	89	u32 alignbuffer;
	90	u32 to32ptr = (u32 ) destptr;
	91	u32 *from32ptr;
	92	u8 *to8ptr;
	93	u8 *from8ptr;
	94
	95	from32ptr = (u32 *) srcptr;
	96	while (bytecount > 3) {
	97
	98	to32ptr++ = from32ptr++;
	99	bytecount -= 4;
	100	}
	101
	102	alignbuffer = 0;
5ac83801	103	to8ptr = (u8 *) &alignbuffer;
89c53891 MS	104	from8ptr = (u8 *) from32ptr;
89c53891 MS	105
5ac83801	106	for (i = 0; i < bytecount; i++)
89c53891	107	to8ptr++ = from8ptr++;
89c53891 MS	108
	109	*to32ptr++ = alignbuffer;
	110	}
	111
042272a6	112	static void emaclite_halt(struct eth_device *dev)
89c53891	113	{
5ac83801	114	debug("eth_halt\n");
89c53891 MS	115	}
89c53891 MS	116
042272a6	117	static int emaclite_init(struct eth_device dev, bd_t bis)
89c53891	118	{
947324b9	119	struct xemaclite *emaclite = dev->priv;
5ac83801	120	debug("EmacLite Initialization Started\n");
89c53891 MS	121
	122	/*
	123	* TX - TX_PING & TX_PONG initialization
	124	*/
	125	/* Restart PING TX */
8d95ddbb	126	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
89c53891	127	/* Copy MAC address */
5ac83801	128	xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
89c53891	129	/* Set the length */
8d95ddbb	130	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
89c53891	131	/* Update the MAC address in the EMAC Lite */
8d95ddbb	132	out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
89c53891	133	/* Wait for EMAC Lite to finish with the MAC address update */
8d95ddbb MS	134	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
	135	XEL_TSR_PROG_MAC_ADDR) != 0)
	136	;
89c53891	137
947324b9 MS	138	if (emaclite->txpp) {
	139	/* The same operation with PONG TX */
	140	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
	141	xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
	142	XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
	143	out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
	144	out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
	145	XEL_TSR_PROG_MAC_ADDR);
	146	while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
	147	XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
	148	;
	149	}
89c53891 MS	150
	151	/*
	152	* RX - RX_PING & RX_PONG initialization
	153	*/
	154	/* Write out the value to flush the RX buffer */
8d95ddbb	155	out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
947324b9 MS	156
	157	if (emaclite->rxpp)
	158	out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
	159	XEL_RSR_RECV_IE_MASK);
89c53891	160
5ac83801	161	debug("EmacLite Initialization complete\n");
89c53891 MS	162	return 0;
	163	}
	164
773cfa8d	165	static int xemaclite_txbufferavailable(struct eth_device *dev)
89c53891 MS	166	{
	167	u32 reg;
	168	u32 txpingbusy;
	169	u32 txpongbusy;
773cfa8d MS	170	struct xemaclite *emaclite = dev->priv;
773cfa8d MS	171
89c53891 MS	172	/*
	173	* Read the other buffer register
	174	* and determine if the other buffer is available
	175	*/
773cfa8d MS	176	reg = in_be32 (dev->iobase +
773cfa8d MS	177	emaclite->nexttxbuffertouse + 0);
89c53891 MS	178	txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
	179	XEL_TSR_XMIT_BUSY_MASK);
	180
773cfa8d MS	181	reg = in_be32 (dev->iobase +
773cfa8d MS	182	(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
89c53891 MS	183	txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
	184	XEL_TSR_XMIT_BUSY_MASK);
	185
5ac83801	186	return !(txpingbusy && txpongbusy);
89c53891 MS	187	}
89c53891 MS	188
1ae6b9c4	189	static int emaclite_send(struct eth_device dev, void ptr, int len)
042272a6 MS	190	{
	191	u32 reg;
	192	u32 baseaddress;
773cfa8d	193	struct xemaclite *emaclite = dev->priv;
89c53891	194
042272a6	195	u32 maxtry = 1000;
89c53891	196
80439252 MS	197	if (len > PKTSIZE)
80439252 MS	198	len = PKTSIZE;
89c53891	199
773cfa8d	200	while (!xemaclite_txbufferavailable(dev) && maxtry) {
5ac83801	201	udelay(10);
89c53891 MS	202	maxtry--;
	203	}
	204
	205	if (!maxtry) {
5ac83801	206	printf("Error: Timeout waiting for ethernet TX buffer\n");
89c53891	207	/* Restart PING TX */
8d95ddbb	208	out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
947324b9 MS	209	if (emaclite->txpp) {
	210	out_be32 (dev->iobase + XEL_TSR_OFFSET +
	211	XEL_BUFFER_OFFSET, 0);
	212	}
95efa79d	213	return -1;
89c53891 MS	214	}
	215
	216	/* Determine the expected TX buffer address */
773cfa8d	217	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
89c53891 MS	218
	219	/* Determine if the expected buffer address is empty */
	220	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	221	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	222	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	223	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	224
947324b9 MS	225	if (emaclite->txpp)
	226	emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
	227
5ac83801	228	debug("Send packet from 0x%x\n", baseaddress);
89c53891	229	/* Write the frame to the buffer */
1ae6b9c4	230	xemaclite_alignedwrite(ptr, baseaddress, len);
89c53891 MS	231	out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
	232	(XEL_TPLR_LENGTH_MASK_HI \| XEL_TPLR_LENGTH_MASK_LO)));
	233	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	234	reg \|= XEL_TSR_XMIT_BUSY_MASK;
5ac83801	235	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
89c53891	236	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
89c53891	237	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
95efa79d	238	return 0;
89c53891	239	}
947324b9 MS	240
	241	if (emaclite->txpp) {
	242	/* Switch to second buffer */
	243	baseaddress ^= XEL_BUFFER_OFFSET;
	244	/* Determine if the expected buffer address is empty */
89c53891	245	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
947324b9 MS	246	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	247	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	248	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	249	debug("Send packet from 0x%x\n", baseaddress);
	250	/* Write the frame to the buffer */
1ae6b9c4	251	xemaclite_alignedwrite(ptr, baseaddress, len);
947324b9 MS	252	out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
	253	(XEL_TPLR_LENGTH_MASK_HI \|
	254	XEL_TPLR_LENGTH_MASK_LO)));
	255	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	256	reg \|= XEL_TSR_XMIT_BUSY_MASK;
	257	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
	258	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
	259	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
	260	return 0;
89c53891	261	}
89c53891	262	}
947324b9	263
5ac83801	264	puts("Error while sending frame\n");
95efa79d	265	return -1;
89c53891 MS	266	}
89c53891 MS	267
042272a6	268	static int emaclite_recv(struct eth_device *dev)
89c53891	269	{
042272a6 MS	270	u32 length;
	271	u32 reg;
	272	u32 baseaddress;
773cfa8d	273	struct xemaclite *emaclite = dev->priv;
89c53891	274
773cfa8d	275	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
89c53891	276	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
5ac83801	277	debug("Testing data at address 0x%x\n", baseaddress);
89c53891	278	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
947324b9 MS	279	if (emaclite->rxpp)
947324b9 MS	280	emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
89c53891	281	} else {
947324b9 MS	282
947324b9 MS	283	if (!emaclite->rxpp) {
5ac83801	284	debug("No data was available - address 0x%x\n",
947324b9	285	baseaddress);
89c53891	286	return 0;
947324b9 MS	287	} else {
	288	baseaddress ^= XEL_BUFFER_OFFSET;
	289	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	290	if ((reg & XEL_RSR_RECV_DONE_MASK) !=
	291	XEL_RSR_RECV_DONE_MASK) {
	292	debug("No data was available - address 0x%x\n",
	293	baseaddress);
	294	return 0;
	295	}
89c53891	296	}
89c53891 MS	297	}
89c53891 MS	298	/* Get the length of the frame that arrived */
3f91ec0f	299	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
89c53891 MS	300	0xFFFF0000 ) >> 16) {
	301	case 0x806:
	302	length = 42 + 20; /* FIXME size of ARP */
5ac83801	303	debug("ARP Packet\n");
89c53891 MS	304	break;
	305	case 0x800:
	306	length = 14 + 14 +
5ac83801 MS	307	(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
	308	0x10))) & 0xFFFF0000) >> 16);
	309	/* FIXME size of IP packet */
89c53891 MS	310	debug ("IP Packet\n");
	311	break;
	312	default:
80439252 MS	313	debug("Other Packet\n");
80439252 MS	314	length = PKTSIZE;
89c53891 MS	315	break;
	316	}
	317
5ac83801	318	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
89c53891 MS	319	etherrxbuff, length);
	320
	321	/* Acknowledge the frame */
	322	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	323	reg &= ~XEL_RSR_RECV_DONE_MASK;
	324	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
	325
5ac83801 MS	326	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
5ac83801 MS	327	NetReceive((uchar *) etherrxbuff, length);
95efa79d	328	return length;
89c53891 MS	329
89c53891 MS	330	}
042272a6	331
c1044a1e MS	332	int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
c1044a1e MS	333	int txpp, int rxpp)
042272a6 MS	334	{
042272a6 MS	335	struct eth_device *dev;
773cfa8d	336	struct xemaclite *emaclite;
042272a6	337
28ae02e5	338	dev = calloc(1, sizeof(*dev));
042272a6	339	if (dev == NULL)
95efa79d	340	return -1;
042272a6	341
773cfa8d MS	342	emaclite = calloc(1, sizeof(struct xemaclite));
	343	if (emaclite == NULL) {
	344	free(dev);
	345	return -1;
	346	}
	347
	348	dev->priv = emaclite;
	349
c1044a1e MS	350	emaclite->txpp = txpp;
c1044a1e MS	351	emaclite->rxpp = rxpp;
947324b9	352
9b94755a	353	sprintf(dev->name, "Xelite.%lx", base_addr);
042272a6 MS	354
042272a6 MS	355	dev->iobase = base_addr;
042272a6 MS	356	dev->init = emaclite_init;
	357	dev->halt = emaclite_halt;
	358	dev->send = emaclite_send;
	359	dev->recv = emaclite_recv;
	360
	361	eth_register(dev);
	362
95efa79d	363	return 1;
042272a6	364	}
7fd70820 MS	365
	366	#ifdef CONFIG_OF_CONTROL
	367	int xilinx_emaclite_init(bd_t *bis)
	368	{
	369	int offset = 0;
	370	u32 ret = 0;
	371	u32 reg;
	372
	373	do {
	374	offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
	375	"xlnx,xps-ethernetlite-1.00.a");
	376	if (offset != -1) {
	377	reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
	378	if (reg != FDT_ADDR_T_NONE) {
	379	u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
	380	"xlnx,rx-ping-pong", 0);
	381	u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
	382	"xlnx,tx-ping-pong", 0);
	383	ret \|= xilinx_emaclite_initialize(bis, reg,
	384	txpp, rxpp);
	385	}
	386	}
	387	} while (offset != -1);
	388
	389	return ret;
	390	}
	391	#endif