projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| af27382e TR |
1 | menuconfig PCI |
| 2 | bool "PCI support" | |
| 3 | default y if PPC || X86 | |
| 4 | help | |
| 5 | Enable support for PCI (Peripheral Interconnect Bus), a type of bus | |
| 6 | used on some devices to allow the CPU to communicate with its | |
| 7 | peripherals. | |
| 8 | ||
| 9 | if PCI | |
| ff3e077b SG |
10 | |
| 11 | config DM_PCI | |
| 12 | bool "Enable driver mode for PCI" | |
| 13 | depends on DM | |
| 14 | help | |
| 15 | Use driver model for PCI. Driver model is the new method for | |
| 16 | orgnising devices in U-Boot. For PCI, driver model keeps track of | |
| 17 | available PCI devices, allows scanning of PCI buses and provides | |
| 18 | device configuration support. | |
| 19 | ||
| 3ba5f74a SG |
20 | config DM_PCI_COMPAT |
| 21 | bool "Enable compatible functions for PCI" | |
| 22 | depends on DM_PCI | |
| 23 | help | |
| 24 | Enable compatibility functions for PCI so that old code can be used | |
| 25 | with CONFIG_DM_PCI enabled. This should be used as an interim | |
| 26 | measure when porting a board to use driver model for PCI. Once the | |
| 27 | board is fully supported, this option should be disabled. | |
| 28 | ||
| 537849aa SG |
29 | config PCI_SANDBOX |
| 30 | bool "Sandbox PCI support" | |
| 31 | depends on SANDBOX && DM_PCI | |
| 32 | help | |
| 33 | Support PCI on sandbox, as an emulated bus. This permits testing of | |
| 34 | PCI feature such as bus scanning, device configuration and device | |
| 35 | access. The available (emulated) devices are defined statically in | |
| 36 | the device tree but the normal PCI scan technique is used to find | |
| 37 | then. | |
| 38 | ||
| fde7e189 SG |
39 | config PCI_TEGRA |
| 40 | bool "Tegra PCI support" | |
| 41 | depends on TEGRA | |
| bbc5b36b | 42 | depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) |
| fde7e189 SG |
43 | help |
| 44 | Enable support for the PCIe controller found on some generations of | |
| 45 | Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has | |
| 46 | 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports | |
| 47 | with a total of 5 lanes. Some boards require this for Ethernet | |
| 48 | support to work (e.g. beaver, jetson-tk1). | |
| 49 | ||
| a29e45a9 PB |
50 | config PCI_XILINX |
| 51 | bool "Xilinx AXI Bridge for PCI Express" | |
| 52 | depends on DM_PCI | |
| 53 | help | |
| 54 | Enable support for the Xilinx AXI bridge for PCI express, an IP block | |
| 55 | which can be used on some generations of Xilinx FPGAs. | |
| 56 | ||
| af27382e | 57 | endif |