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ff3e077b SG |
1 | /* |
2 | * Copyright (c) 2014 Google, Inc | |
3 | * Written by Simon Glass <sjg@chromium.org> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <dm.h> | |
10 | #include <errno.h> | |
11 | #include <fdtdec.h> | |
12 | #include <inttypes.h> | |
13 | #include <pci.h> | |
21d1fe7e | 14 | #include <asm/io.h> |
ff3e077b SG |
15 | #include <dm/lists.h> |
16 | #include <dm/root.h> | |
17 | #include <dm/device-internal.h> | |
348b744b BM |
18 | #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) |
19 | #include <asm/fsp/fsp_support.h> | |
20 | #endif | |
5e23b8b4 | 21 | #include "pci_internal.h" |
ff3e077b SG |
22 | |
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
983c6ba2 SG |
25 | static int pci_get_bus(int busnum, struct udevice **busp) |
26 | { | |
27 | int ret; | |
28 | ||
29 | ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp); | |
30 | ||
31 | /* Since buses may not be numbered yet try a little harder with bus 0 */ | |
32 | if (ret == -ENODEV) { | |
33 | ret = uclass_first_device(UCLASS_PCI, busp); | |
34 | if (ret) | |
35 | return ret; | |
36 | else if (!*busp) | |
37 | return -ENODEV; | |
38 | ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp); | |
39 | } | |
40 | ||
41 | return ret; | |
42 | } | |
43 | ||
ff3e077b SG |
44 | struct pci_controller *pci_bus_to_hose(int busnum) |
45 | { | |
46 | struct udevice *bus; | |
47 | int ret; | |
48 | ||
983c6ba2 | 49 | ret = pci_get_bus(busnum, &bus); |
ff3e077b SG |
50 | if (ret) { |
51 | debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret); | |
52 | return NULL; | |
53 | } | |
983c6ba2 | 54 | |
ff3e077b SG |
55 | return dev_get_uclass_priv(bus); |
56 | } | |
57 | ||
9f60fb0d SG |
58 | struct udevice *pci_get_controller(struct udevice *dev) |
59 | { | |
60 | while (device_is_on_pci_bus(dev)) | |
61 | dev = dev->parent; | |
62 | ||
63 | return dev; | |
64 | } | |
65 | ||
21ccce1b | 66 | pci_dev_t dm_pci_get_bdf(struct udevice *dev) |
4b515e4f SG |
67 | { |
68 | struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); | |
69 | struct udevice *bus = dev->parent; | |
70 | ||
71 | return PCI_ADD_BUS(bus->seq, pplat->devfn); | |
72 | } | |
73 | ||
ff3e077b SG |
74 | /** |
75 | * pci_get_bus_max() - returns the bus number of the last active bus | |
76 | * | |
77 | * @return last bus number, or -1 if no active buses | |
78 | */ | |
79 | static int pci_get_bus_max(void) | |
80 | { | |
81 | struct udevice *bus; | |
82 | struct uclass *uc; | |
83 | int ret = -1; | |
84 | ||
85 | ret = uclass_get(UCLASS_PCI, &uc); | |
86 | uclass_foreach_dev(bus, uc) { | |
87 | if (bus->seq > ret) | |
88 | ret = bus->seq; | |
89 | } | |
90 | ||
91 | debug("%s: ret=%d\n", __func__, ret); | |
92 | ||
93 | return ret; | |
94 | } | |
95 | ||
96 | int pci_last_busno(void) | |
97 | { | |
069155cb | 98 | return pci_get_bus_max(); |
ff3e077b SG |
99 | } |
100 | ||
101 | int pci_get_ff(enum pci_size_t size) | |
102 | { | |
103 | switch (size) { | |
104 | case PCI_SIZE_8: | |
105 | return 0xff; | |
106 | case PCI_SIZE_16: | |
107 | return 0xffff; | |
108 | default: | |
109 | return 0xffffffff; | |
110 | } | |
111 | } | |
112 | ||
113 | int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, | |
114 | struct udevice **devp) | |
115 | { | |
116 | struct udevice *dev; | |
117 | ||
118 | for (device_find_first_child(bus, &dev); | |
119 | dev; | |
120 | device_find_next_child(&dev)) { | |
121 | struct pci_child_platdata *pplat; | |
122 | ||
123 | pplat = dev_get_parent_platdata(dev); | |
124 | if (pplat && pplat->devfn == find_devfn) { | |
125 | *devp = dev; | |
126 | return 0; | |
127 | } | |
128 | } | |
129 | ||
130 | return -ENODEV; | |
131 | } | |
132 | ||
f3f1faef | 133 | int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp) |
ff3e077b SG |
134 | { |
135 | struct udevice *bus; | |
136 | int ret; | |
137 | ||
983c6ba2 | 138 | ret = pci_get_bus(PCI_BUS(bdf), &bus); |
ff3e077b SG |
139 | if (ret) |
140 | return ret; | |
141 | return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp); | |
142 | } | |
143 | ||
144 | static int pci_device_matches_ids(struct udevice *dev, | |
145 | struct pci_device_id *ids) | |
146 | { | |
147 | struct pci_child_platdata *pplat; | |
148 | int i; | |
149 | ||
150 | pplat = dev_get_parent_platdata(dev); | |
151 | if (!pplat) | |
152 | return -EINVAL; | |
153 | for (i = 0; ids[i].vendor != 0; i++) { | |
154 | if (pplat->vendor == ids[i].vendor && | |
155 | pplat->device == ids[i].device) | |
156 | return i; | |
157 | } | |
158 | ||
159 | return -EINVAL; | |
160 | } | |
161 | ||
162 | int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, | |
163 | int *indexp, struct udevice **devp) | |
164 | { | |
165 | struct udevice *dev; | |
166 | ||
167 | /* Scan all devices on this bus */ | |
168 | for (device_find_first_child(bus, &dev); | |
169 | dev; | |
170 | device_find_next_child(&dev)) { | |
171 | if (pci_device_matches_ids(dev, ids) >= 0) { | |
172 | if ((*indexp)-- <= 0) { | |
173 | *devp = dev; | |
174 | return 0; | |
175 | } | |
176 | } | |
177 | } | |
178 | ||
179 | return -ENODEV; | |
180 | } | |
181 | ||
182 | int pci_find_device_id(struct pci_device_id *ids, int index, | |
183 | struct udevice **devp) | |
184 | { | |
185 | struct udevice *bus; | |
186 | ||
187 | /* Scan all known buses */ | |
188 | for (uclass_first_device(UCLASS_PCI, &bus); | |
189 | bus; | |
190 | uclass_next_device(&bus)) { | |
191 | if (!pci_bus_find_devices(bus, ids, &index, devp)) | |
192 | return 0; | |
193 | } | |
194 | *devp = NULL; | |
195 | ||
196 | return -ENODEV; | |
197 | } | |
198 | ||
5c0bf647 SG |
199 | static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor, |
200 | unsigned int device, int *indexp, | |
201 | struct udevice **devp) | |
202 | { | |
203 | struct pci_child_platdata *pplat; | |
204 | struct udevice *dev; | |
205 | ||
206 | for (device_find_first_child(bus, &dev); | |
207 | dev; | |
208 | device_find_next_child(&dev)) { | |
209 | pplat = dev_get_parent_platdata(dev); | |
210 | if (pplat->vendor == vendor && pplat->device == device) { | |
211 | if (!(*indexp)--) { | |
212 | *devp = dev; | |
213 | return 0; | |
214 | } | |
215 | } | |
216 | } | |
217 | ||
218 | return -ENODEV; | |
219 | } | |
220 | ||
221 | int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, | |
222 | struct udevice **devp) | |
223 | { | |
224 | struct udevice *bus; | |
225 | ||
226 | /* Scan all known buses */ | |
227 | for (uclass_first_device(UCLASS_PCI, &bus); | |
228 | bus; | |
229 | uclass_next_device(&bus)) { | |
230 | if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp)) | |
231 | return device_probe(*devp); | |
232 | } | |
233 | *devp = NULL; | |
234 | ||
235 | return -ENODEV; | |
236 | } | |
237 | ||
a0eb8356 SG |
238 | int dm_pci_find_class(uint find_class, int index, struct udevice **devp) |
239 | { | |
240 | struct udevice *dev; | |
241 | ||
242 | /* Scan all known buses */ | |
243 | for (pci_find_first_device(&dev); | |
244 | dev; | |
245 | pci_find_next_device(&dev)) { | |
246 | struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); | |
247 | ||
248 | if (pplat->class == find_class && !index--) { | |
249 | *devp = dev; | |
250 | return device_probe(*devp); | |
251 | } | |
252 | } | |
253 | *devp = NULL; | |
254 | ||
255 | return -ENODEV; | |
256 | } | |
257 | ||
ff3e077b SG |
258 | int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, |
259 | unsigned long value, enum pci_size_t size) | |
260 | { | |
261 | struct dm_pci_ops *ops; | |
262 | ||
263 | ops = pci_get_ops(bus); | |
264 | if (!ops->write_config) | |
265 | return -ENOSYS; | |
266 | return ops->write_config(bus, bdf, offset, value, size); | |
267 | } | |
268 | ||
269 | int pci_write_config(pci_dev_t bdf, int offset, unsigned long value, | |
270 | enum pci_size_t size) | |
271 | { | |
272 | struct udevice *bus; | |
273 | int ret; | |
274 | ||
983c6ba2 | 275 | ret = pci_get_bus(PCI_BUS(bdf), &bus); |
ff3e077b SG |
276 | if (ret) |
277 | return ret; | |
278 | ||
4d8615cb | 279 | return pci_bus_write_config(bus, bdf, offset, value, size); |
ff3e077b SG |
280 | } |
281 | ||
66afb4ed SG |
282 | int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, |
283 | enum pci_size_t size) | |
284 | { | |
285 | struct udevice *bus; | |
286 | ||
1e0f2263 | 287 | for (bus = dev; device_is_on_pci_bus(bus);) |
66afb4ed | 288 | bus = bus->parent; |
21ccce1b SG |
289 | return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value, |
290 | size); | |
66afb4ed SG |
291 | } |
292 | ||
293 | ||
ff3e077b SG |
294 | int pci_write_config32(pci_dev_t bdf, int offset, u32 value) |
295 | { | |
296 | return pci_write_config(bdf, offset, value, PCI_SIZE_32); | |
297 | } | |
298 | ||
299 | int pci_write_config16(pci_dev_t bdf, int offset, u16 value) | |
300 | { | |
301 | return pci_write_config(bdf, offset, value, PCI_SIZE_16); | |
302 | } | |
303 | ||
304 | int pci_write_config8(pci_dev_t bdf, int offset, u8 value) | |
305 | { | |
306 | return pci_write_config(bdf, offset, value, PCI_SIZE_8); | |
307 | } | |
308 | ||
66afb4ed SG |
309 | int dm_pci_write_config8(struct udevice *dev, int offset, u8 value) |
310 | { | |
311 | return dm_pci_write_config(dev, offset, value, PCI_SIZE_8); | |
312 | } | |
313 | ||
314 | int dm_pci_write_config16(struct udevice *dev, int offset, u16 value) | |
315 | { | |
316 | return dm_pci_write_config(dev, offset, value, PCI_SIZE_16); | |
317 | } | |
318 | ||
319 | int dm_pci_write_config32(struct udevice *dev, int offset, u32 value) | |
320 | { | |
321 | return dm_pci_write_config(dev, offset, value, PCI_SIZE_32); | |
322 | } | |
323 | ||
ff3e077b SG |
324 | int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, |
325 | unsigned long *valuep, enum pci_size_t size) | |
326 | { | |
327 | struct dm_pci_ops *ops; | |
328 | ||
329 | ops = pci_get_ops(bus); | |
330 | if (!ops->read_config) | |
331 | return -ENOSYS; | |
332 | return ops->read_config(bus, bdf, offset, valuep, size); | |
333 | } | |
334 | ||
335 | int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep, | |
336 | enum pci_size_t size) | |
337 | { | |
338 | struct udevice *bus; | |
339 | int ret; | |
340 | ||
983c6ba2 | 341 | ret = pci_get_bus(PCI_BUS(bdf), &bus); |
ff3e077b SG |
342 | if (ret) |
343 | return ret; | |
344 | ||
4d8615cb | 345 | return pci_bus_read_config(bus, bdf, offset, valuep, size); |
ff3e077b SG |
346 | } |
347 | ||
66afb4ed SG |
348 | int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, |
349 | enum pci_size_t size) | |
350 | { | |
351 | struct udevice *bus; | |
352 | ||
1e0f2263 | 353 | for (bus = dev; device_is_on_pci_bus(bus);) |
66afb4ed | 354 | bus = bus->parent; |
21ccce1b | 355 | return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep, |
66afb4ed SG |
356 | size); |
357 | } | |
358 | ||
ff3e077b SG |
359 | int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep) |
360 | { | |
361 | unsigned long value; | |
362 | int ret; | |
363 | ||
364 | ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32); | |
365 | if (ret) | |
366 | return ret; | |
367 | *valuep = value; | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep) | |
373 | { | |
374 | unsigned long value; | |
375 | int ret; | |
376 | ||
377 | ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16); | |
378 | if (ret) | |
379 | return ret; | |
380 | *valuep = value; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep) | |
386 | { | |
387 | unsigned long value; | |
388 | int ret; | |
389 | ||
390 | ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8); | |
391 | if (ret) | |
392 | return ret; | |
393 | *valuep = value; | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
66afb4ed SG |
398 | int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep) |
399 | { | |
400 | unsigned long value; | |
401 | int ret; | |
402 | ||
403 | ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8); | |
404 | if (ret) | |
405 | return ret; | |
406 | *valuep = value; | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep) | |
412 | { | |
413 | unsigned long value; | |
414 | int ret; | |
415 | ||
416 | ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16); | |
417 | if (ret) | |
418 | return ret; | |
419 | *valuep = value; | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep) | |
425 | { | |
426 | unsigned long value; | |
427 | int ret; | |
428 | ||
429 | ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32); | |
430 | if (ret) | |
431 | return ret; | |
432 | *valuep = value; | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
bbbcb526 BM |
437 | static void set_vga_bridge_bits(struct udevice *dev) |
438 | { | |
439 | struct udevice *parent = dev->parent; | |
440 | u16 bc; | |
441 | ||
442 | while (parent->seq != 0) { | |
443 | dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc); | |
444 | bc |= PCI_BRIDGE_CTL_VGA; | |
445 | dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc); | |
446 | parent = parent->parent; | |
447 | } | |
448 | } | |
449 | ||
ff3e077b SG |
450 | int pci_auto_config_devices(struct udevice *bus) |
451 | { | |
452 | struct pci_controller *hose = bus->uclass_priv; | |
bbbcb526 | 453 | struct pci_child_platdata *pplat; |
ff3e077b SG |
454 | unsigned int sub_bus; |
455 | struct udevice *dev; | |
456 | int ret; | |
457 | ||
458 | sub_bus = bus->seq; | |
459 | debug("%s: start\n", __func__); | |
460 | pciauto_config_init(hose); | |
461 | for (ret = device_find_first_child(bus, &dev); | |
462 | !ret && dev; | |
463 | ret = device_find_next_child(&dev)) { | |
ff3e077b | 464 | unsigned int max_bus; |
4d21455e | 465 | int ret; |
ff3e077b | 466 | |
ff3e077b | 467 | debug("%s: device %s\n", __func__, dev->name); |
5e23b8b4 | 468 | ret = dm_pciauto_config_device(dev); |
4d21455e SG |
469 | if (ret < 0) |
470 | return ret; | |
471 | max_bus = ret; | |
ff3e077b | 472 | sub_bus = max(sub_bus, max_bus); |
bbbcb526 BM |
473 | |
474 | pplat = dev_get_parent_platdata(dev); | |
475 | if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8)) | |
476 | set_vga_bridge_bits(dev); | |
ff3e077b SG |
477 | } |
478 | debug("%s: done\n", __func__); | |
479 | ||
480 | return sub_bus; | |
481 | } | |
482 | ||
5e23b8b4 | 483 | int dm_pci_hose_probe_bus(struct udevice *bus) |
ff3e077b | 484 | { |
ff3e077b SG |
485 | int sub_bus; |
486 | int ret; | |
487 | ||
488 | debug("%s\n", __func__); | |
ff3e077b SG |
489 | |
490 | sub_bus = pci_get_bus_max() + 1; | |
491 | debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name); | |
5e23b8b4 | 492 | dm_pciauto_prescan_setup_bridge(bus, sub_bus); |
ff3e077b SG |
493 | |
494 | ret = device_probe(bus); | |
495 | if (ret) { | |
3129ace4 | 496 | debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name, |
ff3e077b SG |
497 | ret); |
498 | return ret; | |
499 | } | |
500 | if (sub_bus != bus->seq) { | |
501 | printf("%s: Internal error, bus '%s' got seq %d, expected %d\n", | |
502 | __func__, bus->name, bus->seq, sub_bus); | |
503 | return -EPIPE; | |
504 | } | |
505 | sub_bus = pci_get_bus_max(); | |
5e23b8b4 | 506 | dm_pciauto_postscan_setup_bridge(bus, sub_bus); |
ff3e077b SG |
507 | |
508 | return sub_bus; | |
509 | } | |
510 | ||
aba92962 SG |
511 | /** |
512 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
513 | * PCI device id structure | |
514 | * @id: single PCI device id structure to match | |
515 | * @dev: the PCI device structure to match against | |
516 | * | |
517 | * Returns the matching pci_device_id structure or %NULL if there is no match. | |
518 | */ | |
519 | static bool pci_match_one_id(const struct pci_device_id *id, | |
520 | const struct pci_device_id *find) | |
521 | { | |
522 | if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) && | |
523 | (id->device == PCI_ANY_ID || id->device == find->device) && | |
524 | (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) && | |
525 | (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) && | |
526 | !((id->class ^ find->class) & id->class_mask)) | |
527 | return true; | |
528 | ||
529 | return false; | |
530 | } | |
531 | ||
532 | /** | |
533 | * pci_find_and_bind_driver() - Find and bind the right PCI driver | |
534 | * | |
535 | * This only looks at certain fields in the descriptor. | |
5dbcf3a0 SG |
536 | * |
537 | * @parent: Parent bus | |
538 | * @find_id: Specification of the driver to find | |
539 | * @bdf: Bus/device/function addreess - see PCI_BDF() | |
540 | * @devp: Returns a pointer to the device created | |
541 | * @return 0 if OK, -EPERM if the device is not needed before relocation and | |
542 | * therefore was not created, other -ve value on error | |
aba92962 SG |
543 | */ |
544 | static int pci_find_and_bind_driver(struct udevice *parent, | |
5dbcf3a0 SG |
545 | struct pci_device_id *find_id, |
546 | pci_dev_t bdf, struct udevice **devp) | |
aba92962 SG |
547 | { |
548 | struct pci_driver_entry *start, *entry; | |
549 | const char *drv; | |
550 | int n_ents; | |
551 | int ret; | |
552 | char name[30], *str; | |
08fc7b8f | 553 | bool bridge; |
aba92962 SG |
554 | |
555 | *devp = NULL; | |
556 | ||
557 | debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__, | |
558 | find_id->vendor, find_id->device); | |
559 | start = ll_entry_start(struct pci_driver_entry, pci_driver_entry); | |
560 | n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry); | |
561 | for (entry = start; entry != start + n_ents; entry++) { | |
562 | const struct pci_device_id *id; | |
563 | struct udevice *dev; | |
564 | const struct driver *drv; | |
565 | ||
566 | for (id = entry->match; | |
567 | id->vendor || id->subvendor || id->class_mask; | |
568 | id++) { | |
569 | if (!pci_match_one_id(id, find_id)) | |
570 | continue; | |
571 | ||
572 | drv = entry->driver; | |
08fc7b8f BM |
573 | |
574 | /* | |
575 | * In the pre-relocation phase, we only bind devices | |
576 | * whose driver has the DM_FLAG_PRE_RELOC set, to save | |
577 | * precious memory space as on some platforms as that | |
578 | * space is pretty limited (ie: using Cache As RAM). | |
579 | */ | |
580 | if (!(gd->flags & GD_FLG_RELOC) && | |
581 | !(drv->flags & DM_FLAG_PRE_RELOC)) | |
5dbcf3a0 | 582 | return -EPERM; |
08fc7b8f | 583 | |
aba92962 SG |
584 | /* |
585 | * We could pass the descriptor to the driver as | |
586 | * platdata (instead of NULL) and allow its bind() | |
587 | * method to return -ENOENT if it doesn't support this | |
588 | * device. That way we could continue the search to | |
589 | * find another driver. For now this doesn't seem | |
590 | * necesssary, so just bind the first match. | |
591 | */ | |
592 | ret = device_bind(parent, drv, drv->name, NULL, -1, | |
593 | &dev); | |
594 | if (ret) | |
595 | goto error; | |
596 | debug("%s: Match found: %s\n", __func__, drv->name); | |
597 | dev->driver_data = find_id->driver_data; | |
598 | *devp = dev; | |
599 | return 0; | |
600 | } | |
601 | } | |
602 | ||
08fc7b8f BM |
603 | bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI; |
604 | /* | |
605 | * In the pre-relocation phase, we only bind bridge devices to save | |
606 | * precious memory space as on some platforms as that space is pretty | |
607 | * limited (ie: using Cache As RAM). | |
608 | */ | |
609 | if (!(gd->flags & GD_FLG_RELOC) && !bridge) | |
5dbcf3a0 | 610 | return -EPERM; |
08fc7b8f | 611 | |
aba92962 | 612 | /* Bind a generic driver so that the device can be used */ |
4d8615cb BM |
613 | sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf), |
614 | PCI_FUNC(bdf)); | |
aba92962 SG |
615 | str = strdup(name); |
616 | if (!str) | |
617 | return -ENOMEM; | |
08fc7b8f BM |
618 | drv = bridge ? "pci_bridge_drv" : "pci_generic_drv"; |
619 | ||
aba92962 SG |
620 | ret = device_bind_driver(parent, drv, str, devp); |
621 | if (ret) { | |
3129ace4 | 622 | debug("%s: Failed to bind generic driver: %d\n", __func__, ret); |
aba92962 SG |
623 | return ret; |
624 | } | |
625 | debug("%s: No match found: bound generic driver instead\n", __func__); | |
626 | ||
627 | return 0; | |
628 | ||
629 | error: | |
630 | debug("%s: No match found: error %d\n", __func__, ret); | |
631 | return ret; | |
632 | } | |
633 | ||
ff3e077b SG |
634 | int pci_bind_bus_devices(struct udevice *bus) |
635 | { | |
636 | ulong vendor, device; | |
637 | ulong header_type; | |
4d8615cb | 638 | pci_dev_t bdf, end; |
ff3e077b SG |
639 | bool found_multi; |
640 | int ret; | |
641 | ||
642 | found_multi = false; | |
4d8615cb BM |
643 | end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1, |
644 | PCI_MAX_PCI_FUNCTIONS - 1); | |
645 | for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end; | |
646 | bdf += PCI_BDF(0, 0, 1)) { | |
ff3e077b SG |
647 | struct pci_child_platdata *pplat; |
648 | struct udevice *dev; | |
649 | ulong class; | |
650 | ||
4d8615cb | 651 | if (PCI_FUNC(bdf) && !found_multi) |
ff3e077b SG |
652 | continue; |
653 | /* Check only the first access, we don't expect problems */ | |
4d8615cb | 654 | ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, |
ff3e077b SG |
655 | &header_type, PCI_SIZE_8); |
656 | if (ret) | |
657 | goto error; | |
4d8615cb | 658 | pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, |
ff3e077b SG |
659 | PCI_SIZE_16); |
660 | if (vendor == 0xffff || vendor == 0x0000) | |
661 | continue; | |
662 | ||
4d8615cb | 663 | if (!PCI_FUNC(bdf)) |
ff3e077b SG |
664 | found_multi = header_type & 0x80; |
665 | ||
666 | debug("%s: bus %d/%s: found device %x, function %d\n", __func__, | |
4d8615cb BM |
667 | bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf)); |
668 | pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device, | |
ff3e077b | 669 | PCI_SIZE_16); |
4d8615cb | 670 | pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class, |
aba92962 SG |
671 | PCI_SIZE_32); |
672 | class >>= 8; | |
ff3e077b SG |
673 | |
674 | /* Find this device in the device tree */ | |
4d8615cb | 675 | ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev); |
ff3e077b | 676 | |
aba92962 SG |
677 | /* Search for a driver */ |
678 | ||
ff3e077b SG |
679 | /* If nothing in the device tree, bind a generic device */ |
680 | if (ret == -ENODEV) { | |
aba92962 SG |
681 | struct pci_device_id find_id; |
682 | ulong val; | |
683 | ||
684 | memset(&find_id, '\0', sizeof(find_id)); | |
685 | find_id.vendor = vendor; | |
686 | find_id.device = device; | |
687 | find_id.class = class; | |
688 | if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { | |
4d8615cb | 689 | pci_bus_read_config(bus, bdf, |
aba92962 SG |
690 | PCI_SUBSYSTEM_VENDOR_ID, |
691 | &val, PCI_SIZE_32); | |
692 | find_id.subvendor = val & 0xffff; | |
693 | find_id.subdevice = val >> 16; | |
694 | } | |
4d8615cb | 695 | ret = pci_find_and_bind_driver(bus, &find_id, bdf, |
aba92962 | 696 | &dev); |
ff3e077b | 697 | } |
5dbcf3a0 SG |
698 | if (ret == -EPERM) |
699 | continue; | |
700 | else if (ret) | |
ff3e077b SG |
701 | return ret; |
702 | ||
703 | /* Update the platform data */ | |
5dbcf3a0 SG |
704 | pplat = dev_get_parent_platdata(dev); |
705 | pplat->devfn = PCI_MASK_BUS(bdf); | |
706 | pplat->vendor = vendor; | |
707 | pplat->device = device; | |
708 | pplat->class = class; | |
ff3e077b SG |
709 | } |
710 | ||
711 | return 0; | |
712 | error: | |
713 | printf("Cannot read bus configuration: %d\n", ret); | |
714 | ||
715 | return ret; | |
716 | } | |
717 | ||
718 | static int pci_uclass_post_bind(struct udevice *bus) | |
719 | { | |
1887ed3a BM |
720 | /* |
721 | * If there is no pci device listed in the device tree, | |
722 | * don't bother scanning the device tree. | |
723 | */ | |
724 | if (bus->of_offset == -1) | |
725 | return 0; | |
726 | ||
ff3e077b SG |
727 | /* |
728 | * Scan the device tree for devices. This does not probe the PCI bus, | |
729 | * as this is not permitted while binding. It just finds devices | |
730 | * mentioned in the device tree. | |
731 | * | |
732 | * Before relocation, only bind devices marked for pre-relocation | |
733 | * use. | |
734 | */ | |
735 | return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, | |
736 | gd->flags & GD_FLG_RELOC ? false : true); | |
737 | } | |
738 | ||
739 | static int decode_regions(struct pci_controller *hose, const void *blob, | |
740 | int parent_node, int node) | |
741 | { | |
742 | int pci_addr_cells, addr_cells, size_cells; | |
2084c5af | 743 | phys_addr_t base = 0, size; |
ff3e077b SG |
744 | int cells_per_record; |
745 | const u32 *prop; | |
746 | int len; | |
747 | int i; | |
748 | ||
749 | prop = fdt_getprop(blob, node, "ranges", &len); | |
750 | if (!prop) | |
751 | return -EINVAL; | |
752 | pci_addr_cells = fdt_address_cells(blob, node); | |
753 | addr_cells = fdt_address_cells(blob, parent_node); | |
754 | size_cells = fdt_size_cells(blob, node); | |
755 | ||
756 | /* PCI addresses are always 3-cells */ | |
757 | len /= sizeof(u32); | |
758 | cells_per_record = pci_addr_cells + addr_cells + size_cells; | |
759 | hose->region_count = 0; | |
760 | debug("%s: len=%d, cells_per_record=%d\n", __func__, len, | |
761 | cells_per_record); | |
762 | for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) { | |
763 | u64 pci_addr, addr, size; | |
764 | int space_code; | |
765 | u32 flags; | |
766 | int type; | |
9526d83a | 767 | int pos; |
ff3e077b SG |
768 | |
769 | if (len < cells_per_record) | |
770 | break; | |
771 | flags = fdt32_to_cpu(prop[0]); | |
772 | space_code = (flags >> 24) & 3; | |
773 | pci_addr = fdtdec_get_number(prop + 1, 2); | |
774 | prop += pci_addr_cells; | |
775 | addr = fdtdec_get_number(prop, addr_cells); | |
776 | prop += addr_cells; | |
777 | size = fdtdec_get_number(prop, size_cells); | |
778 | prop += size_cells; | |
779 | debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64 | |
780 | ", size=%" PRIx64 ", space_code=%d\n", __func__, | |
781 | hose->region_count, pci_addr, addr, size, space_code); | |
782 | if (space_code & 2) { | |
783 | type = flags & (1U << 30) ? PCI_REGION_PREFETCH : | |
784 | PCI_REGION_MEM; | |
785 | } else if (space_code & 1) { | |
786 | type = PCI_REGION_IO; | |
787 | } else { | |
788 | continue; | |
789 | } | |
9526d83a SG |
790 | pos = -1; |
791 | for (i = 0; i < hose->region_count; i++) { | |
792 | if (hose->regions[i].flags == type) | |
793 | pos = i; | |
794 | } | |
795 | if (pos == -1) | |
796 | pos = hose->region_count++; | |
797 | debug(" - type=%d, pos=%d\n", type, pos); | |
798 | pci_set_region(hose->regions + pos, pci_addr, addr, size, type); | |
ff3e077b SG |
799 | } |
800 | ||
801 | /* Add a region for our local memory */ | |
2084c5af SG |
802 | size = gd->ram_size; |
803 | #ifdef CONFIG_SYS_SDRAM_BASE | |
804 | base = CONFIG_SYS_SDRAM_BASE; | |
805 | #endif | |
806 | if (gd->pci_ram_top && gd->pci_ram_top < base + size) | |
807 | size = gd->pci_ram_top - base; | |
808 | pci_set_region(hose->regions + hose->region_count++, base, base, | |
809 | size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); | |
ff3e077b SG |
810 | |
811 | return 0; | |
812 | } | |
813 | ||
814 | static int pci_uclass_pre_probe(struct udevice *bus) | |
815 | { | |
816 | struct pci_controller *hose; | |
817 | int ret; | |
818 | ||
819 | debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, | |
820 | bus->parent->name); | |
821 | hose = bus->uclass_priv; | |
822 | ||
823 | /* For bridges, use the top-level PCI controller */ | |
824 | if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) { | |
825 | hose->ctlr = bus; | |
826 | ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset, | |
827 | bus->of_offset); | |
828 | if (ret) { | |
829 | debug("%s: Cannot decode regions\n", __func__); | |
830 | return ret; | |
831 | } | |
832 | } else { | |
833 | struct pci_controller *parent_hose; | |
834 | ||
835 | parent_hose = dev_get_uclass_priv(bus->parent); | |
836 | hose->ctlr = parent_hose->bus; | |
837 | } | |
838 | hose->bus = bus; | |
839 | hose->first_busno = bus->seq; | |
840 | hose->last_busno = bus->seq; | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static int pci_uclass_post_probe(struct udevice *bus) | |
846 | { | |
847 | int ret; | |
848 | ||
ff3e077b SG |
849 | debug("%s: probing bus %d\n", __func__, bus->seq); |
850 | ret = pci_bind_bus_devices(bus); | |
851 | if (ret) | |
852 | return ret; | |
853 | ||
854 | #ifdef CONFIG_PCI_PNP | |
855 | ret = pci_auto_config_devices(bus); | |
4d21455e SG |
856 | if (ret < 0) |
857 | return ret; | |
ff3e077b SG |
858 | #endif |
859 | ||
348b744b BM |
860 | #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) |
861 | /* | |
862 | * Per Intel FSP specification, we should call FSP notify API to | |
863 | * inform FSP that PCI enumeration has been done so that FSP will | |
864 | * do any necessary initialization as required by the chipset's | |
865 | * BIOS Writer's Guide (BWG). | |
866 | * | |
867 | * Unfortunately we have to put this call here as with driver model, | |
868 | * the enumeration is all done on a lazy basis as needed, so until | |
869 | * something is touched on PCI it won't happen. | |
870 | * | |
871 | * Note we only call this 1) after U-Boot is relocated, and 2) | |
872 | * root bus has finished probing. | |
873 | */ | |
4d21455e | 874 | if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) { |
348b744b | 875 | ret = fsp_init_phase_pci(); |
4d21455e SG |
876 | if (ret) |
877 | return ret; | |
878 | } | |
348b744b BM |
879 | #endif |
880 | ||
4d21455e | 881 | return 0; |
ff3e077b SG |
882 | } |
883 | ||
884 | static int pci_uclass_child_post_bind(struct udevice *dev) | |
885 | { | |
886 | struct pci_child_platdata *pplat; | |
887 | struct fdt_pci_addr addr; | |
888 | int ret; | |
889 | ||
890 | if (dev->of_offset == -1) | |
891 | return 0; | |
892 | ||
893 | /* | |
894 | * We could read vendor, device, class if available. But for now we | |
895 | * just check the address. | |
896 | */ | |
897 | pplat = dev_get_parent_platdata(dev); | |
898 | ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, | |
899 | FDT_PCI_SPACE_CONFIG, "reg", &addr); | |
900 | ||
901 | if (ret) { | |
902 | if (ret != -ENOENT) | |
903 | return -EINVAL; | |
904 | } else { | |
dce54dd6 BM |
905 | /* extract the devfn from fdt_pci_addr */ |
906 | pplat->devfn = addr.phys_hi & 0xff00; | |
ff3e077b SG |
907 | } |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
4d8615cb BM |
912 | static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf, |
913 | uint offset, ulong *valuep, | |
914 | enum pci_size_t size) | |
ff3e077b SG |
915 | { |
916 | struct pci_controller *hose = bus->uclass_priv; | |
ff3e077b SG |
917 | |
918 | return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size); | |
919 | } | |
920 | ||
4d8615cb BM |
921 | static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf, |
922 | uint offset, ulong value, | |
923 | enum pci_size_t size) | |
ff3e077b SG |
924 | { |
925 | struct pci_controller *hose = bus->uclass_priv; | |
ff3e077b SG |
926 | |
927 | return pci_bus_write_config(hose->ctlr, bdf, offset, value, size); | |
928 | } | |
929 | ||
76c3fbcd SG |
930 | static int skip_to_next_device(struct udevice *bus, struct udevice **devp) |
931 | { | |
932 | struct udevice *dev; | |
933 | int ret = 0; | |
934 | ||
935 | /* | |
936 | * Scan through all the PCI controllers. On x86 there will only be one | |
937 | * but that is not necessarily true on other hardware. | |
938 | */ | |
939 | do { | |
940 | device_find_first_child(bus, &dev); | |
941 | if (dev) { | |
942 | *devp = dev; | |
943 | return 0; | |
944 | } | |
945 | ret = uclass_next_device(&bus); | |
946 | if (ret) | |
947 | return ret; | |
948 | } while (bus); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | int pci_find_next_device(struct udevice **devp) | |
954 | { | |
955 | struct udevice *child = *devp; | |
956 | struct udevice *bus = child->parent; | |
957 | int ret; | |
958 | ||
959 | /* First try all the siblings */ | |
960 | *devp = NULL; | |
961 | while (child) { | |
962 | device_find_next_child(&child); | |
963 | if (child) { | |
964 | *devp = child; | |
965 | return 0; | |
966 | } | |
967 | } | |
968 | ||
969 | /* We ran out of siblings. Try the next bus */ | |
970 | ret = uclass_next_device(&bus); | |
971 | if (ret) | |
972 | return ret; | |
973 | ||
974 | return bus ? skip_to_next_device(bus, devp) : 0; | |
975 | } | |
976 | ||
977 | int pci_find_first_device(struct udevice **devp) | |
978 | { | |
979 | struct udevice *bus; | |
980 | int ret; | |
981 | ||
982 | *devp = NULL; | |
983 | ret = uclass_first_device(UCLASS_PCI, &bus); | |
984 | if (ret) | |
985 | return ret; | |
986 | ||
987 | return skip_to_next_device(bus, devp); | |
988 | } | |
989 | ||
9289db6c SG |
990 | ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size) |
991 | { | |
992 | switch (size) { | |
993 | case PCI_SIZE_8: | |
994 | return (value >> ((offset & 3) * 8)) & 0xff; | |
995 | case PCI_SIZE_16: | |
996 | return (value >> ((offset & 2) * 8)) & 0xffff; | |
997 | default: | |
998 | return value; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, | |
1003 | enum pci_size_t size) | |
1004 | { | |
1005 | uint off_mask; | |
1006 | uint val_mask, shift; | |
1007 | ulong ldata, mask; | |
1008 | ||
1009 | switch (size) { | |
1010 | case PCI_SIZE_8: | |
1011 | off_mask = 3; | |
1012 | val_mask = 0xff; | |
1013 | break; | |
1014 | case PCI_SIZE_16: | |
1015 | off_mask = 2; | |
1016 | val_mask = 0xffff; | |
1017 | break; | |
1018 | default: | |
1019 | return value; | |
1020 | } | |
1021 | shift = (offset & off_mask) * 8; | |
1022 | ldata = (value & val_mask) << shift; | |
1023 | mask = val_mask << shift; | |
1024 | value = (old & ~mask) | ldata; | |
1025 | ||
1026 | return value; | |
1027 | } | |
1028 | ||
f9260336 SG |
1029 | int pci_get_regions(struct udevice *dev, struct pci_region **iop, |
1030 | struct pci_region **memp, struct pci_region **prefp) | |
1031 | { | |
1032 | struct udevice *bus = pci_get_controller(dev); | |
1033 | struct pci_controller *hose = dev_get_uclass_priv(bus); | |
1034 | int i; | |
1035 | ||
1036 | *iop = NULL; | |
1037 | *memp = NULL; | |
1038 | *prefp = NULL; | |
1039 | for (i = 0; i < hose->region_count; i++) { | |
1040 | switch (hose->regions[i].flags) { | |
1041 | case PCI_REGION_IO: | |
1042 | if (!*iop || (*iop)->size < hose->regions[i].size) | |
1043 | *iop = hose->regions + i; | |
1044 | break; | |
1045 | case PCI_REGION_MEM: | |
1046 | if (!*memp || (*memp)->size < hose->regions[i].size) | |
1047 | *memp = hose->regions + i; | |
1048 | break; | |
1049 | case (PCI_REGION_MEM | PCI_REGION_PREFETCH): | |
1050 | if (!*prefp || (*prefp)->size < hose->regions[i].size) | |
1051 | *prefp = hose->regions + i; | |
1052 | break; | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL); | |
1057 | } | |
1058 | ||
bab17cf1 SG |
1059 | u32 dm_pci_read_bar32(struct udevice *dev, int barnum) |
1060 | { | |
1061 | u32 addr; | |
1062 | int bar; | |
1063 | ||
1064 | bar = PCI_BASE_ADDRESS_0 + barnum * 4; | |
1065 | dm_pci_read_config32(dev, bar, &addr); | |
1066 | if (addr & PCI_BASE_ADDRESS_SPACE_IO) | |
1067 | return addr & PCI_BASE_ADDRESS_IO_MASK; | |
1068 | else | |
1069 | return addr & PCI_BASE_ADDRESS_MEM_MASK; | |
1070 | } | |
1071 | ||
21d1fe7e SG |
1072 | static int _dm_pci_bus_to_phys(struct udevice *ctlr, |
1073 | pci_addr_t bus_addr, unsigned long flags, | |
1074 | unsigned long skip_mask, phys_addr_t *pa) | |
1075 | { | |
1076 | struct pci_controller *hose = dev_get_uclass_priv(ctlr); | |
1077 | struct pci_region *res; | |
1078 | int i; | |
1079 | ||
1080 | for (i = 0; i < hose->region_count; i++) { | |
1081 | res = &hose->regions[i]; | |
1082 | ||
1083 | if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) | |
1084 | continue; | |
1085 | ||
1086 | if (res->flags & skip_mask) | |
1087 | continue; | |
1088 | ||
1089 | if (bus_addr >= res->bus_start && | |
1090 | (bus_addr - res->bus_start) < res->size) { | |
1091 | *pa = (bus_addr - res->bus_start + res->phys_start); | |
1092 | return 0; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | return 1; | |
1097 | } | |
1098 | ||
1099 | phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr, | |
1100 | unsigned long flags) | |
1101 | { | |
1102 | phys_addr_t phys_addr = 0; | |
1103 | struct udevice *ctlr; | |
1104 | int ret; | |
1105 | ||
1106 | /* The root controller has the region information */ | |
1107 | ctlr = pci_get_controller(dev); | |
1108 | ||
1109 | /* | |
1110 | * if PCI_REGION_MEM is set we do a two pass search with preference | |
1111 | * on matches that don't have PCI_REGION_SYS_MEMORY set | |
1112 | */ | |
1113 | if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { | |
1114 | ret = _dm_pci_bus_to_phys(ctlr, bus_addr, | |
1115 | flags, PCI_REGION_SYS_MEMORY, | |
1116 | &phys_addr); | |
1117 | if (!ret) | |
1118 | return phys_addr; | |
1119 | } | |
1120 | ||
1121 | ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr); | |
1122 | ||
1123 | if (ret) | |
1124 | puts("pci_hose_bus_to_phys: invalid physical address\n"); | |
1125 | ||
1126 | return phys_addr; | |
1127 | } | |
1128 | ||
1129 | int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, | |
1130 | unsigned long flags, unsigned long skip_mask, | |
1131 | pci_addr_t *ba) | |
1132 | { | |
1133 | struct pci_region *res; | |
1134 | struct udevice *ctlr; | |
1135 | pci_addr_t bus_addr; | |
1136 | int i; | |
1137 | struct pci_controller *hose; | |
1138 | ||
1139 | /* The root controller has the region information */ | |
1140 | ctlr = pci_get_controller(dev); | |
1141 | hose = dev_get_uclass_priv(ctlr); | |
1142 | ||
1143 | for (i = 0; i < hose->region_count; i++) { | |
1144 | res = &hose->regions[i]; | |
1145 | ||
1146 | if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) | |
1147 | continue; | |
1148 | ||
1149 | if (res->flags & skip_mask) | |
1150 | continue; | |
1151 | ||
1152 | bus_addr = phys_addr - res->phys_start + res->bus_start; | |
1153 | ||
1154 | if (bus_addr >= res->bus_start && | |
1155 | (bus_addr - res->bus_start) < res->size) { | |
1156 | *ba = bus_addr; | |
1157 | return 0; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | return 1; | |
1162 | } | |
1163 | ||
1164 | pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, | |
1165 | unsigned long flags) | |
1166 | { | |
1167 | pci_addr_t bus_addr = 0; | |
1168 | int ret; | |
1169 | ||
1170 | /* | |
1171 | * if PCI_REGION_MEM is set we do a two pass search with preference | |
1172 | * on matches that don't have PCI_REGION_SYS_MEMORY set | |
1173 | */ | |
1174 | if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) { | |
1175 | ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, | |
1176 | PCI_REGION_SYS_MEMORY, &bus_addr); | |
1177 | if (!ret) | |
1178 | return bus_addr; | |
1179 | } | |
1180 | ||
1181 | ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr); | |
1182 | ||
1183 | if (ret) | |
1184 | puts("pci_hose_phys_to_bus: invalid physical address\n"); | |
1185 | ||
1186 | return bus_addr; | |
1187 | } | |
1188 | ||
1189 | void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) | |
1190 | { | |
1191 | pci_addr_t pci_bus_addr; | |
1192 | u32 bar_response; | |
1193 | ||
1194 | /* read BAR address */ | |
1195 | dm_pci_read_config32(dev, bar, &bar_response); | |
1196 | pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); | |
1197 | ||
1198 | /* | |
1199 | * Pass "0" as the length argument to pci_bus_to_virt. The arg | |
1200 | * isn't actualy used on any platform because u-boot assumes a static | |
1201 | * linear mapping. In the future, this could read the BAR size | |
1202 | * and pass that as the size if needed. | |
1203 | */ | |
1204 | return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); | |
1205 | } | |
1206 | ||
ff3e077b SG |
1207 | UCLASS_DRIVER(pci) = { |
1208 | .id = UCLASS_PCI, | |
1209 | .name = "pci", | |
2bb02e4f | 1210 | .flags = DM_UC_FLAG_SEQ_ALIAS, |
ff3e077b SG |
1211 | .post_bind = pci_uclass_post_bind, |
1212 | .pre_probe = pci_uclass_pre_probe, | |
1213 | .post_probe = pci_uclass_post_probe, | |
1214 | .child_post_bind = pci_uclass_child_post_bind, | |
1215 | .per_device_auto_alloc_size = sizeof(struct pci_controller), | |
1216 | .per_child_platdata_auto_alloc_size = | |
1217 | sizeof(struct pci_child_platdata), | |
1218 | }; | |
1219 | ||
1220 | static const struct dm_pci_ops pci_bridge_ops = { | |
1221 | .read_config = pci_bridge_read_config, | |
1222 | .write_config = pci_bridge_write_config, | |
1223 | }; | |
1224 | ||
1225 | static const struct udevice_id pci_bridge_ids[] = { | |
1226 | { .compatible = "pci-bridge" }, | |
1227 | { } | |
1228 | }; | |
1229 | ||
1230 | U_BOOT_DRIVER(pci_bridge_drv) = { | |
1231 | .name = "pci_bridge_drv", | |
1232 | .id = UCLASS_PCI, | |
1233 | .of_match = pci_bridge_ids, | |
1234 | .ops = &pci_bridge_ops, | |
1235 | }; | |
1236 | ||
1237 | UCLASS_DRIVER(pci_generic) = { | |
1238 | .id = UCLASS_PCI_GENERIC, | |
1239 | .name = "pci_generic", | |
1240 | }; | |
1241 | ||
1242 | static const struct udevice_id pci_generic_ids[] = { | |
1243 | { .compatible = "pci-generic" }, | |
1244 | { } | |
1245 | }; | |
1246 | ||
1247 | U_BOOT_DRIVER(pci_generic_drv) = { | |
1248 | .name = "pci_generic_drv", | |
1249 | .id = UCLASS_PCI_GENERIC, | |
1250 | .of_match = pci_generic_ids, | |
1251 | }; |