[people/ms/u-boot.git] / drivers / pci / pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * (C) Copyright 2002, 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Old PCI routines
 *
 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
 * and change pci-uclass.c.
 */

#include <common.h>

#include <command.h>
#include <errno.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

DECLARE_GLOBAL_DATA_PTR;

#define PCI_HOSE_OP(rw, size, type)					\
int pci_hose_##rw##_config_##size(struct pci_controller *hose,		\
				  pci_dev_t dev,			\
				  int offset, type value)		\
{									\
	return hose->rw##_##size(hose, dev, offset, value);		\
}

PCI_HOSE_OP(read, byte, u8 *)
PCI_HOSE_OP(read, word, u16 *)
PCI_HOSE_OP(read, dword, u32 *)
PCI_HOSE_OP(write, byte, u8)
PCI_HOSE_OP(write, word, u16)
PCI_HOSE_OP(write, dword, u32)

#define PCI_OP(rw, size, type, error_code)				\
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
{									\
	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));	\
									\
	if (!hose)							\
	{								\
		error_code;						\
		return -1;						\
	}								\
									\
	return pci_hose_##rw##_config_##size(hose, dev, offset, value);	\
}

PCI_OP(read, byte, u8 *, *value = 0xff)
PCI_OP(read, word, u16 *, *value = 0xffff)
PCI_OP(read, dword, u32 *, *value = 0xffffffff)
PCI_OP(write, byte, u8, )
PCI_OP(write, word, u16, )
PCI_OP(write, dword, u32, )

#define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
					pci_dev_t dev,			\
					int offset, type val)		\
{									\
	u32 val32;							\
									\
	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) {	\
		*val = -1;						\
		return -1;						\
	}								\
									\
	*val = (val32 >> ((offset & (int)off_mask) * 8));		\
									\
	return 0;							\
}

#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)		\
int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
					     pci_dev_t dev,		\
					     int offset, type val)	\
{									\
	u32 val32, mask, ldata, shift;					\
									\
	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
		return -1;						\
									\
	shift = ((offset & (int)off_mask) * 8);				\
	ldata = (((unsigned long)val) & val_mask) << shift;		\
	mask = val_mask << shift;					\
	val32 = (val32 & ~mask) | ldata;				\
									\
	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
		return -1;						\
									\
	return 0;							\
}

PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)

/*
 *
 */

static struct pci_controller* hose_head;

struct pci_controller *pci_get_hose_head(void)
{
	if (gd->hose)
		return gd->hose;

	return hose_head;
}

void pci_register_hose(struct pci_controller* hose)
{
	struct pci_controller **phose = &hose_head;

	while(*phose)
		phose = &(*phose)->next;

	hose->next = NULL;

	*phose = hose;
}

struct pci_controller *pci_bus_to_hose(int bus)
{
	struct pci_controller *hose;

	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
		if (bus >= hose->first_busno && bus <= hose->last_busno)
			return hose;
	}

	printf("pci_bus_to_hose() failed\n");
	return NULL;
}

struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
{
	struct pci_controller *hose;

	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
		if (hose->cfg_addr == cfg_addr)
			return hose;
	}

	return NULL;
}

int pci_last_busno(void)
{
	struct pci_controller *hose = pci_get_hose_head();

	if (!hose)
		return -1;

	while (hose->next)
		hose = hose->next;

	return hose->last_busno;
}

pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
	struct pci_controller * hose;
	pci_dev_t bdf;
	int bus;

	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
		for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
			bdf = pci_hose_find_devices(hose, bus, ids, &index);
			if (bdf != -1)
				return bdf;
		}
	}

	return -1;
}

int pci_hose_config_device(struct pci_controller *hose,
			   pci_dev_t dev,
			   unsigned long io,
			   pci_addr_t mem,
			   unsigned long command)
{
	u32 bar_response;
	unsigned int old_command;
	pci_addr_t bar_value;
	pci_size_t bar_size;
	unsigned char pin;
	int bar, found_mem64;

	debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
		(u64)mem, command);

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);

	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
			/* round up region base address to a multiple of size */
			io = ((io - 1) | (bar_size - 1)) + 1;
			bar_value = io;
			/* compute new region base address */
			io = io + bar_size;
		} else {
			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
				PCI_BASE_ADDRESS_MEM_TYPE_64) {
				u32 bar_response_upper;
				u64 bar64;
				pci_hose_write_config_dword(hose, dev, bar + 4,
					0xffffffff);
				pci_hose_read_config_dword(hose, dev, bar + 4,
					&bar_response_upper);

				bar64 = ((u64)bar_response_upper << 32) | bar_response;

				bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
				found_mem64 = 1;
			} else {
				bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
			}

			/* round up region base address to multiple of size */
			mem = ((mem - 1) | (bar_size - 1)) + 1;
			bar_value = mem;
			/* compute new region base address */
			mem = mem + bar_size;
		}

		/* Write it out and update our limit */
		pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);

		if (found_mem64) {
			bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
			pci_hose_write_config_dword(hose, dev, bar,
				(u32)(bar_value >> 32));
#else
			pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
		}
	}

	/* Configure Cache Line Size Register */
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

	/* Configure Latency Timer */
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);

	/* Disable interrupt line, if device says it wants to use interrupts */
	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
	if (pin != 0) {
		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
					   PCI_INTERRUPT_LINE_DISABLE);
	}

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
				     (old_command & 0xffff0000) | command);

	return 0;
}

/*
 *
 */

struct pci_config_table *pci_find_config(struct pci_controller *hose,
					 unsigned short class,
					 unsigned int vendor,
					 unsigned int device,
					 unsigned int bus,
					 unsigned int dev,
					 unsigned int func)
{
	struct pci_config_table *table;

	for (table = hose->config_table; table && table->vendor; table++) {
		if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
		    (table->device == PCI_ANY_ID || table->device == device) &&
		    (table->class  == PCI_ANY_ID || table->class  == class)  &&
		    (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
		    (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
		    (table->func   == PCI_ANY_ID || table->func   == func)) {
			return table;
		}
	}

	return NULL;
}

void pci_cfgfunc_config_device(struct pci_controller *hose,
			       pci_dev_t dev,
			       struct pci_config_table *entry)
{
	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
		entry->priv[2]);
}

void pci_cfgfunc_do_nothing(struct pci_controller *hose,
			    pci_dev_t dev, struct pci_config_table *entry)
{
}

/*
 * HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);

#ifdef CONFIG_PCI_SCAN_SHOW
__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
	if (dev == PCI_BDF(hose->first_busno, 0, 0))
		return 0;

	return 1;
}
#endif /* CONFIG_PCI_SCAN_SHOW */

int pci_hose_scan_bus(struct pci_controller *hose, int bus)
{
	unsigned int sub_bus, found_multi = 0;
	unsigned short vendor, device, class;
	unsigned char header_type;
#ifndef CONFIG_PCI_PNP
	struct pci_config_table *cfg;
#endif
	pci_dev_t dev;
#ifdef CONFIG_PCI_SCAN_SHOW
	static int indent = 0;
#endif

	sub_bus = bus;

	for (dev =  PCI_BDF(bus,0,0);
	     dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
				PCI_MAX_PCI_FUNCTIONS - 1);
	     dev += PCI_BDF(0, 0, 1)) {

		if (pci_skip_dev(hose, dev))
			continue;

		if (PCI_FUNC(dev) && !found_multi)
			continue;

		pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);

		pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);

		if (vendor == 0xffff || vendor == 0x0000)
			continue;

		if (!PCI_FUNC(dev))
			found_multi = header_type & 0x80;

		debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
			PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));

		pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
		pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

#ifdef CONFIG_PCI_FIXUP_DEV
		board_pci_fixup_dev(hose, dev, vendor, device, class);
#endif

#ifdef CONFIG_PCI_SCAN_SHOW
		indent++;

		/* Print leading space, including bus indentation */
		printf("%*c", indent + 1, ' ');

		if (pci_print_dev(hose, dev)) {
			printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
			       PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
			       vendor, device, pci_class_str(class >> 8));
		}
#endif

#ifdef CONFIG_PCI_PNP
		sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
			      sub_bus);
#else
		cfg = pci_find_config(hose, class, vendor, device,
				      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
		if (cfg) {
			cfg->config_device(hose, dev, cfg);
			sub_bus = max(sub_bus,
				      (unsigned int)hose->current_busno);
		}
#endif

#ifdef CONFIG_PCI_SCAN_SHOW
		indent--;
#endif

		if (hose->fixup_irq)
			hose->fixup_irq(hose, dev);
	}

	return sub_bus;
}

int pci_hose_scan(struct pci_controller *hose)
{
#if defined(CONFIG_PCI_BOOTDELAY)
	char *s;
	int i;

	if (!gd->pcidelay_done) {
		/* wait "pcidelay" ms (if defined)... */
		s = env_get("pcidelay");
		if (s) {
			int val = simple_strtoul(s, NULL, 10);
			for (i = 0; i < val; i++)
				udelay(1000);
		}
		gd->pcidelay_done = 1;
	}
#endif /* CONFIG_PCI_BOOTDELAY */

#ifdef CONFIG_PCI_SCAN_SHOW
	puts("PCI:\n");
#endif

	/*
	 * Start scan at current_busno.
	 * PCIe will start scan at first_busno+1.
	 */
	/* For legacy support, ensure current >= first */
	if (hose->first_busno > hose->current_busno)
		hose->current_busno = hose->first_busno;
#ifdef CONFIG_PCI_PNP
	pciauto_config_init(hose);
#endif
	return pci_hose_scan_bus(hose, hose->current_busno);
}

void pci_init(void)
{
	hose_head = NULL;

	/* allow env to disable pci init/enum */
	if (env_get("pcidisable") != NULL)
		return;

	/* now call board specific pci_init()... */
	pci_init_board();
}

/* Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 * */
int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
			     int cap)
{
	int pos;
	u8 hdr_type;

	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);

	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);

	if (pos)
		pos = pci_find_cap(hose, dev, pos, cap);

	return pos;
}

/* Find the header pointer to the Capabilities*/
int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
			    u8 hdr_type)
{
	u16 status;

	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);

	if (!(status & PCI_STATUS_CAP_LIST))
		return 0;

	switch (hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
	case PCI_HEADER_TYPE_BRIDGE:
		return PCI_CAPABILITY_LIST;
	case PCI_HEADER_TYPE_CARDBUS:
		return PCI_CB_CAPABILITY_LIST;
	default:
		return 0;
	}
}

int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
{
	int ttl = PCI_FIND_CAP_TTL;
	u8 id;
	u8 next_pos;

	while (ttl--) {
		pci_hose_read_config_byte(hose, dev, pos, &next_pos);
		if (next_pos < CAP_START_POS)
			break;
		next_pos &= ~3;
		pos = (int) next_pos;
		pci_hose_read_config_byte(hose, dev,
					  pos + PCI_CAP_LIST_ID, &id);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos += PCI_CAP_LIST_NEXT;
	}
	return 0;
}

/**
 * pci_find_next_ext_capability - Find an extended capability
 *
 * Returns the address of the next matching extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.  Some capabilities can occur several times, e.g., the
 * vendor-specific capability, and this provides a way to find them all.
 */
int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
				 int start, int cap)
{
	u32 header;
	int ttl, pos = PCI_CFG_SPACE_SIZE;

	/* minimum 8 bytes per capability */
	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

	if (start)
		pos = start;

	pci_hose_read_config_dword(hose, dev, pos, &header);
	if (header == 0xffffffff || header == 0)
		return 0;

	while (ttl-- > 0) {
		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
			return pos;

		pos = PCI_EXT_CAP_NEXT(header);
		if (pos < PCI_CFG_SPACE_SIZE)
			break;

		pci_hose_read_config_dword(hose, dev, pos, &header);
		if (header == 0xffffffff || header == 0)
			break;
	}

	return 0;
}

/**
 * pci_hose_find_ext_capability - Find an extended capability
 *
 * Returns the address of the requested extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.
 */
int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
				 int cap)
{
	return pci_find_next_ext_capability(hose, dev, 0, cap);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <aheppel@sysgo.de>
	4	*
f07771cc	5	* (C) Copyright 2002, 2003
c609719b WD	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
c609719b WD	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	9	*/
	10
	11	/*
2b81e8a3 SG	12	* Old PCI routines
	13	*
	14	* Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
	15	* and change pci-uclass.c.
c609719b WD	16	*/
	17
	18	#include <common.h>
	19
c609719b	20	#include <command.h>
250e039d	21	#include <errno.h>
c609719b WD	22	#include <asm/processor.h>
	23	#include <asm/io.h>
	24	#include <pci.h>
	25
8f9052fd BM	26	DECLARE_GLOBAL_DATA_PTR;
8f9052fd BM	27
f07771cc	28	#define PCI_HOSE_OP(rw, size, type) \
53677ef1 WD	29	int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
53677ef1 WD	30	pci_dev_t dev, \
f07771cc WD	31	int offset, type value) \
	32	{ \
	33	return hose->rw##_##size(hose, dev, offset, value); \
c609719b WD	34	}
	35
	36	PCI_HOSE_OP(read, byte, u8 *)
	37	PCI_HOSE_OP(read, word, u16 *)
	38	PCI_HOSE_OP(read, dword, u32 *)
	39	PCI_HOSE_OP(write, byte, u8)
	40	PCI_HOSE_OP(write, word, u16)
	41	PCI_HOSE_OP(write, dword, u32)
	42
f07771cc WD	43	#define PCI_OP(rw, size, type, error_code) \
	44	int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
	45	{ \
	46	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
	47	\
	48	if (!hose) \
	49	{ \
	50	error_code; \
	51	return -1; \
	52	} \
	53	\
	54	return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
c609719b WD	55	}
	56
	57	PCI_OP(read, byte, u8 , value = 0xff)
	58	PCI_OP(read, word, u16 , value = 0xffff)
	59	PCI_OP(read, dword, u32 , value = 0xffffffff)
	60	PCI_OP(write, byte, u8, )
	61	PCI_OP(write, word, u16, )
	62	PCI_OP(write, dword, u32, )
	63
f07771cc WD	64	#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
f07771cc WD	65	int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
53677ef1	66	pci_dev_t dev, \
f07771cc WD	67	int offset, type val) \
	68	{ \
	69	u32 val32; \
	70	\
815b5bd5 SK	71	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
815b5bd5 SK	72	*val = -1; \
f07771cc	73	return -1; \
815b5bd5	74	} \
f07771cc WD	75	\
	76	val = (val32 >> ((offset & (int)off_mask) 8)); \
	77	\
	78	return 0; \
c609719b WD	79	}
c609719b WD	80
f07771cc WD	81	#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
f07771cc WD	82	int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
53677ef1	83	pci_dev_t dev, \
f07771cc WD	84	int offset, type val) \
f07771cc WD	85	{ \
498b8db7	86	u32 val32, mask, ldata, shift; \
f07771cc WD	87	\
	88	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
	89	return -1; \
	90	\
498b8db7 WD	91	shift = ((offset & (int)off_mask) * 8); \
	92	ldata = (((unsigned long)val) & val_mask) << shift; \
	93	mask = val_mask << shift; \
f07771cc WD	94	val32 = (val32 & ~mask) \| ldata; \
	95	\
	96	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
	97	return -1; \
	98	\
	99	return 0; \
c609719b WD	100	}
	101
	102	PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
	103	PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
	104	PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
	105	PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
	106
	107	/*
	108	*
	109	*/
	110
96d61603	111	static struct pci_controller* hose_head;
c609719b	112
8f9052fd BM	113	struct pci_controller *pci_get_hose_head(void)
	114	{
	115	if (gd->hose)
	116	return gd->hose;
	117
	118	return hose_head;
	119	}
	120
c609719b WD	121	void pci_register_hose(struct pci_controller* hose)
	122	{
	123	struct pci_controller **phose = &hose_head;
	124
	125	while(*phose)
	126	phose = &(*phose)->next;
	127
	128	hose->next = NULL;
	129
	130	*phose = hose;
	131	}
	132
cb2bf931	133	struct pci_controller *pci_bus_to_hose(int bus)
c609719b WD	134	{
	135	struct pci_controller *hose;
	136
8f9052fd	137	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
f07771cc	138	if (bus >= hose->first_busno && bus <= hose->last_busno)
c609719b	139	return hose;
cb2bf931	140	}
c609719b	141
6902df56	142	printf("pci_bus_to_hose() failed\n");
c609719b WD	143	return NULL;
	144	}
	145
3a0e3c27 KG	146	struct pci_controller find_hose_by_cfg_addr(void cfg_addr)
	147	{
	148	struct pci_controller *hose;
	149
8f9052fd	150	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
3a0e3c27 KG	151	if (hose->cfg_addr == cfg_addr)
	152	return hose;
	153	}
	154
	155	return NULL;
	156	}
	157
cc2a8c77 AV	158	int pci_last_busno(void)
cc2a8c77 AV	159	{
8f9052fd	160	struct pci_controller *hose = pci_get_hose_head();
cc2a8c77 AV	161
	162	if (!hose)
	163	return -1;
	164
	165	while (hose->next)
	166	hose = hose->next;
	167
	168	return hose->last_busno;
	169	}
	170
c609719b WD	171	pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
	172	{
	173	struct pci_controller * hose;
c609719b	174	pci_dev_t bdf;
aab6724c	175	int bus;
c609719b	176
8f9052fd	177	for (hose = pci_get_hose_head(); hose; hose = hose->next) {
aab6724c	178	for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
aab6724c SG	179	bdf = pci_hose_find_devices(hose, bus, ids, &index);
aab6724c SG	180	if (bdf != -1)
250e039d	181	return bdf;
250e039d SG	182	}
	183	}
	184
aab6724c	185	return -1;
c609719b WD	186	}
c609719b WD	187
c609719b WD	188	int pci_hose_config_device(struct pci_controller *hose,
	189	pci_dev_t dev,
	190	unsigned long io,
30e76d5e	191	pci_addr_t mem,
c609719b WD	192	unsigned long command)
c609719b WD	193	{
cf5787f2	194	u32 bar_response;
af778c6d	195	unsigned int old_command;
30e76d5e KG	196	pci_addr_t bar_value;
30e76d5e KG	197	pci_size_t bar_size;
c609719b WD	198	unsigned char pin;
	199	int bar, found_mem64;
	200
cb2bf931 AS	201	debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
cb2bf931 AS	202	(u64)mem, command);
c609719b	203
cb2bf931	204	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
c609719b	205
252b404d	206	for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
cb2bf931 AS	207	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
cb2bf931 AS	208	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
c609719b WD	209
	210	if (!bar_response)
	211	continue;
	212
	213	found_mem64 = 0;
	214
	215	/* Check the BAR type and set our address mask */
f07771cc	216	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
c609719b	217	bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
f07771cc	218	/* round up region base address to a multiple of size */
c609719b	219	io = ((io - 1) \| (bar_size - 1)) + 1;
f07771cc WD	220	bar_value = io;
	221	/* compute new region base address */
	222	io = io + bar_size;
	223	} else {
	224	if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
30e76d5e KG	225	PCI_BASE_ADDRESS_MEM_TYPE_64) {
	226	u32 bar_response_upper;
	227	u64 bar64;
cb2bf931 AS	228	pci_hose_write_config_dword(hose, dev, bar + 4,
	229	0xffffffff);
	230	pci_hose_read_config_dword(hose, dev, bar + 4,
	231	&bar_response_upper);
30e76d5e KG	232
30e76d5e KG	233	bar64 = ((u64)bar_response_upper << 32) \| bar_response;
c609719b	234
30e76d5e KG	235	bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
	236	found_mem64 = 1;
	237	} else {
	238	bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
	239	}
c609719b	240
f07771cc	241	/* round up region base address to multiple of size */
c609719b	242	mem = ((mem - 1) \| (bar_size - 1)) + 1;
f07771cc WD	243	bar_value = mem;
	244	/* compute new region base address */
	245	mem = mem + bar_size;
c609719b WD	246	}
	247
	248	/* Write it out and update our limit */
30e76d5e	249	pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
c609719b	250
f07771cc	251	if (found_mem64) {
c609719b	252	bar += 4;
30e76d5e	253	#ifdef CONFIG_SYS_PCI_64BIT
cb2bf931 AS	254	pci_hose_write_config_dword(hose, dev, bar,
cb2bf931 AS	255	(u32)(bar_value >> 32));
30e76d5e	256	#else
cb2bf931	257	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
30e76d5e	258	#endif
c609719b WD	259	}
	260	}
	261
	262	/* Configure Cache Line Size Register */
cb2bf931	263	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
c609719b WD	264
c609719b WD	265	/* Configure Latency Timer */
cb2bf931	266	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
c609719b WD	267
c609719b WD	268	/* Disable interrupt line, if device says it wants to use interrupts */
cb2bf931	269	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
f07771cc	270	if (pin != 0) {
5f48d798 SG	271	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
5f48d798 SG	272	PCI_INTERRUPT_LINE_DISABLE);
c609719b WD	273	}
c609719b WD	274
cb2bf931 AS	275	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
cb2bf931 AS	276	pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
f07771cc	277	(old_command & 0xffff0000) \| command);
c609719b WD	278
	279	return 0;
	280	}
	281
	282	/*
	283	*
	284	*/
	285
	286	struct pci_config_table pci_find_config(struct pci_controller hose,
	287	unsigned short class,
	288	unsigned int vendor,
	289	unsigned int device,
	290	unsigned int bus,
	291	unsigned int dev,
	292	unsigned int func)
	293	{
	294	struct pci_config_table *table;
	295
f07771cc	296	for (table = hose->config_table; table && table->vendor; table++) {
c609719b WD	297	if ((table->vendor == PCI_ANY_ID \|\| table->vendor == vendor) &&
	298	(table->device == PCI_ANY_ID \|\| table->device == device) &&
	299	(table->class == PCI_ANY_ID \|\| table->class == class) &&
	300	(table->bus == PCI_ANY_ID \|\| table->bus == bus) &&
	301	(table->dev == PCI_ANY_ID \|\| table->dev == dev) &&
f07771cc	302	(table->func == PCI_ANY_ID \|\| table->func == func)) {
c609719b WD	303	return table;
	304	}
	305	}
	306
	307	return NULL;
	308	}
	309
	310	void pci_cfgfunc_config_device(struct pci_controller *hose,
	311	pci_dev_t dev,
	312	struct pci_config_table *entry)
	313	{
cb2bf931 AS	314	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
cb2bf931 AS	315	entry->priv[2]);
c609719b WD	316	}
	317
	318	void pci_cfgfunc_do_nothing(struct pci_controller *hose,
	319	pci_dev_t dev, struct pci_config_table *entry)
	320	{
	321	}
	322
	323	/*
cb2bf931	324	* HJF: Changed this to return int. I think this is required
c7de829c WD	325	* to get the correct result when scanning bridges
	326	*/
	327	extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
c609719b	328
dc1da42f	329	#ifdef CONFIG_PCI_SCAN_SHOW
7b19fd6d	330	__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
dc1da42f SR	331	{
	332	if (dev == PCI_BDF(hose->first_busno, 0, 0))
	333	return 0;
	334
	335	return 1;
	336	}
dc1da42f SR	337	#endif /* CONFIG_PCI_SCAN_SHOW */
dc1da42f SR	338
c609719b WD	339	int pci_hose_scan_bus(struct pci_controller *hose, int bus)
c609719b WD	340	{
cb2bf931	341	unsigned int sub_bus, found_multi = 0;
c609719b WD	342	unsigned short vendor, device, class;
c609719b WD	343	unsigned char header_type;
03992ac2	344	#ifndef CONFIG_PCI_PNP
c609719b	345	struct pci_config_table *cfg;
03992ac2	346	#endif
c609719b	347	pci_dev_t dev;
009884ae PT	348	#ifdef CONFIG_PCI_SCAN_SHOW
	349	static int indent = 0;
	350	#endif
c609719b WD	351
	352	sub_bus = bus;
	353
	354	for (dev = PCI_BDF(bus,0,0);
cb2bf931 AS	355	dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
	356	PCI_MAX_PCI_FUNCTIONS - 1);
	357	dev += PCI_BDF(0, 0, 1)) {
dc1da42f SR	358
	359	if (pci_skip_dev(hose, dev))
	360	continue;
c609719b WD	361
	362	if (PCI_FUNC(dev) && !found_multi)
	363	continue;
	364
	365	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
	366
	367	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
	368
983eb9d1 PT	369	if (vendor == 0xffff \|\| vendor == 0x0000)
983eb9d1 PT	370	continue;
c609719b	371
983eb9d1 PT	372	if (!PCI_FUNC(dev))
983eb9d1 PT	373	found_multi = header_type & 0x80;
c609719b	374
cb2bf931 AS	375	debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
cb2bf931 AS	376	PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
c609719b	377
983eb9d1 PT	378	pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
983eb9d1 PT	379	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
c609719b	380
0991866c TH	381	#ifdef CONFIG_PCI_FIXUP_DEV
	382	board_pci_fixup_dev(hose, dev, vendor, device, class);
	383	#endif
	384
a38d216e	385	#ifdef CONFIG_PCI_SCAN_SHOW
009884ae PT	386	indent++;
	387
	388	/* Print leading space, including bus indentation */
	389	printf("%*c", indent + 1, ' ');
	390
a38d216e	391	if (pci_print_dev(hose, dev)) {
009884ae PT	392	printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
009884ae PT	393	PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
a38d216e PT	394	vendor, device, pci_class_str(class >> 8));
	395	}
	396	#endif
	397
03992ac2	398	#ifdef CONFIG_PCI_PNP
b4141195 MY	399	sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
b4141195 MY	400	sub_bus);
03992ac2	401	#else
983eb9d1 PT	402	cfg = pci_find_config(hose, class, vendor, device,
	403	PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
	404	if (cfg) {
	405	cfg->config_device(hose, dev, cfg);
b4141195 MY	406	sub_bus = max(sub_bus,
b4141195 MY	407	(unsigned int)hose->current_busno);
983eb9d1	408	}
03992ac2	409	#endif
a38d216e	410
009884ae PT	411	#ifdef CONFIG_PCI_SCAN_SHOW
	412	indent--;
	413	#endif
	414
983eb9d1 PT	415	if (hose->fixup_irq)
983eb9d1 PT	416	hose->fixup_irq(hose, dev);
c609719b WD	417	}
	418
	419	return sub_bus;
	420	}
	421
	422	int pci_hose_scan(struct pci_controller *hose)
	423	{
0da1fb03	424	#if defined(CONFIG_PCI_BOOTDELAY)
0da1fb03 AG	425	char *s;
	426	int i;
	427
8f9052fd	428	if (!gd->pcidelay_done) {
0da1fb03	429	/* wait "pcidelay" ms (if defined)... */
00caae6d	430	s = env_get("pcidelay");
0da1fb03 AG	431	if (s) {
	432	int val = simple_strtoul(s, NULL, 10);
	433	for (i = 0; i < val; i++)
	434	udelay(1000);
	435	}
8f9052fd	436	gd->pcidelay_done = 1;
0da1fb03 AG	437	}
	438	#endif /* CONFIG_PCI_BOOTDELAY */
	439
0373a7e9 TH	440	#ifdef CONFIG_PCI_SCAN_SHOW
	441	puts("PCI:\n");
	442	#endif
	443
cb2bf931 AS	444	/*
cb2bf931 AS	445	* Start scan at current_busno.
40e81add ES	446	* PCIe will start scan at first_busno+1.
40e81add ES	447	*/
cb2bf931	448	/* For legacy support, ensure current >= first */
40e81add ES	449	if (hose->first_busno > hose->current_busno)
40e81add ES	450	hose->current_busno = hose->first_busno;
c609719b WD	451	#ifdef CONFIG_PCI_PNP
	452	pciauto_config_init(hose);
	453	#endif
40e81add	454	return pci_hose_scan_bus(hose, hose->current_busno);
c609719b WD	455	}
c609719b WD	456
ad10dd9a SR	457	void pci_init(void)
ad10dd9a SR	458	{
96d61603 JS	459	hose_head = NULL;
96d61603 JS	460
ec21aee6	461	/* allow env to disable pci init/enum */
00caae6d	462	if (env_get("pcidisable") != NULL)
ec21aee6 TH	463	return;
ec21aee6 TH	464
ad10dd9a SR	465	/* now call board specific pci_init()... */
	466	pci_init_board();
	467	}
287df01e ZQ	468
	469	/* Returns the address of the requested capability structure within the
	470	* device's PCI configuration space or 0 in case the device does not
	471	* support it.
	472	* */
	473	int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
	474	int cap)
	475	{
	476	int pos;
	477	u8 hdr_type;
	478
	479	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
	480
	481	pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
	482
	483	if (pos)
	484	pos = pci_find_cap(hose, dev, pos, cap);
	485
	486	return pos;
	487	}
	488
	489	/* Find the header pointer to the Capabilities*/
	490	int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
	491	u8 hdr_type)
	492	{
	493	u16 status;
	494
	495	pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
	496
	497	if (!(status & PCI_STATUS_CAP_LIST))
	498	return 0;
	499
	500	switch (hdr_type) {
	501	case PCI_HEADER_TYPE_NORMAL:
	502	case PCI_HEADER_TYPE_BRIDGE:
	503	return PCI_CAPABILITY_LIST;
	504	case PCI_HEADER_TYPE_CARDBUS:
	505	return PCI_CB_CAPABILITY_LIST;
	506	default:
	507	return 0;
	508	}
	509	}
	510
	511	int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
	512	{
	513	int ttl = PCI_FIND_CAP_TTL;
	514	u8 id;
	515	u8 next_pos;
	516
	517	while (ttl--) {
	518	pci_hose_read_config_byte(hose, dev, pos, &next_pos);
	519	if (next_pos < CAP_START_POS)
	520	break;
	521	next_pos &= ~3;
	522	pos = (int) next_pos;
	523	pci_hose_read_config_byte(hose, dev,
	524	pos + PCI_CAP_LIST_ID, &id);
	525	if (id == 0xff)
	526	break;
	527	if (id == cap)
	528	return pos;
	529	pos += PCI_CAP_LIST_NEXT;
	530	}
	531	return 0;
532	}
ed5b580b ML	533
	534	/**
	535	* pci_find_next_ext_capability - Find an extended capability
	536	*
	537	* Returns the address of the next matching extended capability structure
	538	* within the device's PCI configuration space or 0 if the device does
	539	* not support it. Some capabilities can occur several times, e.g., the
	540	* vendor-specific capability, and this provides a way to find them all.
	541	*/
	542	int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
	543	int start, int cap)
	544	{
	545	u32 header;
	546	int ttl, pos = PCI_CFG_SPACE_SIZE;
	547
	548	/* minimum 8 bytes per capability */
	549	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
	550
	551	if (start)
	552	pos = start;
	553
	554	pci_hose_read_config_dword(hose, dev, pos, &header);
	555	if (header == 0xffffffff \|\| header == 0)
	556	return 0;
	557
	558	while (ttl-- > 0) {
	559	if (PCI_EXT_CAP_ID(header) == cap && pos != start)
	560	return pos;
	561
	562	pos = PCI_EXT_CAP_NEXT(header);
	563	if (pos < PCI_CFG_SPACE_SIZE)
	564	break;
	565
	566	pci_hose_read_config_dword(hose, dev, pos, &header);
	567	if (header == 0xffffffff \|\| header == 0)
	568	break;
	569	}
	570
	571	return 0;
	572	}
	573
	574	/**
	575	* pci_hose_find_ext_capability - Find an extended capability
	576	*
	577	* Returns the address of the requested extended capability structure
	578	* within the device's PCI configuration space or 0 if the device does
	579	* not support it.
	580	*/
	581	int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
	582	int cap)
	583	{
	584	return pci_find_next_ext_capability(hose, dev, 0, cap);
	585	}