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armv8: LS2080A: Rename LS2085A to reflect LS2080A
[people/ms/u-boot.git] / drivers / pci / pcie_layerscape.c
CommitLineData
da419027 1/*
e4e8cb71 2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
da419027
ML		 3 * Layerscape PCIe driver
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/arch/fsl_serdes.h>
10#include <pci.h>
11#include <asm/io.h>
e4e8cb71
ML		 12#include <errno.h>
13#include <malloc.h>
9f3183d2
MH		 14#ifdef CONFIG_FSL_LAYERSCAPE
15#include <asm/arch/fdt.h>
16#endif
da419027 17
e4e8cb71
ML		 18#ifndef CONFIG_SYS_PCI_MEMORY_BUS
19#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
20#endif
21
22#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
23#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
24#endif
25
26#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
27#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
28#endif
29
01cafced
ML		 30#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
31#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
32#endif
33
e4e8cb71
ML		 34/* iATU registers */
35#define PCIE_ATU_VIEWPORT 0x900
36#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
37#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
38#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
39#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
40#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
41#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
42#define PCIE_ATU_CR1 0x904
43#define PCIE_ATU_TYPE_MEM (0x0 << 0)
44#define PCIE_ATU_TYPE_IO (0x2 << 0)
45#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
46#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
47#define PCIE_ATU_CR2 0x908
48#define PCIE_ATU_ENABLE (0x1 << 31)
49#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
01cafced 50#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
e4e8cb71
ML		 51#define PCIE_ATU_LOWER_BASE 0x90C
52#define PCIE_ATU_UPPER_BASE 0x910
53#define PCIE_ATU_LIMIT 0x914
54#define PCIE_ATU_LOWER_TARGET 0x918
55#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
56#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
57#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
58#define PCIE_ATU_UPPER_TARGET 0x91C
59
00704590
ML		 60/* LUT registers */
61#define PCIE_LUT_BASE 0x80000
01cafced 62#define PCIE_LUT_LCTRL0 0x7F8
00704590
ML		 63#define PCIE_LUT_DBG 0x7FC
64
65#define PCIE_DBI_RO_WR_EN 0x8bc
66
e4e8cb71
ML		 67#define PCIE_LINK_CAP 0x7c
68#define PCIE_LINK_SPEED_MASK 0xf
69#define PCIE_LINK_STA 0x82
70
00704590
ML		 71#define LTSSM_STATE_MASK 0x3f
72#define LTSSM_PCIE_L0 0x11 /* L0 state */
73
74#define PCIE_DBI_SIZE 0x100000 /* 1M */
e4e8cb71 75
01cafced
ML		 76#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
77#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
78#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
79#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
80#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
81 PCIE_LCTRL0_VF(vf) | \
82 ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
83 PCIE_LCTRL0_CFG2_ENABLE)
84
85#define PCIE_NO_SRIOV_BAR_BASE 0x1000
86
87#define PCIE_PF_NUM 2
88#define PCIE_VF_NUM 64
89
90#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
91#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
92#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
93#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
94
e4e8cb71
ML		 95struct ls_pcie {
96 int idx;
97 void __iomem *dbi;
98 void __iomem *va_cfg0;
99 void __iomem *va_cfg1;
100 struct pci_controller hose;
101};
102
103struct ls_pcie_info {
104 unsigned long regs;
105 int pci_num;
01cafced 106 u64 phys_base;
e4e8cb71
ML		 107 u64 cfg0_phys;
108 u64 cfg0_size;
109 u64 cfg1_phys;
110 u64 cfg1_size;
111 u64 mem_bus;
112 u64 mem_phys;
113 u64 mem_size;
114 u64 io_bus;
115 u64 io_phys;
116 u64 io_size;
117};
118
119#define SET_LS_PCIE_INFO(x, num) \
120{ \
121 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
01cafced 122 x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
e4e8cb71
ML		 123 x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
124 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
125 x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
126 x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
127 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
128 x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
129 x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
130 x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
131 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
132 x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
133 x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
134 x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
135 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
136 x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
137 x.pci_num = num; \
138}
139
140#ifdef CONFIG_LS102XA
141#include <asm/arch/immap_ls102xa.h>
142
143/* PEX1/2 Misc Ports Status Register */
144#define LTSSM_STATE_SHIFT 20
e4e8cb71
ML		 145
146static int ls_pcie_link_state(struct ls_pcie *pcie)
147{
148 u32 state;
149 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
150
151 state = in_be32(&scfg->pexmscportsr[pcie->idx]);
152 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
153 if (state < LTSSM_PCIE_L0) {
154 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
155 return 0;
156 }
157
158 return 1;
159}
160#else
e4e8cb71
ML		 161static int ls_pcie_link_state(struct ls_pcie *pcie)
162{
163 u32 state;
164
00704590
ML		 165 state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
166 LTSSM_STATE_MASK;
167 if (state < LTSSM_PCIE_L0) {
168 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
169 return 0;
170 }
e4e8cb71 171
00704590 172 return 1;
e4e8cb71
ML		 173}
174#endif
175
176static int ls_pcie_link_up(struct ls_pcie *pcie)
177{
178 int state;
179 u32 cap;
180
181 state = ls_pcie_link_state(pcie);
182 if (state)
183 return state;
184
185 /* Try to download speed to gen1 */
186 cap = readl(pcie->dbi + PCIE_LINK_CAP);
187 writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
00704590
ML		 188 /*
189 * Notice: the following delay has critical impact on link training
190 * if too short (<30ms) the link doesn't get up.
191 */
192 mdelay(100);
e4e8cb71
ML		 193 state = ls_pcie_link_state(pcie);
194 if (state)
195 return state;
196
197 writel(cap, pcie->dbi + PCIE_LINK_CAP);
198
199 return 0;
200}
201
202static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
203{
204 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
205 pcie->dbi + PCIE_ATU_VIEWPORT);
206 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
207}
208
209static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
210{
211 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
212 pcie->dbi + PCIE_ATU_VIEWPORT);
213 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
214}
215
216static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
217 u64 phys, u64 bus_addr, pci_size_t size)
218{
219 writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
220 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
221 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
222 writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
223 writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
224 writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
225 writel(type, pcie->dbi + PCIE_ATU_CR1);
226 writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
227}
228
01cafced
ML		 229/* Use bar match mode and MEM type as default */
230static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
231 int bar, u64 phys)
232{
233 writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
234 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
235 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
236 writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
237 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
238 PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
239}
240
e4e8cb71
ML		 241static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
242{
243#ifdef DEBUG
244 int i;
245#endif
246
247 /* ATU 0 : OUTBOUND : CFG0 */
248 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
249 PCIE_ATU_TYPE_CFG0,
250 info->cfg0_phys,
251 0,
252 info->cfg0_size);
253 /* ATU 1 : OUTBOUND : CFG1 */
254 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
255 PCIE_ATU_TYPE_CFG1,
256 info->cfg1_phys,
257 0,
258 info->cfg1_size);
259 /* ATU 2 : OUTBOUND : MEM */
260 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
261 PCIE_ATU_TYPE_MEM,
262 info->mem_phys,
263 info->mem_bus,
264 info->mem_size);
265 /* ATU 3 : OUTBOUND : IO */
266 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
267 PCIE_ATU_TYPE_IO,
268 info->io_phys,
269 info->io_bus,
270 info->io_size);
271
272#ifdef DEBUG
273 for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
274 writel(PCIE_ATU_REGION_OUTBOUND | i,
275 pcie->dbi + PCIE_ATU_VIEWPORT);
276 debug("iATU%d:\n", i);
277 debug("\tLOWER PHYS 0x%08x\n",
278 readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
279 debug("\tUPPER PHYS 0x%08x\n",
280 readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
281 debug("\tLOWER BUS 0x%08x\n",
282 readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
283 debug("\tUPPER BUS 0x%08x\n",
284 readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
285 debug("\tLIMIT 0x%08x\n",
286 readl(pcie->dbi + PCIE_ATU_LIMIT));
287 debug("\tCR1 0x%08x\n",
288 readl(pcie->dbi + PCIE_ATU_CR1));
289 debug("\tCR2 0x%08x\n",
290 readl(pcie->dbi + PCIE_ATU_CR2));
291 }
292#endif
293}
294
295int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
296{
297 /* Do not skip controller */
298 return 0;
299}
300
301static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
302{
303 if (PCI_DEV(d) > 0)
304 return -EINVAL;
305
00704590
ML		 306 /* Controller does not support multi-function in RC mode */
307 if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
308 return -EINVAL;
309
e4e8cb71
ML		 310 return 0;
311}
312
313static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
314 int where, u32 *val)
315{
316 struct ls_pcie *pcie = hose->priv_data;
317 u32 busdev, *addr;
318
319 if (ls_pcie_addr_valid(hose, d)) {
320 *val = 0xffffffff;
321 return -EINVAL;
322 }
323
324 if (PCI_BUS(d) == hose->first_busno) {
325 addr = pcie->dbi + (where & ~0x3);
326 } else {
327 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
328 PCIE_ATU_DEV(PCI_DEV(d)) |
329 PCIE_ATU_FUNC(PCI_FUNC(d));
330
331 if (PCI_BUS(d) == hose->first_busno + 1) {
332 ls_pcie_cfg0_set_busdev(pcie, busdev);
333 addr = pcie->va_cfg0 + (where & ~0x3);
334 } else {
335 ls_pcie_cfg1_set_busdev(pcie, busdev);
336 addr = pcie->va_cfg1 + (where & ~0x3);
337 }
338 }
339
340 *val = readl(addr);
341
342 return 0;
343}
344
345static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
346 int where, u32 val)
347{
348 struct ls_pcie *pcie = hose->priv_data;
349 u32 busdev, *addr;
350
351 if (ls_pcie_addr_valid(hose, d))
352 return -EINVAL;
353
354 if (PCI_BUS(d) == hose->first_busno) {
355 addr = pcie->dbi + (where & ~0x3);
356 } else {
357 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
358 PCIE_ATU_DEV(PCI_DEV(d)) |
359 PCIE_ATU_FUNC(PCI_FUNC(d));
360
361 if (PCI_BUS(d) == hose->first_busno + 1) {
362 ls_pcie_cfg0_set_busdev(pcie, busdev);
363 addr = pcie->va_cfg0 + (where & ~0x3);
364 } else {
365 ls_pcie_cfg1_set_busdev(pcie, busdev);
366 addr = pcie->va_cfg1 + (where & ~0x3);
367 }
368 }
369
370 writel(val, addr);
371
372 return 0;
373}
374
375static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
376 struct ls_pcie_info *info)
377{
378 struct pci_controller *hose = &pcie->hose;
379 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
380
381 ls_pcie_setup_atu(pcie, info);
382
383 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
384
385 /* program correct class for RC */
00704590 386 writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
e4e8cb71
ML		 387 pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
388 PCI_CLASS_BRIDGE_PCI);
00704590
ML		 389#ifndef CONFIG_LS102XA
390 writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
391#endif
e4e8cb71
ML		 392}
393
01cafced
ML		 394static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
395 struct ls_pcie_info *info)
396{
397 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
398
399 /* ATU 0 : INBOUND : map BAR0 */
400 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
401 /* ATU 1 : INBOUND : map BAR1 */
402 phys += PCIE_BAR1_SIZE;
403 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
404 /* ATU 2 : INBOUND : map BAR2 */
405 phys += PCIE_BAR2_SIZE;
406 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
407 /* ATU 3 : INBOUND : map BAR4 */
408 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
409 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
410
411 /* ATU 0 : OUTBOUND : map 4G MEM */
412 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
413 PCIE_ATU_TYPE_MEM,
414 info->phys_base,
415 0,
416 4 * 1024 * 1024 * 1024ULL);
417}
418
419/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
420static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
421{
422 if (size < 4 * 1024)
423 return;
424
425 switch (bar) {
426 case 0:
427 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
428 break;
429 case 1:
430 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
431 break;
432 case 2:
433 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
434 writel(0, bar_base + PCI_BASE_ADDRESS_3);
435 break;
436 case 4:
437 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
438 writel(0, bar_base + PCI_BASE_ADDRESS_5);
439 break;
440 default:
441 break;
442 }
443}
444
445static void ls_pcie_ep_setup_bars(void *bar_base)
446{
447 /* BAR0 - 32bit - 4K configuration */
448 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
449 /* BAR1 - 32bit - 8K MSIX*/
450 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
451 /* BAR2 - 64bit - 4K MEM desciptor */
452 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
453 /* BAR4 - 64bit - 1M MEM*/
454 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
455}
456
457static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
458{
459 struct pci_controller *hose = &pcie->hose;
460 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
461 int sriov;
462
463 sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
464 if (sriov) {
465 int pf, vf;
466
467 for (pf = 0; pf < PCIE_PF_NUM; pf++) {
468 for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
469 writel(PCIE_LCTRL0_VAL(pf, vf),
470 pcie->dbi + PCIE_LUT_BASE +
471 PCIE_LUT_LCTRL0);
472 ls_pcie_ep_setup_bars(pcie->dbi);
473 ls_pcie_ep_setup_atu(pcie, info);
474 }
475 }
476
477 /* Disable CFG2 */
478 writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
479 } else {
480 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
481 ls_pcie_ep_setup_atu(pcie, info);
482 }
483}
484
e4e8cb71
ML		 485int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
486{
487 struct ls_pcie *pcie;
488 struct pci_controller *hose;
489 int num = dev - PCIE1;
490 pci_dev_t pdev = PCI_BDF(busno, 0, 0);
491 int i, linkup, ep_mode;
492 u8 header_type;
493 u16 temp16;
494
495 if (!is_serdes_configured(dev)) {
496 printf("PCIe%d: disabled\n", num + 1);
497 return busno;
498 }
499
500 pcie = malloc(sizeof(*pcie));
501 if (!pcie)
502 return busno;
503 memset(pcie, 0, sizeof(*pcie));
504
505 hose = &pcie->hose;
506 hose->priv_data = pcie;
507 hose->first_busno = busno;
508 pcie->idx = num;
509 pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
510 pcie->va_cfg0 = map_physmem(info->cfg0_phys,
511 info->cfg0_size,
512 MAP_NOCACHE);
513 pcie->va_cfg1 = map_physmem(info->cfg1_phys,
514 info->cfg1_size,
515 MAP_NOCACHE);
516
517 /* outbound memory */
518 pci_set_region(&hose->regions[0],
519 (pci_size_t)info->mem_bus,
520 (phys_size_t)info->mem_phys,
521 (pci_size_t)info->mem_size,
522 PCI_REGION_MEM);
523
524 /* outbound io */
525 pci_set_region(&hose->regions[1],
526 (pci_size_t)info->io_bus,
527 (phys_size_t)info->io_phys,
528 (pci_size_t)info->io_size,
529 PCI_REGION_IO);
530
531 /* System memory space */
532 pci_set_region(&hose->regions[2],
533 CONFIG_SYS_PCI_MEMORY_BUS,
534 CONFIG_SYS_PCI_MEMORY_PHYS,
535 CONFIG_SYS_PCI_MEMORY_SIZE,
536 PCI_REGION_SYS_MEMORY);
537
538 hose->region_count = 3;
539
540 for (i = 0; i < hose->region_count; i++)
541 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
542 i,
543 (u64)hose->regions[i].phys_start,
544 (u64)hose->regions[i].bus_start,
545 (u64)hose->regions[i].size,
546 hose->regions[i].flags);
547
548 pci_set_ops(hose,
549 pci_hose_read_config_byte_via_dword,
550 pci_hose_read_config_word_via_dword,
551 ls_pcie_read_config,
552 pci_hose_write_config_byte_via_dword,
553 pci_hose_write_config_word_via_dword,
554 ls_pcie_write_config);
555
556 pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
557 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
558 printf("PCIe%u: %s ", info->pci_num,
559 ep_mode ? "Endpoint" : "Root Complex");
560
01cafced
ML		 561 if (ep_mode)
562 ls_pcie_setup_ep(pcie, info);
563 else
564 ls_pcie_setup_ctrl(pcie, info);
565
e4e8cb71
ML		 566 linkup = ls_pcie_link_up(pcie);
567
568 if (!linkup) {
569 /* Let the user know there's no PCIe link */
570 printf("no link, regs @ 0x%lx\n", info->regs);
571 hose->last_busno = hose->first_busno;
572 return busno;
573 }
574
575 /* Print the negotiated PCIe link width */
00704590
ML		 576 pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
577 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
578 (temp16 & 0xf), info->regs);
e4e8cb71
ML		 579
580 if (ep_mode)
581 return busno;
582
e4e8cb71
ML		 583 pci_register_hose(hose);
584
585 hose->last_busno = pci_hose_scan(hose);
586
587 printf("PCIe%x: Bus %02x - %02x\n",
588 info->pci_num, hose->first_busno, hose->last_busno);
589
590 return hose->last_busno + 1;
591}
592
593int ls_pcie_init_board(int busno)
594{
595 struct ls_pcie_info info;
596
597#ifdef CONFIG_PCIE1
598 SET_LS_PCIE_INFO(info, 1);
599 busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
600#endif
601
602#ifdef CONFIG_PCIE2
603 SET_LS_PCIE_INFO(info, 2);
604 busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
605#endif
606
607#ifdef CONFIG_PCIE3
608 SET_LS_PCIE_INFO(info, 3);
609 busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
610#endif
611
612#ifdef CONFIG_PCIE4
613 SET_LS_PCIE_INFO(info, 4);
614 busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
615#endif
616
617 return busno;
618}
619
620void pci_init_board(void)
621{
622 ls_pcie_init_board(0);
623}
624
da419027
ML		 625#ifdef CONFIG_OF_BOARD_SETUP
626#include <libfdt.h>
627#include <fdt_support.h>
628
629static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
630 unsigned long ctrl_addr, enum srds_prtcl dev)
631{
632 int off;
633
634 off = fdt_node_offset_by_compat_reg(blob, pci_compat,
635 (phys_addr_t)ctrl_addr);
636 if (off < 0)
637 return;
638
639 if (!is_serdes_configured(dev))
640 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
641}
642
d42bd345 643void ft_pci_setup(void *blob, bd_t *bd)
da419027
ML		 644{
645 #ifdef CONFIG_PCIE1
646 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
647 #endif
648
649 #ifdef CONFIG_PCIE2
650 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
651 #endif
e4e8cb71
ML		 652
653 #ifdef CONFIG_PCIE3
654 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
655 #endif
656
657 #ifdef CONFIG_PCIE4
658 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
659 #endif
da419027
ML		 660}
661
662#else
d42bd345 663void ft_pci_setup(void *blob, bd_t *bd)
da419027
ML		 664{
665}
666#endif
70e52d21 667
44937214 668#ifdef CONFIG_LS2080A
70e52d21
SY		 669
670void pcie_set_available_streamids(void *blob, const char *pcie_path,
671 u32 *stream_ids, int count)
672{
673 int nodeoffset;
674 int i;
675
676 nodeoffset = fdt_path_offset(blob, pcie_path);
677 if (nodeoffset < 0) {
678 printf("\n%s: ERROR: unable to update PCIe node\n", __func__);
679 return;
680 }
681
682 /* for each stream ID, append to mmu-masters */
683 for (i = 0; i < count; i++) {
684 fdt_appendprop_u32(blob, nodeoffset, "available-stream-ids",
685 stream_ids[i]);
686 }
687}
688
689#define MAX_STREAM_IDS 4
690void fdt_fixup_smmu_pcie(void *blob)
691{
692 int count;
693 u32 stream_ids[MAX_STREAM_IDS];
6923b069 694 u32 ctlr_streamid = 0x300;
70e52d21
SY		 695
696 #ifdef CONFIG_PCIE1
697 /* PEX1 stream ID fixup */
698 count = FSL_PEX1_STREAM_ID_END - FSL_PEX1_STREAM_ID_START + 1;
699 alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
700 MAX_STREAM_IDS);
701 pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
6923b069
VS		 702 append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000",
703 &ctlr_streamid, 1);
70e52d21
SY		 704 #endif
705
706 #ifdef CONFIG_PCIE2
707 /* PEX2 stream ID fixup */
708 count = FSL_PEX2_STREAM_ID_END - FSL_PEX2_STREAM_ID_START + 1;
709 alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
710 MAX_STREAM_IDS);
711 pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
6923b069
VS		 712 append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000",
713 &ctlr_streamid, 1);
70e52d21
SY		 714 #endif
715
716 #ifdef CONFIG_PCIE3
717 /* PEX3 stream ID fixup */
718 count = FSL_PEX3_STREAM_ID_END - FSL_PEX3_STREAM_ID_START + 1;
719 alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
720 MAX_STREAM_IDS);
721 pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
6923b069
VS		 722 append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000",
723 &ctlr_streamid, 1);
70e52d21
SY		 724 #endif
725
726 #ifdef CONFIG_PCIE4
727 /* PEX4 stream ID fixup */
728 count = FSL_PEX4_STREAM_ID_END - FSL_PEX4_STREAM_ID_START + 1;
729 alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
730 MAX_STREAM_IDS);
731 pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);
6923b069
VS		 732 append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000",
733 &ctlr_streamid, 1);
70e52d21
SY		 734 #endif
735}
736#endif
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