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a7294aba | 1 | /* |
e809e747 | 2 | * Copyright 2017 NXP |
a7294aba HZ |
3 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
4 | * Layerscape PCIe driver | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef _PCIE_LAYERSCAPE_H_ | |
10 | #define _PCIE_LAYERSCAPE_H_ | |
11 | #include <pci.h> | |
9fa2a4fc | 12 | #include <dm.h> |
a7294aba HZ |
13 | |
14 | #ifndef CONFIG_SYS_PCI_MEMORY_BUS | |
15 | #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE | |
16 | #endif | |
17 | ||
18 | #ifndef CONFIG_SYS_PCI_MEMORY_PHYS | |
19 | #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE | |
20 | #endif | |
21 | ||
22 | #ifndef CONFIG_SYS_PCI_MEMORY_SIZE | |
23 | #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ | |
24 | #endif | |
25 | ||
26 | #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE | |
27 | #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR | |
28 | #endif | |
29 | ||
3d8553f0 HZ |
30 | #define PCIE_PHYS_SIZE 0x200000000 |
31 | #define LS2088A_PCIE_PHYS_SIZE 0x800000000 | |
32 | #define LS2088A_PCIE1_PHYS_ADDR 0x2000000000 | |
33 | ||
a7294aba HZ |
34 | /* iATU registers */ |
35 | #define PCIE_ATU_VIEWPORT 0x900 | |
36 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
37 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
38 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
39 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | |
40 | #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) | |
41 | #define PCIE_ATU_REGION_INDEX3 (0x3 << 0) | |
42 | #define PCIE_ATU_REGION_NUM 6 | |
43 | #define PCIE_ATU_CR1 0x904 | |
44 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
45 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
46 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
47 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
48 | #define PCIE_ATU_CR2 0x908 | |
49 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
50 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
51 | #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8) | |
52 | #define PCIE_ATU_LOWER_BASE 0x90C | |
53 | #define PCIE_ATU_UPPER_BASE 0x910 | |
54 | #define PCIE_ATU_LIMIT 0x914 | |
55 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
56 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
57 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
58 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
59 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
60 | ||
61 | /* DBI registers */ | |
62 | #define PCIE_SRIOV 0x178 | |
63 | #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ | |
64 | #define PCIE_DBI_RO_WR_EN 0x8bc | |
65 | ||
66 | #define PCIE_LINK_CAP 0x7c | |
67 | #define PCIE_LINK_SPEED_MASK 0xf | |
68 | #define PCIE_LINK_WIDTH_MASK 0x3f0 | |
69 | #define PCIE_LINK_STA 0x82 | |
70 | ||
71 | #define LTSSM_STATE_MASK 0x3f | |
72 | #define LTSSM_PCIE_L0 0x11 /* L0 state */ | |
73 | ||
74 | #define PCIE_DBI_SIZE 0x100000 /* 1M */ | |
75 | ||
76 | #define PCIE_LCTRL0_CFG2_ENABLE (1 << 31) | |
77 | #define PCIE_LCTRL0_VF(vf) ((vf) << 22) | |
78 | #define PCIE_LCTRL0_PF(pf) ((pf) << 16) | |
79 | #define PCIE_LCTRL0_VF_ACTIVE (1 << 21) | |
80 | #define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \ | |
81 | PCIE_LCTRL0_VF(vf) | \ | |
82 | ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \ | |
83 | PCIE_LCTRL0_CFG2_ENABLE) | |
84 | ||
85 | #define PCIE_NO_SRIOV_BAR_BASE 0x1000 | |
86 | ||
87 | #define PCIE_PF_NUM 2 | |
88 | #define PCIE_VF_NUM 64 | |
89 | ||
90 | #define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ | |
91 | #define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ | |
92 | #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ | |
93 | #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ | |
94 | ||
80afc63f ML |
95 | /* LUT registers */ |
96 | #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) | |
97 | #define PCIE_LUT_LDR(n) (0x804 + (n) * 8) | |
98 | #define PCIE_LUT_ENABLE (1 << 31) | |
99 | #define PCIE_LUT_ENTRY_COUNT 32 | |
100 | ||
101 | /* PF Controll registers */ | |
d170aca1 | 102 | #define PCIE_PF_CONFIG 0x14 |
80afc63f ML |
103 | #define PCIE_PF_VF_CTRL 0x7F8 |
104 | #define PCIE_PF_DBG 0x7FC | |
d170aca1 | 105 | #define PCIE_CONFIG_READY (1 << 0) |
80afc63f ML |
106 | |
107 | #define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) | |
108 | #define PCIE_SYS_BASE_ADDR 0x3400000 | |
109 | #define PCIE_CCSR_SIZE 0x0100000 | |
110 | ||
111 | /* CS2 */ | |
112 | #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ | |
113 | ||
114 | #define SVR_LS102XA 0 | |
115 | #define SVR_VAR_PER_SHIFT 8 | |
116 | #define SVR_LS102XA_MASK 0x700 | |
3d8553f0 HZ |
117 | #define SVR_LS2088A 0x870900 |
118 | #define SVR_LS2084A 0x870910 | |
119 | #define SVR_LS2048A 0x870920 | |
120 | #define SVR_LS2044A 0x870930 | |
ec8a7d77 SK |
121 | #define SVR_LS2081A 0x870918 |
122 | #define SVR_LS2041A 0x870914 | |
80afc63f ML |
123 | |
124 | /* LS1021a PCIE space */ | |
125 | #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL | |
126 | #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL | |
127 | ||
128 | /* LS1021a PEX1/2 Misc Ports Status Register */ | |
129 | #define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) | |
130 | #define LS1021_LTSSM_STATE_SHIFT 20 | |
131 | ||
132 | struct ls_pcie { | |
133 | int idx; | |
134 | struct list_head list; | |
135 | struct udevice *bus; | |
136 | struct fdt_resource dbi_res; | |
137 | struct fdt_resource lut_res; | |
138 | struct fdt_resource ctrl_res; | |
139 | struct fdt_resource cfg_res; | |
140 | void __iomem *dbi; | |
141 | void __iomem *lut; | |
142 | void __iomem *ctrl; | |
143 | void __iomem *cfg0; | |
144 | void __iomem *cfg1; | |
145 | bool big_endian; | |
146 | bool enabled; | |
147 | int next_lut_index; | |
148 | struct pci_controller hose; | |
149 | }; | |
150 | ||
151 | extern struct list_head ls_pcie_list; | |
152 | ||
a7294aba | 153 | #endif /* _PCIE_LAYERSCAPE_H_ */ |