[people/ms/u-boot.git] / drivers / pci / w83c553f.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
 * write protection (for flash) in function 0 of the chip.
 * Enabling function 1 (IDE controller of the chip.
 */

#include <common.h>
#include <config.h>

#include <asm/io.h>
#include <pci.h>

#include <w83c553f.h>

#define out8(addr,val)	do { \
			out_8((u8*) (addr),(val)); udelay(1); \
			} while (0)
#define out16(addr,val)	do { \
			out_be16((u16*) (addr),(val)); udelay(1); \
			} while (0)

extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];

void initialise_pic(void);
void initialise_dma(void);

void initialise_w83c553f(void)
{
	pci_dev_t devbusfn;
	unsigned char reg8;
	unsigned short reg16;
	unsigned int reg32;

	devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
	if (devbusfn == -1)
	{
		printf("Error: Cannot find W83C553F controller on any PCI bus.");
		return;
	}

	pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
	pci_write_config_word(devbusfn, PCI_COMMAND, reg16);

	pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
	/* 16 MB ISA memory space */
	reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
	reg8 &= ~IPADCR_MBE512;
	pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);

	pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
	/* switch off BIOS write protection */
	reg8 |= CSCR_UBIOSCSE;
	reg8 &= ~CSCR_BIOSWP;
	pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);

	/*
	 * Interrupt routing:
	 *  - IDE  -> IRQ 9/0
	 *  - INTA -> IRQ 10
	 *  - INTB -> IRQ 11
	 *  - INTC -> IRQ 14
	 *  - INTD -> IRQ 15
	 */
	pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
	pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);

	/*
	 * Read IDE bus offsets from function 1 device.
	 * We must unmask the LSB indicating that ist is an IO address.
	 */
	devbusfn |= PCI_BDF(0,0,1);

	/*
	 * Switch off legacy IRQ for IDE and IDE port 1.
	 */
	pci_write_config_byte(devbusfn, 0x09, 0x8F);

	pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
	reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
	pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);

	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
	ide_bus_offset[0] &= ~1;
#if CONFIG_SYS_IDE_MAXBUS > 1
	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
	ide_bus_offset[1] &= ~1;
#endif

	/*
	 * Enable function 1, IDE -> busmastering and IO space access
	 */
	pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
	pci_write_config_word(devbusfn, PCI_COMMAND, reg16);

	/*
	 * Initialise ISA interrupt controller
	 */
	initialise_pic();

	/*
	 * Initialise DMA controller
	 */
	initialise_dma();
}

void initialise_pic(void)
{
	out8(W83C553F_PIC1_ICW1, 0x11);
	out8(W83C553F_PIC1_ICW2, 0x08);
	out8(W83C553F_PIC1_ICW3, 0x04);
	out8(W83C553F_PIC1_ICW4, 0x01);
	out8(W83C553F_PIC1_OCW1, 0xfb);
	out8(W83C553F_PIC1_ELC, 0x20);

	out8(W83C553F_PIC2_ICW1, 0x11);
	out8(W83C553F_PIC2_ICW2, 0x08);
	out8(W83C553F_PIC2_ICW3, 0x02);
	out8(W83C553F_PIC2_ICW4, 0x01);
	out8(W83C553F_PIC2_OCW1, 0xff);
	out8(W83C553F_PIC2_ELC, 0xce);

	out8(W83C553F_TMR1_CMOD, 0x74);

	out8(W83C553F_PIC2_OCW1, 0x20);
	out8(W83C553F_PIC1_OCW1, 0x20);

	out8(W83C553F_PIC2_OCW1, 0x2b);
	out8(W83C553F_PIC1_OCW1, 0x2b);
}

void initialise_dma(void)
{
	unsigned int channel;
	unsigned int rvalue1, rvalue2;

	/* perform a H/W reset of the devices */

	out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
	out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);

	/* initialise all channels to a sane state */

	for (channel = 0; channel < 4; channel++) {
		/*
		 * dependent upon the channel, setup the specifics:
		 *
		 * demand
		 * address-increment
		 * autoinitialize-disable
		 * verify-transfer
		 */

		switch (channel) {
		case 0:
			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
			rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
			break;
		case 1:
			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
			break;
		case 2:
			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
			break;
		case 3:
			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
			break;
		default:
			rvalue1 = 0x00;
			rvalue2 = 0x00;
			break;
		}

		/* write to write mode registers */

		out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
		out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
	}

	/* enable all channels */

	out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
	out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
	/*
	 * initialize the global DMA configuration
	 *
	 * DACK# active low
	 * DREQ active high
	 * fixed priority
	 * channel group enable
	 */

	out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
	out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
}
Commit	Line	Data
1df49e27 WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <aheppel@sysgo.de>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Initialisation of the PCI-to-ISA bridge and disabling the BIOS
	26	* write protection (for flash) in function 0 of the chip.
	27	* Enabling function 1 (IDE controller of the chip.
	28	*/
	29
	30	#include <common.h>
	31	#include <config.h>
	32
1df49e27 WD	33	#include <asm/io.h>
	34	#include <pci.h>
	35
	36	#include <w83c553f.h>
	37
	38	#define out8(addr,val) do { \
	39	out_8((u8*) (addr),(val)); udelay(1); \
	40	} while (0)
	41	#define out16(addr,val) do { \
	42	out_be16((u16*) (addr),(val)); udelay(1); \
	43	} while (0)
	44
6d0f6bcf	45	extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
1df49e27 WD	46
	47	void initialise_pic(void);
	48	void initialise_dma(void);
	49
	50	void initialise_w83c553f(void)
	51	{
	52	pci_dev_t devbusfn;
	53	unsigned char reg8;
	54	unsigned short reg16;
	55	unsigned int reg32;
	56
	57	devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
	58	if (devbusfn == -1)
	59	{
	60	printf("Error: Cannot find W83C553F controller on any PCI bus.");
	61	return;
	62	}
	63
	64	pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
	65	reg16 \|= PCI_COMMAND_MASTER \| PCI_COMMAND_IO \| PCI_COMMAND_MEMORY;
	66	pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
	67
	68	pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
	69	/* 16 MB ISA memory space */
	70	reg8 \|= (IPADCR_IPATOM4 \| IPADCR_IPATOM5 \| IPADCR_IPATOM6 \| IPADCR_IPATOM7);
	71	reg8 &= ~IPADCR_MBE512;
	72	pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
	73
	74	pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
	75	/* switch off BIOS write protection */
	76	reg8 \|= CSCR_UBIOSCSE;
	77	reg8 &= ~CSCR_BIOSWP;
	78	pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
	79
	80	/*
	81	* Interrupt routing:
	82	* - IDE -> IRQ 9/0
	83	* - INTA -> IRQ 10
	84	* - INTB -> IRQ 11
	85	* - INTC -> IRQ 14
	86	* - INTD -> IRQ 15
	87	*/
	88	pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
	89	pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
	90
	91	/*
	92	* Read IDE bus offsets from function 1 device.
	93	* We must unmask the LSB indicating that ist is an IO address.
	94	*/
	95	devbusfn \|= PCI_BDF(0,0,1);
	96
	97	/*
	98	* Switch off legacy IRQ for IDE and IDE port 1.
	99	*/
	100	pci_write_config_byte(devbusfn, 0x09, 0x8F);
	101
	102	pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
	103	reg32 &= ~(IDECSR_LEGIRQ \| IDECSR_P1EN \| IDECSR_P1F16);
	104	pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
	105
	106	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
	107	ide_bus_offset[0] &= ~1;
6d0f6bcf	108	#if CONFIG_SYS_IDE_MAXBUS > 1
1df49e27 WD	109	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
	110	ide_bus_offset[1] &= ~1;
	111	#endif
	112
	113	/*
	114	* Enable function 1, IDE -> busmastering and IO space access
	115	*/
	116	pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
	117	reg16 \|= PCI_COMMAND_MASTER \| PCI_COMMAND_IO;
	118	pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
	119
	120	/*
	121	* Initialise ISA interrupt controller
	122	*/
	123	initialise_pic();
	124
	125	/*
	126	* Initialise DMA controller
	127	*/
	128	initialise_dma();
	129	}
	130
	131	void initialise_pic(void)
	132	{
	133	out8(W83C553F_PIC1_ICW1, 0x11);
	134	out8(W83C553F_PIC1_ICW2, 0x08);
	135	out8(W83C553F_PIC1_ICW3, 0x04);
	136	out8(W83C553F_PIC1_ICW4, 0x01);
	137	out8(W83C553F_PIC1_OCW1, 0xfb);
	138	out8(W83C553F_PIC1_ELC, 0x20);
	139
	140	out8(W83C553F_PIC2_ICW1, 0x11);
	141	out8(W83C553F_PIC2_ICW2, 0x08);
	142	out8(W83C553F_PIC2_ICW3, 0x02);
	143	out8(W83C553F_PIC2_ICW4, 0x01);
	144	out8(W83C553F_PIC2_OCW1, 0xff);
	145	out8(W83C553F_PIC2_ELC, 0xce);
	146
	147	out8(W83C553F_TMR1_CMOD, 0x74);
	148
	149	out8(W83C553F_PIC2_OCW1, 0x20);
	150	out8(W83C553F_PIC1_OCW1, 0x20);
	151
	152	out8(W83C553F_PIC2_OCW1, 0x2b);
	153	out8(W83C553F_PIC1_OCW1, 0x2b);
	154	}
	155
	156	void initialise_dma(void)
	157	{
	158	unsigned int channel;
	159	unsigned int rvalue1, rvalue2;
	160
	161	/* perform a H/W reset of the devices */
	162
	163	out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
	164	out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
	165
	166	/* initialise all channels to a sane state */
	167
	168	for (channel = 0; channel < 4; channel++) {
	169	/*
	170	* dependent upon the channel, setup the specifics:
	171	*
	172	* demand
173	* address-increment
174	* autoinitialize-disable
175	* verify-transfer
176	*/
177
178	switch (channel) {
179	case 0:
180	rvalue1 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH0SEL\|W83C553F_MODE_TT_VERIFY);
181	rvalue2 = (W83C553F_MODE_TM_CASCADE\|W83C553F_MODE_CH0SEL);
182	break;
53677ef1	183	case 1:
1df49e27 WD	184	rvalue1 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH1SEL\|W83C553F_MODE_TT_VERIFY);
	185	rvalue2 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH1SEL\|W83C553F_MODE_TT_VERIFY);
	186	break;
	187	case 2:
	188	rvalue1 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH2SEL\|W83C553F_MODE_TT_VERIFY);
	189	rvalue2 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH2SEL\|W83C553F_MODE_TT_VERIFY);
	190	break;
	191	case 3:
	192	rvalue1 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH3SEL\|W83C553F_MODE_TT_VERIFY);
	193	rvalue2 = (W83C553F_MODE_TM_DEMAND\|W83C553F_MODE_CH3SEL\|W83C553F_MODE_TT_VERIFY);
	194	break;
	195	default:
	196	rvalue1 = 0x00;
	197	rvalue2 = 0x00;
	198	break;
	199	}
	200
	201	/* write to write mode registers */
	202
	203	out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
	204	out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
	205	}
	206
	207	/* enable all channels */
	208
	209	out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
	210	out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
	211	/*
	212	* initialize the global DMA configuration
	213	*
	214	* DACK# active low
	215	* DREQ active high
	216	* fixed priority
	217	* channel group enable
	218	*/
	219
	220	out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
	221	out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
	222	}