[people/ms/u-boot.git] / drivers / pinctrl / nxp / pinctrl-imx.c

/*
 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mapmem.h>
#include <linux/io.h>
#include <linux/err.h>
#include <dm.h>
#include <dm/pinctrl.h>

#include "pinctrl-imx.h"

DECLARE_GLOBAL_DATA_PTR;

static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
	struct imx_pinctrl_soc_info *info = priv->info;
	int node = dev_of_offset(config);
	const struct fdt_property *prop;
	u32 *pin_data;
	int npins, size, pin_size;
	int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
	int i, j = 0;

	dev_dbg(dev, "%s: %s\n", __func__, config->name);

	if (info->flags & SHARE_MUX_CONF_REG)
		pin_size = SHARE_FSL_PIN_SIZE;
	else
		pin_size = FSL_PIN_SIZE;

	prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
	if (!prop) {
		dev_err(dev, "No fsl,pins property in node %s\n", config->name);
		return -EINVAL;
	}

	if (!size || size % pin_size) {
		dev_err(dev, "Invalid fsl,pins property in node %s\n",
			config->name);
		return -EINVAL;
	}

	pin_data = devm_kzalloc(dev, size, 0);
	if (!pin_data)
		return -ENOMEM;

	if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
				 pin_data, size >> 2)) {
		dev_err(dev, "Error reading pin data.\n");
		devm_kfree(dev, pin_data);
		return -EINVAL;
	}

	npins = size / pin_size;

	/*
	 * Refer to linux documentation for details:
	 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
	 */
	for (i = 0; i < npins; i++) {
		mux_reg = pin_data[j++];

		if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
			mux_reg = -1;

		if (info->flags & SHARE_MUX_CONF_REG) {
			conf_reg = mux_reg;
		} else {
			conf_reg = pin_data[j++];
			if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
				conf_reg = -1;
		}

		if ((mux_reg == -1) || (conf_reg == -1)) {
			dev_err(dev, "Error mux_reg or conf_reg\n");
			devm_kfree(dev, pin_data);
			return -EINVAL;
		}

		input_reg = pin_data[j++];
		mux_mode = pin_data[j++];
		input_val = pin_data[j++];
		config_val = pin_data[j++];

		dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
			"mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
			mux_reg, conf_reg, input_reg, mux_mode, input_val,
			config_val);

		if (config_val & IMX_PAD_SION)
			mux_mode |= IOMUXC_CONFIG_SION;

		config_val &= ~IMX_PAD_SION;

		/* Set Mux */
		if (info->flags & SHARE_MUX_CONF_REG) {
			clrsetbits_le32(info->base + mux_reg, info->mux_mask,
					mux_mode << mux_shift);
		} else {
			writel(mux_mode, info->base + mux_reg);
		}

		dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
			mux_mode);

		/*
		 * Set select input
		 *
		 * If the select input value begins with 0xff, it's a quirky
		 * select input and the value should be interpreted as below.
		 *     31     23      15      7        0
		 *     | 0xff | shift | width | select |
		 * It's used to work around the problem that the select
		 * input for some pin is not implemented in the select
		 * input register but in some general purpose register.
		 * We encode the select input value, width and shift of
		 * the bit field into input_val cell of pin function ID
		 * in device tree, and then decode them here for setting
		 * up the select input bits in general purpose register.
		 */

		if (input_val >> 24 == 0xff) {
			u32 val = input_val;
			u8 select = val & 0xff;
			u8 width = (val >> 8) & 0xff;
			u8 shift = (val >> 16) & 0xff;
			u32 mask = ((1 << width) - 1) << shift;
			/*
			 * The input_reg[i] here is actually some IOMUXC general
			 * purpose register, not regular select input register.
			 */
			val = readl(info->base + input_reg);
			val &= ~mask;
			val |= select << shift;
			writel(val, info->base + input_reg);
		} else if (input_reg) {
			/*
			 * Regular select input register can never be at offset
			 * 0, and we only print register value for regular case.
			 */
			if (info->input_sel_base)
				writel(input_val, info->input_sel_base +
				       input_reg);
			else
				writel(input_val, info->base + input_reg);

			dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
				input_reg, input_val);
		}

		/* Set config */
		if (!(config_val & IMX_NO_PAD_CTL)) {
			if (info->flags & SHARE_MUX_CONF_REG) {
				clrsetbits_le32(info->base + conf_reg,
						~info->mux_mask, config_val);
			} else {
				writel(config_val, info->base + conf_reg);
			}

			dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
				conf_reg, config_val);
		}
	}

	devm_kfree(dev, pin_data);

	return 0;
}

const struct pinctrl_ops imx_pinctrl_ops  = {
	.set_state = imx_pinctrl_set_state,
};

int imx_pinctrl_probe(struct udevice *dev,
		      struct imx_pinctrl_soc_info *info)
{
	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
	int node = dev_of_offset(dev), ret;
	struct fdtdec_phandle_args arg;
	fdt_addr_t addr;
	fdt_size_t size;

	if (!info) {
		dev_err(dev, "wrong pinctrl info\n");
		return -EINVAL;
	}

	priv->dev = dev;
	priv->info = info;

	addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
				    &size);

	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	info->base = map_sysmem(addr, size);
	if (!info->base)
		return -ENOMEM;
	priv->info = info;

	info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
	/*
	 * Refer to linux documentation for details:
	 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
	 */
	if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
		ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
						     node, "fsl,input-sel",
						     NULL, 0, 0, &arg);
		if (ret) {
			dev_err(dev, "iomuxc fsl,input-sel property not found\n");
			return -EINVAL;
		}

		addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
					    &size);
		if (addr == FDT_ADDR_T_NONE)
			return -EINVAL;

		info->input_sel_base = map_sysmem(addr, size);
		if (!info->input_sel_base)
			return -ENOMEM;
	}

	dev_dbg(dev, "initialized IMX pinctrl driver\n");

	return 0;
}

int imx_pinctrl_remove(struct udevice *dev)
{
	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
	struct imx_pinctrl_soc_info *info = priv->info;

	if (info->input_sel_base)
		unmap_sysmem(info->input_sel_base);
	if (info->base)
		unmap_sysmem(info->base);

	return 0;
}
Commit	Line	Data
745df68d PF	1	/*
	2	* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <mapmem.h>
	9	#include <linux/io.h>
	10	#include <linux/err.h>
9d922450	11	#include <dm.h>
745df68d PF	12	#include <dm/pinctrl.h>
	13
	14	#include "pinctrl-imx.h"
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	static int imx_pinctrl_set_state(struct udevice dev, struct udevice config)
	19	{
	20	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
	21	struct imx_pinctrl_soc_info *info = priv->info;
e160f7d4	22	int node = dev_of_offset(config);
745df68d PF	23	const struct fdt_property *prop;
	24	u32 *pin_data;
	25	int npins, size, pin_size;
	26	int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
4aa9d4d0	27	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
745df68d PF	28	int i, j = 0;
	29
	30	dev_dbg(dev, "%s: %s\n", __func__, config->name);
	31
	32	if (info->flags & SHARE_MUX_CONF_REG)
	33	pin_size = SHARE_FSL_PIN_SIZE;
	34	else
	35	pin_size = FSL_PIN_SIZE;
	36
	37	prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
	38	if (!prop) {
	39	dev_err(dev, "No fsl,pins property in node %s\n", config->name);
	40	return -EINVAL;
	41	}
	42
	43	if (!size \|\| size % pin_size) {
	44	dev_err(dev, "Invalid fsl,pins property in node %s\n",
	45	config->name);
	46	return -EINVAL;
	47	}
	48
	49	pin_data = devm_kzalloc(dev, size, 0);
	50	if (!pin_data)
	51	return -ENOMEM;
	52
	53	if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
	54	pin_data, size >> 2)) {
	55	dev_err(dev, "Error reading pin data.\n");
c1d1e9d6	56	devm_kfree(dev, pin_data);
745df68d PF	57	return -EINVAL;
	58	}
	59
	60	npins = size / pin_size;
	61
	62	/*
	63	* Refer to linux documentation for details:
	64	* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
	65	*/
	66	for (i = 0; i < npins; i++) {
	67	mux_reg = pin_data[j++];
	68
	69	if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
	70	mux_reg = -1;
	71
	72	if (info->flags & SHARE_MUX_CONF_REG) {
	73	conf_reg = mux_reg;
	74	} else {
	75	conf_reg = pin_data[j++];
	76	if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
	77	conf_reg = -1;
	78	}
	79
	80	if ((mux_reg == -1) \|\| (conf_reg == -1)) {
	81	dev_err(dev, "Error mux_reg or conf_reg\n");
c1d1e9d6	82	devm_kfree(dev, pin_data);
745df68d PF	83	return -EINVAL;
	84	}
	85
	86	input_reg = pin_data[j++];
	87	mux_mode = pin_data[j++];
	88	input_val = pin_data[j++];
	89	config_val = pin_data[j++];
	90
	91	dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
	92	"mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
	93	mux_reg, conf_reg, input_reg, mux_mode, input_val,
	94	config_val);
	95
	96	if (config_val & IMX_PAD_SION)
	97	mux_mode \|= IOMUXC_CONFIG_SION;
	98
	99	config_val &= ~IMX_PAD_SION;
	100
	101	/* Set Mux */
	102	if (info->flags & SHARE_MUX_CONF_REG) {
4aa9d4d0 PF	103	clrsetbits_le32(info->base + mux_reg, info->mux_mask,
4aa9d4d0 PF	104	mux_mode << mux_shift);
745df68d PF	105	} else {
	106	writel(mux_mode, info->base + mux_reg);
	107	}
	108
	109	dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
	110	mux_mode);
	111
	112	/*
	113	* Set select input
	114	*
	115	* If the select input value begins with 0xff, it's a quirky
	116	* select input and the value should be interpreted as below.
	117	* 31 23 15 7 0
	118	* \| 0xff \| shift \| width \| select \|
	119	* It's used to work around the problem that the select
	120	* input for some pin is not implemented in the select
	121	* input register but in some general purpose register.
	122	* We encode the select input value, width and shift of
	123	* the bit field into input_val cell of pin function ID
	124	* in device tree, and then decode them here for setting
	125	* up the select input bits in general purpose register.
	126	*/
	127
	128	if (input_val >> 24 == 0xff) {
	129	u32 val = input_val;
	130	u8 select = val & 0xff;
	131	u8 width = (val >> 8) & 0xff;
	132	u8 shift = (val >> 16) & 0xff;
	133	u32 mask = ((1 << width) - 1) << shift;
	134	/*
	135	* The input_reg[i] here is actually some IOMUXC general
	136	* purpose register, not regular select input register.
	137	*/
	138	val = readl(info->base + input_reg);
	139	val &= ~mask;
	140	val \|= select << shift;
	141	writel(val, info->base + input_reg);
	142	} else if (input_reg) {
	143	/*
	144	* Regular select input register can never be at offset
	145	* 0, and we only print register value for regular case.
	146	*/
	147	if (info->input_sel_base)
	148	writel(input_val, info->input_sel_base +
	149	input_reg);
	150	else
	151	writel(input_val, info->base + input_reg);
	152
	153	dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
	154	input_reg, input_val);
	155	}
	156
	157	/* Set config */
	158	if (!(config_val & IMX_NO_PAD_CTL)) {
	159	if (info->flags & SHARE_MUX_CONF_REG) {
4aa9d4d0	160	clrsetbits_le32(info->base + conf_reg,
63fbc59b	161	~info->mux_mask, config_val);
745df68d PF	162	} else {
	163	writel(config_val, info->base + conf_reg);
	164	}
	165
	166	dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
	167	conf_reg, config_val);
	168	}
	169	}
	170
c1d1e9d6 PF	171	devm_kfree(dev, pin_data);
c1d1e9d6 PF	172
745df68d PF	173	return 0;
	174	}
	175
	176	const struct pinctrl_ops imx_pinctrl_ops = {
	177	.set_state = imx_pinctrl_set_state,
	178	};
	179
	180	int imx_pinctrl_probe(struct udevice *dev,
	181	struct imx_pinctrl_soc_info *info)
	182	{
	183	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
e160f7d4	184	int node = dev_of_offset(dev), ret;
745df68d PF	185	struct fdtdec_phandle_args arg;
	186	fdt_addr_t addr;
	187	fdt_size_t size;
	188
	189	if (!info) {
	190	dev_err(dev, "wrong pinctrl info\n");
	191	return -EINVAL;
	192	}
	193
	194	priv->dev = dev;
	195	priv->info = info;
	196
e160f7d4 SG	197	addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
e160f7d4 SG	198	&size);
745df68d PF	199
	200	if (addr == FDT_ADDR_T_NONE)
	201	return -EINVAL;
	202
	203	info->base = map_sysmem(addr, size);
	204	if (!info->base)
	205	return -ENOMEM;
	206	priv->info = info;
	207
4aa9d4d0	208	info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
745df68d PF	209	/*
	210	* Refer to linux documentation for details:
	211	* Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
	212	*/
	213	if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
	214	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
	215	node, "fsl,input-sel",
	216	NULL, 0, 0, &arg);
	217	if (ret) {
	218	dev_err(dev, "iomuxc fsl,input-sel property not found\n");
	219	return -EINVAL;
	220	}
	221
	222	addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
	223	&size);
	224	if (addr == FDT_ADDR_T_NONE)
	225	return -EINVAL;
	226
	227	info->input_sel_base = map_sysmem(addr, size);
	228	if (!info->input_sel_base)
	229	return -ENOMEM;
	230	}
	231
5a6f8d7b	232	dev_dbg(dev, "initialized IMX pinctrl driver\n");
745df68d PF	233
	234	return 0;
	235	}
	236
	237	int imx_pinctrl_remove(struct udevice *dev)
	238	{
	239	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
	240	struct imx_pinctrl_soc_info *info = priv->info;
	241
	242	if (info->input_sel_base)
	243	unmap_sysmem(info->input_sel_base);
	244	if (info->base)
	245	unmap_sysmem(info->base);
	246
	247	return 0;
	248	}