[people/ms/u-boot.git] / drivers / pinctrl / renesas / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/stringify.h>

enum {
	PINMUX_TYPE_NONE,
	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
};

#define SH_PFC_PIN_CFG_INPUT		(1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT		(1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP		(1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN	(1 << 3)
#define SH_PFC_PIN_CFG_IO_VOLTAGE	(1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH	(1 << 5)
#define SH_PFC_PIN_CFG_NO_GPIO		(1 << 31)

struct sh_pfc_pin {
	u16 pin;
	u16 enum_id;
	const char *name;
	unsigned int configs;
};

#define SH_PFC_PIN_GROUP(n)				\
	{						\
		.name = #n,				\
		.pins = n##_pins,			\
		.mux = n##_mux,				\
		.nr_pins = ARRAY_SIZE(n##_pins),	\
	}

struct sh_pfc_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int *mux;
	unsigned int nr_pins;
};

/*
 * Using union vin_data saves memory occupied by the VIN data pins.
 * VIN_DATA_PIN_GROUP() is  a macro  used  to describe the VIN pin groups
 * in this case.
 */
#define VIN_DATA_PIN_GROUP(n, s)				\
	{							\
		.name = #n#s,					\
		.pins = n##_pins.data##s,			\
		.mux = n##_mux.data##s,				\
		.nr_pins = ARRAY_SIZE(n##_pins.data##s),	\
	}

union vin_data {
	unsigned int data24[24];
	unsigned int data20[20];
	unsigned int data16[16];
	unsigned int data12[12];
	unsigned int data10[10];
	unsigned int data8[8];
	unsigned int data4[4];
};

#define SH_PFC_FUNCTION(n)				\
	{						\
		.name = #n,				\
		.groups = n##_groups,			\
		.nr_groups = ARRAY_SIZE(n##_groups),	\
	}

struct sh_pfc_function {
	const char *name;
	const char * const *groups;
	unsigned int nr_groups;
};

struct pinmux_func {
	u16 enum_id;
	const char *name;
};

struct pinmux_cfg_reg {
	u32 reg;
	u8 reg_width, field_width;
	const u16 *enum_ids;
	const u8 *var_field_width;
};

/*
 * Describe a config register consisting of several fields of the same width
 *   - name: Register name (unused, for documentation purposes only)
 *   - r: Physical register address
 *   - r_width: Width of the register (in bits)
 *   - f_width: Width of the fixed-width register fields (in bits)
 * This macro must be followed by initialization data: For each register field
 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
 * one for each possible combination of the register field bit values.
 */
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])

/*
 * Describe a config register consisting of several fields of different widths
 *   - name: Register name (unused, for documentation purposes only)
 *   - r: Physical register address
 *   - r_width: Width of the register (in bits)
 *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),
 *                          From left to right (i.e. MSB to LSB)
 * This macro must be followed by initialization data: For each register field
 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
 * one for each possible combination of the register field bit values.
 */
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.var_field_width = (const u8 [r_width]) \
		{ var_fw0, var_fwn, 0 }, \
	.enum_ids = (const u16 [])

struct pinmux_drive_reg_field {
	u16 pin;
	u8 offset;
	u8 size;
};

struct pinmux_drive_reg {
	u32 reg;
	const struct pinmux_drive_reg_field fields[8];
};

#define PINMUX_DRIVE_REG(name, r) \
	.reg = r, \
	.fields =

struct pinmux_data_reg {
	u32 reg;
	u8 reg_width;
	const u16 *enum_ids;
};

/*
 * Describe a data register
 *   - name: Register name (unused, for documentation purposes only)
 *   - r: Physical register address
 *   - r_width: Width of the register (in bits)
 * This macro must be followed by initialization data: For each register bit
 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
 */
#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (const u16 [r_width]) \

struct pinmux_irq {
	const short *gpios;
};

/*
 * Describe the mapping from GPIOs to a single IRQ
 *   - ids...: List of GPIOs that are mapped to the same IRQ
 */
#define PINMUX_IRQ(ids...)			   \
	{ .gpios = (const short []) { ids, -1 } }

struct pinmux_range {
	u16 begin;
	u16 end;
	u16 force;
};

struct sh_pfc_bias_info {
	u16 pin;
	u16 reg : 11;
	u16 bit : 5;
};

struct sh_pfc_pin_range;

struct sh_pfc {
	struct device *dev;
	const struct sh_pfc_soc_info *info;

	void *regs;

	struct sh_pfc_pin_range *ranges;
	unsigned int nr_ranges;

	unsigned int nr_gpio_pins;

	struct sh_pfc_chip *gpio;
};

struct sh_pfc_soc_operations {
	int (*init)(struct sh_pfc *pfc);
	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
			 unsigned int bias);
	int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
};

struct sh_pfc_soc_info {
	const char *name;
	const struct sh_pfc_soc_operations *ops;

	struct pinmux_range input;
	struct pinmux_range output;
	struct pinmux_range function;

	const struct sh_pfc_pin *pins;
	unsigned int nr_pins;
	const struct sh_pfc_pin_group *groups;
	unsigned int nr_groups;
	const struct sh_pfc_function *functions;
	unsigned int nr_functions;

	const struct pinmux_cfg_reg *cfg_regs;
	const struct pinmux_drive_reg *drive_regs;
	const struct pinmux_data_reg *data_regs;

	const u16 *pinmux_data;
	unsigned int pinmux_data_size;

	const struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	u32 unlock_reg;
};

u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
const struct sh_pfc_bias_info *
sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
			unsigned int num, unsigned int pin);
int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);

extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
/* -----------------------------------------------------------------------------
 * Helper macros to create pin and port lists
 */

/*
 * sh_pfc_soc_info pinmux_data array macros
 */

/*
 * Describe generic pinmux data
 *   - data_or_mark: *_DATA or *_MARK enum ID
 *   - ids...: List of enum IDs to associate with data_or_mark
 */
#define PINMUX_DATA(data_or_mark, ids...)	data_or_mark, ids, 0

/*
 * Describe a pinmux configuration without GPIO function that needs
 * configuration in a Peripheral Function Select Register (IPSR)
 *   - ipsr: IPSR field (unused, for documentation purposes only)
 *   - fn: Function name, referring to a field in the IPSR
 */
#define PINMUX_IPSR_NOGP(ipsr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn)

/*
 * Describe a pinmux configuration with GPIO function that needs configuration
 * in both a Peripheral Function Select Register (IPSR) and in a
 * GPIO/Peripheral Function Select Register (GPSR)
 *   - ipsr: IPSR field
 *   - fn: Function name, also referring to the IPSR field
 */
#define PINMUX_IPSR_GPSR(ipsr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)

/*
 * Describe a pinmux configuration without GPIO function that needs
 * configuration in a Peripheral Function Select Register (IPSR), and where the
 * pinmux function has a representation in a Module Select Register (MOD_SEL).
 *   - ipsr: IPSR field (unused, for documentation purposes only)
 *   - fn: Function name, also referring to the IPSR field
 *   - msel: Module selector
 */
#define PINMUX_IPSR_NOGM(ipsr, fn, msel)				\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)

/*
 * Describe a pinmux configuration with GPIO function where the pinmux function
 * has no representation in a Peripheral Function Select Register (IPSR), but
 * instead solely depends on a group selection.
 *   - gpsr: GPSR field
 *   - fn: Function name, also referring to the GPSR field
 *   - gsel: Group selector
 */
#define PINMUX_IPSR_NOFN(gpsr, fn, gsel)				\
	PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)

/*
 * Describe a pinmux configuration with GPIO function that needs configuration
 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
 * Function Select Register (GPSR), and where the pinmux function has a
 * representation in a Module Select Register (MOD_SEL).
 *   - ipsr: IPSR field
 *   - fn: Function name, also referring to the IPSR field
 *   - msel: Module selector
 */
#define PINMUX_IPSR_MSEL(ipsr, fn, msel)				\
	PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)

/*
 * Describe a pinmux configuration for a single-function pin with GPIO
 * capability.
 *   - fn: Function name
 */
#define PINMUX_SINGLE(fn)						\
	PINMUX_DATA(fn##_MARK, FN_##fn)

/*
 * GP port style (32 ports banks)
 */

#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg)				\
	fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx)	PORT_GP_CFG_1(bank, pin, fn, sfx, 0)

#define PORT_GP_CFG_4(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx)	PORT_GP_CFG_4(bank, fn, sfx, 0)

#define PORT_GP_CFG_6(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_4(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
#define PORT_GP_6(bank, fn, sfx)	PORT_GP_CFG_6(bank, fn, sfx, 0)

#define PORT_GP_CFG_8(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_4(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
#define PORT_GP_8(bank, fn, sfx)	PORT_GP_CFG_8(bank, fn, sfx, 0)

#define PORT_GP_CFG_9(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_8(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
#define PORT_GP_9(bank, fn, sfx)	PORT_GP_CFG_9(bank, fn, sfx, 0)

#define PORT_GP_CFG_10(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_9(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
#define PORT_GP_10(bank, fn, sfx)	PORT_GP_CFG_10(bank, fn, sfx, 0)

#define PORT_GP_CFG_12(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_10(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx)	PORT_GP_CFG_12(bank, fn, sfx, 0)

#define PORT_GP_CFG_14(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_12(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 12, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx)	PORT_GP_CFG_14(bank, fn, sfx, 0)

#define PORT_GP_CFG_15(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_14(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
#define PORT_GP_15(bank, fn, sfx)	PORT_GP_CFG_15(bank, fn, sfx, 0)

#define PORT_GP_CFG_16(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_15(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
#define PORT_GP_16(bank, fn, sfx)	PORT_GP_CFG_16(bank, fn, sfx, 0)

#define PORT_GP_CFG_17(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_16(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
#define PORT_GP_17(bank, fn, sfx)	PORT_GP_CFG_17(bank, fn, sfx, 0)

#define PORT_GP_CFG_18(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_17(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx)	PORT_GP_CFG_18(bank, fn, sfx, 0)

#define PORT_GP_CFG_20(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_18(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
#define PORT_GP_20(bank, fn, sfx)	PORT_GP_CFG_20(bank, fn, sfx, 0)

#define PORT_GP_CFG_21(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_20(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx)	PORT_GP_CFG_21(bank, fn, sfx, 0)

#define PORT_GP_CFG_22(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_18(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
#define PORT_GP_22(bank, fn, sfx)	PORT_GP_CFG_22(bank, fn, sfx, 0)

#define PORT_GP_CFG_23(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_21(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
#define PORT_GP_23(bank, fn, sfx)	PORT_GP_CFG_23(bank, fn, sfx, 0)

#define PORT_GP_CFG_24(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_23(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
#define PORT_GP_24(bank, fn, sfx)	PORT_GP_CFG_24(bank, fn, sfx, 0)

#define PORT_GP_CFG_26(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_24(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx)	PORT_GP_CFG_26(bank, fn, sfx, 0)

#define PORT_GP_CFG_28(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_26(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 26, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx)	PORT_GP_CFG_28(bank, fn, sfx, 0)

#define PORT_GP_CFG_29(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_28(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
#define PORT_GP_29(bank, fn, sfx)	PORT_GP_CFG_29(bank, fn, sfx, 0)

#define PORT_GP_CFG_30(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_29(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx)	PORT_GP_CFG_30(bank, fn, sfx, 0)

#define PORT_GP_CFG_32(bank, fn, sfx, cfg)				\
	PORT_GP_CFG_30(bank, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg),				\
	PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx)	PORT_GP_CFG_32(bank, fn, sfx, 0)

#define PORT_GP_32_REV(bank, fn, sfx)					\
	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)

/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx, cfg)	name##_##sfx
#define GP_ALL(str)			CPU_ALL_PORT(_GP_ALL, str)

/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx, cfg)				\
	{								\
		.pin = (bank * 32) + _pin,				\
		.name = __stringify(_name),				\
		.enum_id = _name##_DATA,				\
		.configs = cfg,						\
	}
#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO, unused)

/* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx, cfg)	PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL()		CPU_ALL_PORT(_GP_DATA, unused)

/*
 * PORT style (linear pin space)
 */

#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)

#define PORT_10(pn, fn, pfx, sfx)					  \
	PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),	  \
	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),	  \
	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),	  \
	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),	  \
	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)

#define PORT_90(pn, fn, pfx, sfx)					  \
	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
	PORT_10(pn+90, fn, pfx##9, sfx)

/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
#define _PORT_ALL(pn, pfx, sfx)		pfx##_##sfx
#define PORT_ALL(str)			CPU_ALL_PORT(_PORT_ALL, PORT, str)

/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
#define PINMUX_GPIO(_pin)						\
	[GPIO_##_pin] = {						\
		.pin = (u16)-1,						\
		.name = __stringify(GPIO_##_pin),			\
		.enum_id = _pin##_DATA,					\
	}

/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(_pin, cfgs)					\
	{								\
		.pin = _pin,						\
		.name = __stringify(PORT##_pin),			\
		.enum_id = PORT##_pin##_DATA,				\
		.configs = cfgs,					\
	}

/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED(row, col, _name)				\
	{								\
		.pin = PIN_NUMBER(row, col),				\
		.name = __stringify(PIN_##_name),			\
		.configs = SH_PFC_PIN_CFG_NO_GPIO,			\
	}

/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs)			\
	{								\
		.pin = PIN_NUMBER(row, col),				\
		.name = __stringify(PIN_##_name),			\
		.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs,		\
	}

/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 *		     PORT_name_OUT, PORT_name_IN marks
 */
#define _PORT_DATA(pn, pfx, sfx)					\
	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,			\
		    PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL()		CPU_ALL_PORT(_PORT_DATA, , unused)

/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark)			\
	[gpio - (base)] = {						\
		.name = __stringify(gpio),				\
		.enum_id = data_or_mark,				\
	}
#define GPIO_FN(str)							\
	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)

/*
 * PORTnCR helper macro for SH-Mobile/R-Mobile
 */
#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
			/* PULMD[1:0], handled by .set_bias() */	\
			0, 0, 0, 0,					\
			/* IE and OE */					\
			0, PORT##nr##_OUT, PORT##nr##_IN, 0,		\
			/* SEC, not supported */			\
			0, 0,						\
			/* PTMD[2:0] */					\
			PORT##nr##_FN0, PORT##nr##_FN1,			\
			PORT##nr##_FN2, PORT##nr##_FN3,			\
			PORT##nr##_FN4, PORT##nr##_FN5,			\
			PORT##nr##_FN6, PORT##nr##_FN7			\
		}							\
	}

/*
 * GPIO number helper macro for R-Car
 */
#define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))

#endif /* __SH_PFC_H */
Commit	Line	Data
910df4d0 MV	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
	14	#include <linux/stringify.h>
	15
	16	enum {
	17	PINMUX_TYPE_NONE,
	18	PINMUX_TYPE_FUNCTION,
	19	PINMUX_TYPE_GPIO,
	20	PINMUX_TYPE_OUTPUT,
	21	PINMUX_TYPE_INPUT,
	22	};
	23
	24	#define SH_PFC_PIN_CFG_INPUT (1 << 0)
	25	#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
	26	#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
	27	#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
	28	#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
	29	#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
	30	#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
	31
	32	struct sh_pfc_pin {
	33	u16 pin;
	34	u16 enum_id;
	35	const char *name;
	36	unsigned int configs;
	37	};
	38
	39	#define SH_PFC_PIN_GROUP(n) \
	40	{ \
	41	.name = #n, \
	42	.pins = n##_pins, \
	43	.mux = n##_mux, \
	44	.nr_pins = ARRAY_SIZE(n##_pins), \
	45	}
	46
	47	struct sh_pfc_pin_group {
	48	const char *name;
	49	const unsigned int *pins;
	50	const unsigned int *mux;
	51	unsigned int nr_pins;
	52	};
	53
	54	/*
	55	* Using union vin_data saves memory occupied by the VIN data pins.
	56	* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
	57	* in this case.
	58	*/
	59	#define VIN_DATA_PIN_GROUP(n, s) \
	60	{ \
	61	.name = #n#s, \
	62	.pins = n##_pins.data##s, \
	63	.mux = n##_mux.data##s, \
	64	.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
65	}
66
67	union vin_data {
68	unsigned int data24[24];
69	unsigned int data20[20];
70	unsigned int data16[16];
71	unsigned int data12[12];
72	unsigned int data10[10];
73	unsigned int data8[8];
74	unsigned int data4[4];
75	};
76
77	#define SH_PFC_FUNCTION(n) \
78	{ \
79	.name = #n, \
80	.groups = n##_groups, \
81	.nr_groups = ARRAY_SIZE(n##_groups), \
82	}
83
84	struct sh_pfc_function {
85	const char *name;
86	const char * const *groups;
87	unsigned int nr_groups;
88	};
89
90	struct pinmux_func {
91	u16 enum_id;
92	const char *name;
93	};
94
95	struct pinmux_cfg_reg {
96	u32 reg;
97	u8 reg_width, field_width;
98	const u16 *enum_ids;
99	const u8 *var_field_width;
100	};
101
102	/*
103	* Describe a config register consisting of several fields of the same width
104	* - name: Register name (unused, for documentation purposes only)
105	* - r: Physical register address
106	* - r_width: Width of the register (in bits)
107	* - f_width: Width of the fixed-width register fields (in bits)
108	* This macro must be followed by initialization data: For each register field
109	* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
110	* one for each possible combination of the register field bit values.
111	*/
112	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
113	.reg = r, .reg_width = r_width, .field_width = f_width, \
114	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
115
116	/*
117	* Describe a config register consisting of several fields of different widths
118	* - name: Register name (unused, for documentation purposes only)
119	* - r: Physical register address
120	* - r_width: Width of the register (in bits)
121	* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
122	* From left to right (i.e. MSB to LSB)
123	* This macro must be followed by initialization data: For each register field
124	* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
125	* one for each possible combination of the register field bit values.
126	*/
127	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
128	.reg = r, .reg_width = r_width, \
129	.var_field_width = (const u8 [r_width]) \
130	{ var_fw0, var_fwn, 0 }, \
131	.enum_ids = (const u16 [])
132
133	struct pinmux_drive_reg_field {
134	u16 pin;
135	u8 offset;
136	u8 size;
137	};
138
139	struct pinmux_drive_reg {
140	u32 reg;
141	const struct pinmux_drive_reg_field fields[8];
142	};
143
144	#define PINMUX_DRIVE_REG(name, r) \
145	.reg = r, \
146	.fields =
147
148	struct pinmux_data_reg {
149	u32 reg;
150	u8 reg_width;
151	const u16 *enum_ids;
152	};
153
154	/*
155	* Describe a data register
156	* - name: Register name (unused, for documentation purposes only)
157	* - r: Physical register address
158	* - r_width: Width of the register (in bits)
159	* This macro must be followed by initialization data: For each register bit
160	* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
161	*/
162	#define PINMUX_DATA_REG(name, r, r_width) \
163	.reg = r, .reg_width = r_width, \
164	.enum_ids = (const u16 [r_width]) \
165
166	struct pinmux_irq {
167	const short *gpios;
168	};
169
170	/*
171	* Describe the mapping from GPIOs to a single IRQ
172	* - ids...: List of GPIOs that are mapped to the same IRQ
173	*/
174	#define PINMUX_IRQ(ids...) \
175	{ .gpios = (const short []) { ids, -1 } }
176
177	struct pinmux_range {
178	u16 begin;
179	u16 end;
180	u16 force;
181	};
182
183	struct sh_pfc_bias_info {
184	u16 pin;
185	u16 reg : 11;
186	u16 bit : 5;
187	};
188
189	struct sh_pfc_pin_range;
190
191	struct sh_pfc {
192	struct device *dev;
193	const struct sh_pfc_soc_info *info;
194
195	void *regs;
196
197	struct sh_pfc_pin_range *ranges;
198	unsigned int nr_ranges;
199
200	unsigned int nr_gpio_pins;
201
202	struct sh_pfc_chip *gpio;
203	};
204
205	struct sh_pfc_soc_operations {
206	int (init)(struct sh_pfc pfc);
207	unsigned int (get_bias)(struct sh_pfc pfc, unsigned int pin);
208	void (set_bias)(struct sh_pfc pfc, unsigned int pin,
209	unsigned int bias);
210	int (pin_to_pocctrl)(struct sh_pfc pfc, unsigned int pin, u32 *pocctrl);
211	};
212
213	struct sh_pfc_soc_info {
214	const char *name;
215	const struct sh_pfc_soc_operations *ops;
216
217	struct pinmux_range input;
218	struct pinmux_range output;
219	struct pinmux_range function;
220
221	const struct sh_pfc_pin *pins;
222	unsigned int nr_pins;
223	const struct sh_pfc_pin_group *groups;
224	unsigned int nr_groups;
225	const struct sh_pfc_function *functions;
226	unsigned int nr_functions;
227
228	const struct pinmux_cfg_reg *cfg_regs;
229	const struct pinmux_drive_reg *drive_regs;
230	const struct pinmux_data_reg *data_regs;
231
232	const u16 *pinmux_data;
233	unsigned int pinmux_data_size;
234
235	const struct pinmux_irq *gpio_irq;
236	unsigned int gpio_irq_size;
237
238	u32 unlock_reg;
239	};
240
241	u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
242	void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
243	const struct sh_pfc_bias_info *
244	sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
245	unsigned int num, unsigned int pin);
f6e545a7	246	int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
910df4d0	247
7547ad4c	248	extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
427c75df	249	extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
ab2d09b4	250	extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
427c75df	251	extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
910df4d0 MV	252	extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
910df4d0 MV	253	extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
c106bb53	254	extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
a59e6976	255	extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
910df4d0 MV	256	/* -----------------------------------------------------------------------------
	257	* Helper macros to create pin and port lists
	258	*/
	259
	260	/*
	261	* sh_pfc_soc_info pinmux_data array macros
	262	*/
	263
	264	/*
	265	* Describe generic pinmux data
	266	* - data_or_mark: _DATA or _MARK enum ID
	267	* - ids...: List of enum IDs to associate with data_or_mark
	268	*/
	269	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	270
	271	/*
	272	* Describe a pinmux configuration without GPIO function that needs
	273	* configuration in a Peripheral Function Select Register (IPSR)
	274	* - ipsr: IPSR field (unused, for documentation purposes only)
	275	* - fn: Function name, referring to a field in the IPSR
	276	*/
	277	#define PINMUX_IPSR_NOGP(ipsr, fn) \
	278	PINMUX_DATA(fn##_MARK, FN_##fn)
	279
	280	/*
	281	* Describe a pinmux configuration with GPIO function that needs configuration
	282	* in both a Peripheral Function Select Register (IPSR) and in a
	283	* GPIO/Peripheral Function Select Register (GPSR)
	284	* - ipsr: IPSR field
	285	* - fn: Function name, also referring to the IPSR field
	286	*/
	287	#define PINMUX_IPSR_GPSR(ipsr, fn) \
	288	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
	289
	290	/*
	291	* Describe a pinmux configuration without GPIO function that needs
	292	* configuration in a Peripheral Function Select Register (IPSR), and where the
	293	* pinmux function has a representation in a Module Select Register (MOD_SEL).
	294	* - ipsr: IPSR field (unused, for documentation purposes only)
	295	* - fn: Function name, also referring to the IPSR field
	296	* - msel: Module selector
	297	*/
	298	#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
	299	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
	300
	301	/*
	302	* Describe a pinmux configuration with GPIO function where the pinmux function
	303	* has no representation in a Peripheral Function Select Register (IPSR), but
	304	* instead solely depends on a group selection.
	305	* - gpsr: GPSR field
	306	* - fn: Function name, also referring to the GPSR field
	307	* - gsel: Group selector
	308	*/
	309	#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
	310	PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
	311
	312	/*
	313	* Describe a pinmux configuration with GPIO function that needs configuration
	314	* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
	315	* Function Select Register (GPSR), and where the pinmux function has a
	316	* representation in a Module Select Register (MOD_SEL).
	317	* - ipsr: IPSR field
	318	* - fn: Function name, also referring to the IPSR field
	319	* - msel: Module selector
320	*/
321	#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
322	PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
323
324	/*
325	* Describe a pinmux configuration for a single-function pin with GPIO
326	* capability.
327	* - fn: Function name
328	*/
329	#define PINMUX_SINGLE(fn) \
330	PINMUX_DATA(fn##_MARK, FN_##fn)
331
332	/*
333	* GP port style (32 ports banks)
334	*/
335
336	#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
337	fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
338	#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
339
340	#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
341	PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
342	PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
343	PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
344	PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
345	#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
346
c106bb53 MV	347	#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
	348	PORT_GP_CFG_4(bank, fn, sfx, cfg), \
	349	PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
	350	#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
	351
910df4d0 MV	352	#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
	353	PORT_GP_CFG_4(bank, fn, sfx, cfg), \
	354	PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
	355	PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
	356	PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
	357	PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
	358	#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
	359
	360	#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
	361	PORT_GP_CFG_8(bank, fn, sfx, cfg), \
	362	PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
	363	#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
	364
	365	#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
	366	PORT_GP_CFG_9(bank, fn, sfx, cfg), \
	367	PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
	368	#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
	369
	370	#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
	371	PORT_GP_CFG_10(bank, fn, sfx, cfg), \
	372	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
	373	PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
	374	#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
	375
	376	#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
	377	PORT_GP_CFG_12(bank, fn, sfx, cfg), \
	378	PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
	379	PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
	380	#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
	381
	382	#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
	383	PORT_GP_CFG_14(bank, fn, sfx, cfg), \
	384	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
	385	#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
	386
	387	#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
	388	PORT_GP_CFG_15(bank, fn, sfx, cfg), \
	389	PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
	390	#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
	391
	392	#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
	393	PORT_GP_CFG_16(bank, fn, sfx, cfg), \
	394	PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
	395	#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
	396
	397	#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
	398	PORT_GP_CFG_17(bank, fn, sfx, cfg), \
	399	PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
	400	#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
	401
	402	#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
	403	PORT_GP_CFG_18(bank, fn, sfx, cfg), \
	404	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
	405	PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
	406	#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
	407
	408	#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
	409	PORT_GP_CFG_20(bank, fn, sfx, cfg), \
	410	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
	411	#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
	412
c106bb53 MV	413	#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
	414	PORT_GP_CFG_18(bank, fn, sfx, cfg), \
	415	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
	416	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
	417	#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
	418
910df4d0 MV	419	#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
	420	PORT_GP_CFG_21(bank, fn, sfx, cfg), \
	421	PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
	422	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
	423	#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
	424
	425	#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
	426	PORT_GP_CFG_23(bank, fn, sfx, cfg), \
	427	PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
	428	#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
	429
	430	#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
	431	PORT_GP_CFG_24(bank, fn, sfx, cfg), \
	432	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
	433	PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
	434	#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
	435
	436	#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
	437	PORT_GP_CFG_26(bank, fn, sfx, cfg), \
	438	PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
	439	PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
	440	#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
	441
	442	#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
	443	PORT_GP_CFG_28(bank, fn, sfx, cfg), \
	444	PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
	445	#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
	446
	447	#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
	448	PORT_GP_CFG_29(bank, fn, sfx, cfg), \
	449	PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
	450	#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
	451
	452	#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
	453	PORT_GP_CFG_30(bank, fn, sfx, cfg), \
	454	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
	455	PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
	456	#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
	457
	458	#define PORT_GP_32_REV(bank, fn, sfx) \
	459	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
	460	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
	461	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
	462	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
	463	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
	464	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
	465	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
	466	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
	467	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
	468	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
	469	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
	470	PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
	471	PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
	472	PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
	473	PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
	474	PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
	475
	476	/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
	477	#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
	478	#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
	479
	480	/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
	481	#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
	482	{ \
483	.pin = (bank * 32) + _pin, \
484	.name = __stringify(_name), \
485	.enum_id = _name##_DATA, \
486	.configs = cfg, \
487	}
488	#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
489
490	/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
491	#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
492	#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
493
494	/*
495	* PORT style (linear pin space)
496	*/
497
498	#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
499
500	#define PORT_10(pn, fn, pfx, sfx) \
501	PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
502	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
503	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
504	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
505	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
506
507	#define PORT_90(pn, fn, pfx, sfx) \
508	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
509	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
510	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
511	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
512	PORT_10(pn+90, fn, pfx##9, sfx)
513
514	/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
515	#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
516	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
517
518	/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
519	#define PINMUX_GPIO(_pin) \
520	[GPIO_##_pin] = { \
521	.pin = (u16)-1, \
522	.name = __stringify(GPIO_##_pin), \
523	.enum_id = _pin##_DATA, \
524	}
525
526	/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
527	#define SH_PFC_PIN_CFG(_pin, cfgs) \
528	{ \
529	.pin = _pin, \
530	.name = __stringify(PORT##_pin), \
531	.enum_id = PORT##_pin##_DATA, \
532	.configs = cfgs, \
533	}
534
535	/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
536	#define SH_PFC_PIN_NAMED(row, col, _name) \
537	{ \
538	.pin = PIN_NUMBER(row, col), \
539	.name = __stringify(PIN_##_name), \
540	.configs = SH_PFC_PIN_CFG_NO_GPIO, \
541	}
542
543	/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
544	#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
545	{ \
546	.pin = PIN_NUMBER(row, col), \
547	.name = __stringify(PIN_##_name), \
548	.configs = SH_PFC_PIN_CFG_NO_GPIO \| cfgs, \
549	}
550
551	/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
552	* PORT_name_OUT, PORT_name_IN marks
553	*/
554	#define _PORT_DATA(pn, pfx, sfx) \
555	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
556	PORT##pfx##_OUT, PORT##pfx##_IN)
557	#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
558
559	/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
560	#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
561	[gpio - (base)] = { \
562	.name = __stringify(gpio), \
563	.enum_id = data_or_mark, \
564	}
565	#define GPIO_FN(str) \
566	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
567
568	/*
569	* PORTnCR helper macro for SH-Mobile/R-Mobile
570	*/
571	#define PORTCR(nr, reg) \
572	{ \
573	PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
574	/* PULMD[1:0], handled by .set_bias() */ \
575	0, 0, 0, 0, \
576	/* IE and OE */ \
577	0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
578	/* SEC, not supported */ \
579	0, 0, \
580	/* PTMD[2:0] */ \
581	PORT##nr##_FN0, PORT##nr##_FN1, \
582	PORT##nr##_FN2, PORT##nr##_FN3, \
583	PORT##nr##_FN4, PORT##nr##_FN5, \
584	PORT##nr##_FN6, PORT##nr##_FN7 \
585	} \
586	}
587
588	/*
589	* GPIO number helper macro for R-Car
590	*/
591	#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
592
593	#endif /* __SH_PFC_H */