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a2c08df3 KY |
1 | /* |
2 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <dm.h> | |
9 | #include <errno.h> | |
10 | #include <syscon.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch/grf_rk3399.h> | |
13 | #include <asm/arch/hardware.h> | |
14 | #include <asm/arch/periph.h> | |
15 | #include <asm/arch/clock.h> | |
16 | #include <dm/pinctrl.h> | |
17 | ||
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
20 | struct rk3399_pinctrl_priv { | |
21 | struct rk3399_grf_regs *grf; | |
22 | struct rk3399_pmugrf_regs *pmugrf; | |
23 | }; | |
24 | ||
a2c08df3 KY |
25 | static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, |
26 | struct rk3399_pmugrf_regs *pmugrf, int pwm_id) | |
27 | { | |
28 | switch (pwm_id) { | |
29 | case PERIPH_ID_PWM0: | |
30 | rk_clrsetreg(&grf->gpio4c_iomux, | |
31 | GRF_GPIO4C2_SEL_MASK, | |
32 | GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT); | |
33 | break; | |
34 | case PERIPH_ID_PWM1: | |
35 | rk_clrsetreg(&grf->gpio4c_iomux, | |
36 | GRF_GPIO4C6_SEL_MASK, | |
37 | GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT); | |
38 | break; | |
39 | case PERIPH_ID_PWM2: | |
40 | rk_clrsetreg(&pmugrf->gpio1c_iomux, | |
41 | PMUGRF_GPIO1C3_SEL_MASK, | |
42 | PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT); | |
43 | break; | |
44 | case PERIPH_ID_PWM3: | |
45 | if (readl(&pmugrf->soc_con0) & (1 << 5)) | |
46 | rk_clrsetreg(&pmugrf->gpio1b_iomux, | |
47 | PMUGRF_GPIO1B6_SEL_MASK, | |
48 | PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT); | |
49 | else | |
50 | rk_clrsetreg(&pmugrf->gpio0a_iomux, | |
51 | PMUGRF_GPIO0A6_SEL_MASK, | |
52 | PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT); | |
53 | break; | |
54 | default: | |
55 | debug("pwm id = %d iomux error!\n", pwm_id); | |
56 | break; | |
57 | } | |
58 | } | |
59 | ||
60 | static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, | |
61 | struct rk3399_pmugrf_regs *pmugrf, | |
62 | int i2c_id) | |
63 | { | |
64 | switch (i2c_id) { | |
65 | case PERIPH_ID_I2C0: | |
66 | rk_clrsetreg(&pmugrf->gpio1b_iomux, | |
67 | PMUGRF_GPIO1B7_SEL_MASK, | |
68 | PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT); | |
69 | rk_clrsetreg(&pmugrf->gpio1c_iomux, | |
70 | PMUGRF_GPIO1C0_SEL_MASK, | |
71 | PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); | |
72 | break; | |
8c2bb589 PT |
73 | case PERIPH_ID_I2C8: |
74 | rk_clrsetreg(&pmugrf->gpio1c_iomux, | |
75 | PMUGRF_GPIO1C4_SEL_MASK, | |
76 | PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT); | |
77 | rk_clrsetreg(&pmugrf->gpio1c_iomux, | |
78 | PMUGRF_GPIO1C5_SEL_MASK, | |
79 | PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT); | |
80 | break; | |
a2c08df3 KY |
81 | case PERIPH_ID_I2C1: |
82 | case PERIPH_ID_I2C2: | |
83 | case PERIPH_ID_I2C3: | |
84 | case PERIPH_ID_I2C4: | |
85 | case PERIPH_ID_I2C5: | |
8c2bb589 PT |
86 | case PERIPH_ID_I2C6: |
87 | case PERIPH_ID_I2C7: | |
a2c08df3 KY |
88 | default: |
89 | debug("i2c id = %d iomux error!\n", i2c_id); | |
90 | break; | |
91 | } | |
92 | } | |
93 | ||
94 | static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id) | |
95 | { | |
96 | switch (lcd_id) { | |
97 | case PERIPH_ID_LCDC0: | |
98 | break; | |
99 | default: | |
100 | debug("lcdc id = %d iomux error!\n", lcd_id); | |
101 | break; | |
102 | } | |
103 | } | |
104 | ||
105 | static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, | |
106 | struct rk3399_pmugrf_regs *pmugrf, | |
107 | enum periph_id spi_id, int cs) | |
108 | { | |
109 | switch (spi_id) { | |
110 | case PERIPH_ID_SPI0: | |
111 | switch (cs) { | |
112 | case 0: | |
113 | rk_clrsetreg(&grf->gpio3a_iomux, | |
114 | GRF_GPIO3A7_SEL_MASK, | |
115 | GRF_SPI0NORCODEC_CSN0 | |
116 | << GRF_GPIO3A7_SEL_SHIFT); | |
117 | break; | |
118 | case 1: | |
119 | rk_clrsetreg(&grf->gpio3b_iomux, | |
120 | GRF_GPIO3B0_SEL_MASK, | |
121 | GRF_SPI0NORCODEC_CSN1 | |
122 | << GRF_GPIO3B0_SEL_SHIFT); | |
123 | break; | |
124 | default: | |
125 | goto err; | |
126 | } | |
127 | rk_clrsetreg(&grf->gpio3a_iomux, | |
128 | GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT | |
129 | | GRF_GPIO3A6_SEL_SHIFT, | |
130 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT | |
131 | | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT | |
132 | | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT); | |
133 | break; | |
134 | case PERIPH_ID_SPI1: | |
135 | if (cs != 0) | |
136 | goto err; | |
137 | rk_clrsetreg(&pmugrf->gpio1a_iomux, | |
138 | PMUGRF_GPIO1A7_SEL_MASK, | |
139 | PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT); | |
140 | rk_clrsetreg(&pmugrf->gpio1b_iomux, | |
141 | PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK | |
142 | | PMUGRF_GPIO1B2_SEL_MASK, | |
143 | PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT | |
144 | | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT | |
145 | | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT); | |
146 | break; | |
147 | case PERIPH_ID_SPI2: | |
148 | if (cs != 0) | |
149 | goto err; | |
150 | rk_clrsetreg(&grf->gpio2b_iomux, | |
151 | GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK | |
152 | | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK, | |
153 | GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT | |
154 | | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT | |
155 | | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT | |
156 | | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); | |
157 | break; | |
315e6a38 PT |
158 | case PERIPH_ID_SPI5: |
159 | if (cs != 0) | |
160 | goto err; | |
161 | rk_clrsetreg(&grf->gpio2c_iomux, | |
162 | GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK | |
163 | | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK, | |
164 | GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT | |
165 | | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT | |
166 | | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT | |
167 | | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT); | |
168 | break; | |
a2c08df3 | 169 | default: |
315e6a38 | 170 | printf("%s: spi_id %d is not supported.\n", __func__, spi_id); |
a2c08df3 KY |
171 | goto err; |
172 | } | |
173 | ||
174 | return 0; | |
175 | err: | |
176 | debug("rkspi: periph%d cs=%d not supported", spi_id, cs); | |
177 | return -ENOENT; | |
178 | } | |
179 | ||
180 | static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf, | |
181 | struct rk3399_pmugrf_regs *pmugrf, | |
182 | int uart_id) | |
183 | { | |
184 | switch (uart_id) { | |
185 | case PERIPH_ID_UART2: | |
186 | /* Using channel-C by default */ | |
187 | rk_clrsetreg(&grf->gpio4c_iomux, | |
188 | GRF_GPIO4C3_SEL_MASK, | |
189 | GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); | |
190 | rk_clrsetreg(&grf->gpio4c_iomux, | |
191 | GRF_GPIO4C4_SEL_MASK, | |
192 | GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); | |
193 | break; | |
194 | case PERIPH_ID_UART0: | |
195 | case PERIPH_ID_UART1: | |
196 | case PERIPH_ID_UART3: | |
197 | case PERIPH_ID_UART4: | |
198 | default: | |
199 | debug("uart id = %d iomux error!\n", uart_id); | |
200 | break; | |
201 | } | |
202 | } | |
203 | ||
204 | static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) | |
205 | { | |
206 | switch (mmc_id) { | |
207 | case PERIPH_ID_EMMC: | |
208 | break; | |
209 | case PERIPH_ID_SDCARD: | |
210 | rk_clrsetreg(&grf->gpio4b_iomux, | |
211 | GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK | |
212 | | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK | |
213 | | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK, | |
214 | GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT | |
215 | | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT | |
216 | | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT | |
217 | | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT | |
218 | | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT | |
219 | | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT); | |
220 | break; | |
221 | default: | |
222 | debug("mmc id = %d iomux error!\n", mmc_id); | |
223 | break; | |
224 | } | |
225 | } | |
226 | ||
476f7090 PT |
227 | #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) |
228 | static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) | |
229 | { | |
230 | rk_clrsetreg(&grf->gpio3a_iomux, | |
231 | GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK | | |
232 | GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK | | |
233 | GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK | | |
234 | GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK, | |
235 | GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT | | |
236 | GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT | | |
237 | GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT | | |
238 | GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT | | |
239 | GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT | | |
240 | GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT | | |
241 | GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT | | |
242 | GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT); | |
243 | rk_clrsetreg(&grf->gpio3b_iomux, | |
244 | GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK | | |
245 | GRF_GPIO3B3_SEL_MASK | | |
246 | GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK | | |
247 | GRF_GPIO3B6_SEL_MASK, | |
248 | GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT | | |
249 | GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT | | |
250 | GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT | | |
251 | GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT | | |
252 | GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT | | |
253 | GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT); | |
254 | rk_clrsetreg(&grf->gpio3c_iomux, | |
255 | GRF_GPIO3C1_SEL_MASK, | |
256 | GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); | |
602778d3 KY |
257 | |
258 | /* Set drive strength for GMAC tx io, value 3 means 13mA */ | |
259 | rk_clrsetreg(&grf->gpio3_e[0], | |
260 | GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK | | |
261 | GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK, | |
262 | 3 << GRF_GPIO3A0_E_SHIFT | | |
263 | 3 << GRF_GPIO3A1_E_SHIFT | | |
264 | 3 << GRF_GPIO3A4_E_SHIFT | | |
265 | 1 << GRF_GPIO3A5_E0_SHIFT); | |
266 | rk_clrsetreg(&grf->gpio3_e[1], | |
267 | GRF_GPIO3A5_E12_MASK, | |
268 | 1 << GRF_GPIO3A5_E12_SHIFT); | |
269 | rk_clrsetreg(&grf->gpio3_e[2], | |
270 | GRF_GPIO3B4_E_MASK, | |
271 | 3 << GRF_GPIO3B4_E_SHIFT); | |
272 | rk_clrsetreg(&grf->gpio3_e[4], | |
273 | GRF_GPIO3C1_E_MASK, | |
274 | 3 << GRF_GPIO3C1_E_SHIFT); | |
476f7090 PT |
275 | } |
276 | #endif | |
277 | ||
26e2e404 PT |
278 | #if !defined(CONFIG_SPL_BUILD) |
279 | static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id) | |
280 | { | |
281 | switch (hdmi_id) { | |
282 | case PERIPH_ID_HDMI: | |
283 | rk_clrsetreg(&grf->gpio4c_iomux, | |
284 | GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK, | |
285 | (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) | | |
286 | (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT)); | |
287 | break; | |
288 | default: | |
289 | debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id); | |
290 | break; | |
291 | } | |
292 | } | |
293 | #endif | |
294 | ||
a2c08df3 KY |
295 | static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) |
296 | { | |
297 | struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); | |
298 | ||
299 | debug("%s: func=%x, flags=%x\n", __func__, func, flags); | |
300 | switch (func) { | |
301 | case PERIPH_ID_PWM0: | |
302 | case PERIPH_ID_PWM1: | |
303 | case PERIPH_ID_PWM2: | |
304 | case PERIPH_ID_PWM3: | |
305 | case PERIPH_ID_PWM4: | |
306 | pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func); | |
307 | break; | |
308 | case PERIPH_ID_I2C0: | |
309 | case PERIPH_ID_I2C1: | |
310 | case PERIPH_ID_I2C2: | |
311 | case PERIPH_ID_I2C3: | |
312 | case PERIPH_ID_I2C4: | |
313 | case PERIPH_ID_I2C5: | |
8c2bb589 PT |
314 | case PERIPH_ID_I2C6: |
315 | case PERIPH_ID_I2C7: | |
316 | case PERIPH_ID_I2C8: | |
a2c08df3 KY |
317 | pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func); |
318 | break; | |
319 | case PERIPH_ID_SPI0: | |
320 | case PERIPH_ID_SPI1: | |
321 | case PERIPH_ID_SPI2: | |
315e6a38 PT |
322 | case PERIPH_ID_SPI3: |
323 | case PERIPH_ID_SPI4: | |
324 | case PERIPH_ID_SPI5: | |
a2c08df3 KY |
325 | pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); |
326 | break; | |
327 | case PERIPH_ID_UART0: | |
328 | case PERIPH_ID_UART1: | |
329 | case PERIPH_ID_UART2: | |
330 | case PERIPH_ID_UART3: | |
331 | case PERIPH_ID_UART4: | |
332 | pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func); | |
333 | break; | |
334 | case PERIPH_ID_LCDC0: | |
335 | case PERIPH_ID_LCDC1: | |
336 | pinctrl_rk3399_lcdc_config(priv->grf, func); | |
337 | break; | |
338 | case PERIPH_ID_SDMMC0: | |
339 | case PERIPH_ID_SDMMC1: | |
340 | pinctrl_rk3399_sdmmc_config(priv->grf, func); | |
341 | break; | |
476f7090 PT |
342 | #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) |
343 | case PERIPH_ID_GMAC: | |
344 | pinctrl_rk3399_gmac_config(priv->grf, func); | |
345 | break; | |
26e2e404 PT |
346 | #endif |
347 | #if !defined(CONFIG_SPL_BUILD) | |
348 | case PERIPH_ID_HDMI: | |
349 | pinctrl_rk3399_hdmi_config(priv->grf, func); | |
350 | break; | |
476f7090 | 351 | #endif |
a2c08df3 KY |
352 | default: |
353 | return -EINVAL; | |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int rk3399_pinctrl_get_periph_id(struct udevice *dev, | |
360 | struct udevice *periph) | |
361 | { | |
6657f664 | 362 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
a2c08df3 KY |
363 | u32 cell[3]; |
364 | int ret; | |
365 | ||
9f4f914d | 366 | ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); |
a2c08df3 KY |
367 | if (ret < 0) |
368 | return -EINVAL; | |
369 | ||
370 | switch (cell[1]) { | |
371 | case 68: | |
372 | return PERIPH_ID_SPI0; | |
373 | case 53: | |
374 | return PERIPH_ID_SPI1; | |
375 | case 52: | |
376 | return PERIPH_ID_SPI2; | |
315e6a38 PT |
377 | case 132: |
378 | return PERIPH_ID_SPI5; | |
a2c08df3 KY |
379 | case 57: |
380 | return PERIPH_ID_I2C0; | |
381 | case 59: /* Note strange order */ | |
382 | return PERIPH_ID_I2C1; | |
383 | case 35: | |
384 | return PERIPH_ID_I2C2; | |
385 | case 34: | |
386 | return PERIPH_ID_I2C3; | |
387 | case 56: | |
388 | return PERIPH_ID_I2C4; | |
389 | case 38: | |
390 | return PERIPH_ID_I2C5; | |
8c2bb589 PT |
391 | case 37: |
392 | return PERIPH_ID_I2C6; | |
393 | case 36: | |
394 | return PERIPH_ID_I2C7; | |
395 | case 58: | |
396 | return PERIPH_ID_I2C8; | |
a2c08df3 KY |
397 | case 65: |
398 | return PERIPH_ID_SDMMC1; | |
476f7090 PT |
399 | #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) |
400 | case 12: | |
401 | return PERIPH_ID_GMAC; | |
26e2e404 PT |
402 | #endif |
403 | #if !defined(CONFIG_SPL_BUILD) | |
404 | case 23: | |
405 | return PERIPH_ID_HDMI; | |
476f7090 | 406 | #endif |
a2c08df3 | 407 | } |
6657f664 | 408 | #endif |
a2c08df3 KY |
409 | return -ENOENT; |
410 | } | |
411 | ||
412 | static int rk3399_pinctrl_set_state_simple(struct udevice *dev, | |
413 | struct udevice *periph) | |
414 | { | |
415 | int func; | |
416 | ||
417 | func = rk3399_pinctrl_get_periph_id(dev, periph); | |
418 | if (func < 0) | |
419 | return func; | |
420 | ||
421 | return rk3399_pinctrl_request(dev, func, 0); | |
422 | } | |
423 | ||
424 | static struct pinctrl_ops rk3399_pinctrl_ops = { | |
425 | .set_state_simple = rk3399_pinctrl_set_state_simple, | |
426 | .request = rk3399_pinctrl_request, | |
427 | .get_periph_id = rk3399_pinctrl_get_periph_id, | |
428 | }; | |
429 | ||
430 | static int rk3399_pinctrl_probe(struct udevice *dev) | |
431 | { | |
432 | struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); | |
433 | int ret = 0; | |
434 | ||
435 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); | |
436 | priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); | |
437 | debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); | |
438 | ||
439 | return ret; | |
440 | } | |
441 | ||
442 | static const struct udevice_id rk3399_pinctrl_ids[] = { | |
443 | { .compatible = "rockchip,rk3399-pinctrl" }, | |
444 | { } | |
445 | }; | |
446 | ||
447 | U_BOOT_DRIVER(pinctrl_rk3399) = { | |
448 | .name = "rockchip_rk3399_pinctrl", | |
449 | .id = UCLASS_PINCTRL, | |
450 | .of_match = rk3399_pinctrl_ids, | |
451 | .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), | |
452 | .ops = &rk3399_pinctrl_ops, | |
6657f664 | 453 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
a2c08df3 | 454 | .bind = dm_scan_fdt_dev, |
6657f664 | 455 | #endif |
a2c08df3 KY |
456 | .probe = rk3399_pinctrl_probe, |
457 | }; |