]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/qe/uec.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Big white-space cleanup.
[people/ms/u-boot.git] / drivers / qe / uec.c
CommitLineData
7737d5c6
DL		 1/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include "common.h"
23#include "net.h"
24#include "malloc.h"
25#include "asm/errno.h"
26#include "asm/io.h"
27#include "asm/immap_qe.h"
28#include "qe.h"
29#include "uccf.h"
30#include "uec.h"
31#include "uec_phy.h"
32
33#if defined(CONFIG_QE)
34
35#ifdef CONFIG_UEC_ETH1
36static uec_info_t eth1_uec_info = {
37 .uf_info = {
38 .ucc_num = CFG_UEC1_UCC_NUM,
39 .rx_clock = CFG_UEC1_RX_CLK,
40 .tx_clock = CFG_UEC1_TX_CLK,
41 .eth_type = CFG_UEC1_ETH_TYPE,
42 },
2465665b
DS		 43#if (CFG_UEC1_ETH_TYPE == FAST_ETH)
44 .num_threads_tx = UEC_NUM_OF_THREADS_1,
45 .num_threads_rx = UEC_NUM_OF_THREADS_1,
46#else
7737d5c6
DL		 47 .num_threads_tx = UEC_NUM_OF_THREADS_4,
48 .num_threads_rx = UEC_NUM_OF_THREADS_4,
2465665b 49#endif
7737d5c6
DL		 50 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
51 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
52 .tx_bd_ring_len = 16,
53 .rx_bd_ring_len = 16,
54 .phy_address = CFG_UEC1_PHY_ADDR,
55 .enet_interface = CFG_UEC1_INTERFACE_MODE,
56};
57#endif
58#ifdef CONFIG_UEC_ETH2
59static uec_info_t eth2_uec_info = {
60 .uf_info = {
61 .ucc_num = CFG_UEC2_UCC_NUM,
62 .rx_clock = CFG_UEC2_RX_CLK,
63 .tx_clock = CFG_UEC2_TX_CLK,
64 .eth_type = CFG_UEC2_ETH_TYPE,
65 },
2465665b
DS		 66#if (CFG_UEC2_ETH_TYPE == FAST_ETH)
67 .num_threads_tx = UEC_NUM_OF_THREADS_1,
68 .num_threads_rx = UEC_NUM_OF_THREADS_1,
69#else
7737d5c6
DL		 70 .num_threads_tx = UEC_NUM_OF_THREADS_4,
71 .num_threads_rx = UEC_NUM_OF_THREADS_4,
2465665b 72#endif
7737d5c6
DL		 73 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
74 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
75 .tx_bd_ring_len = 16,
76 .rx_bd_ring_len = 16,
77 .phy_address = CFG_UEC2_PHY_ADDR,
78 .enet_interface = CFG_UEC2_INTERFACE_MODE,
79};
80#endif
ccf21c31
JT		 81#ifdef CONFIG_UEC_ETH3
82static uec_info_t eth3_uec_info = {
83 .uf_info = {
84 .ucc_num = CFG_UEC3_UCC_NUM,
85 .rx_clock = CFG_UEC3_RX_CLK,
86 .tx_clock = CFG_UEC3_TX_CLK,
87 .eth_type = CFG_UEC3_ETH_TYPE,
88 },
2465665b
DS		 89#if (CFG_UEC3_ETH_TYPE == FAST_ETH)
90 .num_threads_tx = UEC_NUM_OF_THREADS_1,
91 .num_threads_rx = UEC_NUM_OF_THREADS_1,
92#else
ccf21c31
JT		 93 .num_threads_tx = UEC_NUM_OF_THREADS_4,
94 .num_threads_rx = UEC_NUM_OF_THREADS_4,
2465665b 95#endif
ccf21c31
JT		 96 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
97 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
98 .tx_bd_ring_len = 16,
99 .rx_bd_ring_len = 16,
100 .phy_address = CFG_UEC3_PHY_ADDR,
101 .enet_interface = CFG_UEC3_INTERFACE_MODE,
102};
103#endif
2465665b
DS		 104#ifdef CONFIG_UEC_ETH4
105static uec_info_t eth4_uec_info = {
106 .uf_info = {
107 .ucc_num = CFG_UEC4_UCC_NUM,
108 .rx_clock = CFG_UEC4_RX_CLK,
109 .tx_clock = CFG_UEC4_TX_CLK,
110 .eth_type = CFG_UEC4_ETH_TYPE,
111 },
112#if (CFG_UEC4_ETH_TYPE == FAST_ETH)
113 .num_threads_tx = UEC_NUM_OF_THREADS_1,
114 .num_threads_rx = UEC_NUM_OF_THREADS_1,
115#else
116 .num_threads_tx = UEC_NUM_OF_THREADS_4,
117 .num_threads_rx = UEC_NUM_OF_THREADS_4,
118#endif
119 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
120 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
121 .tx_bd_ring_len = 16,
122 .rx_bd_ring_len = 16,
123 .phy_address = CFG_UEC4_PHY_ADDR,
124 .enet_interface = CFG_UEC4_INTERFACE_MODE,
125};
126#endif
ccf21c31 127
7737d5c6
DL		 128static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
129{
130 uec_t *uec_regs;
131 u32 maccfg1;
132
133 if (!uec) {
134 printf("%s: uec not initial\n", __FUNCTION__);
135 return -EINVAL;
136 }
137 uec_regs = uec->uec_regs;
138
139 maccfg1 = in_be32(&uec_regs->maccfg1);
140
141 if (mode & COMM_DIR_TX) {
142 maccfg1 |= MACCFG1_ENABLE_TX;
143 out_be32(&uec_regs->maccfg1, maccfg1);
144 uec->mac_tx_enabled = 1;
145 }
146
147 if (mode & COMM_DIR_RX) {
148 maccfg1 |= MACCFG1_ENABLE_RX;
149 out_be32(&uec_regs->maccfg1, maccfg1);
150 uec->mac_rx_enabled = 1;
151 }
152
153 return 0;
154}
155
156static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
157{
158 uec_t *uec_regs;
159 u32 maccfg1;
160
161 if (!uec) {
162 printf("%s: uec not initial\n", __FUNCTION__);
163 return -EINVAL;
164 }
165 uec_regs = uec->uec_regs;
166
167 maccfg1 = in_be32(&uec_regs->maccfg1);
168
169 if (mode & COMM_DIR_TX) {
170 maccfg1 &= ~MACCFG1_ENABLE_TX;
171 out_be32(&uec_regs->maccfg1, maccfg1);
172 uec->mac_tx_enabled = 0;
173 }
174
175 if (mode & COMM_DIR_RX) {
176 maccfg1 &= ~MACCFG1_ENABLE_RX;
177 out_be32(&uec_regs->maccfg1, maccfg1);
178 uec->mac_rx_enabled = 0;
179 }
180
181 return 0;
182}
183
184static int uec_graceful_stop_tx(uec_private_t *uec)
185{
186 ucc_fast_t *uf_regs;
187 u32 cecr_subblock;
188 u32 ucce;
189
190 if (!uec || !uec->uccf) {
191 printf("%s: No handle passed.\n", __FUNCTION__);
192 return -EINVAL;
193 }
194
195 uf_regs = uec->uccf->uf_regs;
196
197 /* Clear the grace stop event */
198 out_be32(&uf_regs->ucce, UCCE_GRA);
199
200 /* Issue host command */
201 cecr_subblock =
202 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
203 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
204 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
205
206 /* Wait for command to complete */
207 do {
208 ucce = in_be32(&uf_regs->ucce);
209 } while (! (ucce & UCCE_GRA));
210
211 uec->grace_stopped_tx = 1;
212
213 return 0;
214}
215
216static int uec_graceful_stop_rx(uec_private_t *uec)
217{
218 u32 cecr_subblock;
219 u8 ack;
220
221 if (!uec) {
222 printf("%s: No handle passed.\n", __FUNCTION__);
223 return -EINVAL;
224 }
225
226 if (!uec->p_rx_glbl_pram) {
227 printf("%s: No init rx global parameter\n", __FUNCTION__);
228 return -EINVAL;
229 }
230
231 /* Clear acknowledge bit */
232 ack = uec->p_rx_glbl_pram->rxgstpack;
233 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
234 uec->p_rx_glbl_pram->rxgstpack = ack;
235
236 /* Keep issuing cmd and checking ack bit until it is asserted */
237 do {
238 /* Issue host command */
239 cecr_subblock =
240 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
241 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
242 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
243 ack = uec->p_rx_glbl_pram->rxgstpack;
244 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
245
246 uec->grace_stopped_rx = 1;
247
248 return 0;
249}
250
251static int uec_restart_tx(uec_private_t *uec)
252{
253 u32 cecr_subblock;
254
255 if (!uec || !uec->uec_info) {
256 printf("%s: No handle passed.\n", __FUNCTION__);
257 return -EINVAL;
258 }
259
260 cecr_subblock =
261 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
262 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
263 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
264
265 uec->grace_stopped_tx = 0;
266
267 return 0;
268}
269
270static int uec_restart_rx(uec_private_t *uec)
271{
272 u32 cecr_subblock;
273
274 if (!uec || !uec->uec_info) {
275 printf("%s: No handle passed.\n", __FUNCTION__);
276 return -EINVAL;
277 }
278
279 cecr_subblock =
280 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
281 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
282 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
283
284 uec->grace_stopped_rx = 0;
285
286 return 0;
287}
288
289static int uec_open(uec_private_t *uec, comm_dir_e mode)
290{
291 ucc_fast_private_t *uccf;
292
293 if (!uec || !uec->uccf) {
294 printf("%s: No handle passed.\n", __FUNCTION__);
295 return -EINVAL;
296 }
297 uccf = uec->uccf;
298
299 /* check if the UCC number is in range. */
300 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
301 printf("%s: ucc_num out of range.\n", __FUNCTION__);
302 return -EINVAL;
303 }
304
305 /* Enable MAC */
306 uec_mac_enable(uec, mode);
307
308 /* Enable UCC fast */
309 ucc_fast_enable(uccf, mode);
310
311 /* RISC microcode start */
312 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
313 uec_restart_tx(uec);
314 }
315 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
316 uec_restart_rx(uec);
317 }
318
319 return 0;
320}
321
322static int uec_stop(uec_private_t *uec, comm_dir_e mode)
323{
324 ucc_fast_private_t *uccf;
325
326 if (!uec || !uec->uccf) {
327 printf("%s: No handle passed.\n", __FUNCTION__);
328 return -EINVAL;
329 }
330 uccf = uec->uccf;
331
332 /* check if the UCC number is in range. */
333 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
334 printf("%s: ucc_num out of range.\n", __FUNCTION__);
335 return -EINVAL;
336 }
337 /* Stop any transmissions */
338 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
339 uec_graceful_stop_tx(uec);
340 }
341 /* Stop any receptions */
342 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
343 uec_graceful_stop_rx(uec);
344 }
345
346 /* Disable the UCC fast */
347 ucc_fast_disable(uec->uccf, mode);
348
349 /* Disable the MAC */
350 uec_mac_disable(uec, mode);
351
352 return 0;
353}
354
355static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
356{
357 uec_t *uec_regs;
358 u32 maccfg2;
359
360 if (!uec) {
361 printf("%s: uec not initial\n", __FUNCTION__);
362 return -EINVAL;
363 }
364 uec_regs = uec->uec_regs;
365
366 if (duplex == DUPLEX_HALF) {
367 maccfg2 = in_be32(&uec_regs->maccfg2);
368 maccfg2 &= ~MACCFG2_FDX;
369 out_be32(&uec_regs->maccfg2, maccfg2);
370 }
371
372 if (duplex == DUPLEX_FULL) {
373 maccfg2 = in_be32(&uec_regs->maccfg2);
374 maccfg2 |= MACCFG2_FDX;
375 out_be32(&uec_regs->maccfg2, maccfg2);
376 }
377
378 return 0;
379}
380
381static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
382{
383 enet_interface_e enet_if_mode;
53677ef1 384 uec_info_t *uec_info;
7737d5c6
DL		 385 uec_t *uec_regs;
386 u32 upsmr;
387 u32 maccfg2;
388
389 if (!uec) {
390 printf("%s: uec not initial\n", __FUNCTION__);
391 return -EINVAL;
392 }
393
394 uec_info = uec->uec_info;
395 uec_regs = uec->uec_regs;
396 enet_if_mode = if_mode;
397
398 maccfg2 = in_be32(&uec_regs->maccfg2);
399 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
400
401 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
402 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
403
404 switch (enet_if_mode) {
405 case ENET_100_MII:
406 case ENET_10_MII:
407 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
408 break;
409 case ENET_1000_GMII:
410 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
411 break;
412 case ENET_1000_TBI:
413 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
414 upsmr |= UPSMR_TBIM;
415 break;
416 case ENET_1000_RTBI:
417 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
418 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
419 break;
6a600c3a 420 case ENET_1000_RGMII_RXID:
7737d5c6
DL		 421 case ENET_1000_RGMII:
422 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
423 upsmr |= UPSMR_RPM;
424 break;
425 case ENET_100_RGMII:
426 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
427 upsmr |= UPSMR_RPM;
428 break;
429 case ENET_10_RGMII:
430 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
431 upsmr |= (UPSMR_RPM | UPSMR_R10M);
432 break;
433 case ENET_100_RMII:
434 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
435 upsmr |= UPSMR_RMM;
436 break;
437 case ENET_10_RMII:
438 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
439 upsmr |= (UPSMR_R10M | UPSMR_RMM);
440 break;
441 default:
442 return -EINVAL;
443 break;
444 }
445 out_be32(&uec_regs->maccfg2, maccfg2);
446 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
447
448 return 0;
449}
450
da9d4610 451static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
7737d5c6
DL		 452{
453 uint timeout = 0x1000;
454 u32 miimcfg = 0;
455
da9d4610 456 miimcfg = in_be32(&uec_mii_regs->miimcfg);
7737d5c6 457 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
da9d4610 458 out_be32(&uec_mii_regs->miimcfg, miimcfg);
7737d5c6
DL		 459
460 /* Wait until the bus is free */
da9d4610 461 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
7737d5c6
DL		 462 if (timeout <= 0) {
463 printf("%s: The MII Bus is stuck!", __FUNCTION__);
464 return -ETIMEDOUT;
465 }
466
467 return 0;
468}
469
470static int init_phy(struct eth_device *dev)
471{
472 uec_private_t *uec;
da9d4610 473 uec_mii_t *umii_regs;
7737d5c6
DL		 474 struct uec_mii_info *mii_info;
475 struct phy_info *curphy;
476 int err;
477
478 uec = (uec_private_t *)dev->priv;
da9d4610 479 umii_regs = uec->uec_mii_regs;
7737d5c6
DL		 480
481 uec->oldlink = 0;
482 uec->oldspeed = 0;
483 uec->oldduplex = -1;
484
485 mii_info = malloc(sizeof(*mii_info));
486 if (!mii_info) {
487 printf("%s: Could not allocate mii_info", dev->name);
488 return -ENOMEM;
489 }
490 memset(mii_info, 0, sizeof(*mii_info));
491
24c3aca3
DL		 492 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
493 mii_info->speed = SPEED_1000;
494 } else {
495 mii_info->speed = SPEED_100;
496 }
497
7737d5c6
DL		 498 mii_info->duplex = DUPLEX_FULL;
499 mii_info->pause = 0;
500 mii_info->link = 1;
501
502 mii_info->advertising = (ADVERTISED_10baseT_Half |
503 ADVERTISED_10baseT_Full |
504 ADVERTISED_100baseT_Half |
505 ADVERTISED_100baseT_Full |
506 ADVERTISED_1000baseT_Full);
507 mii_info->autoneg = 1;
508 mii_info->mii_id = uec->uec_info->phy_address;
509 mii_info->dev = dev;
510
da9d4610
AF		 511 mii_info->mdio_read = &uec_read_phy_reg;
512 mii_info->mdio_write = &uec_write_phy_reg;
7737d5c6
DL		 513
514 uec->mii_info = mii_info;
515
ee62ed32
KP		 516 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
517
da9d4610 518 if (init_mii_management_configuration(umii_regs)) {
7737d5c6
DL		 519 printf("%s: The MII Bus is stuck!", dev->name);
520 err = -1;
521 goto bus_fail;
522 }
523
524 /* get info for this PHY */
da9d4610 525 curphy = uec_get_phy_info(uec->mii_info);
7737d5c6
DL		 526 if (!curphy) {
527 printf("%s: No PHY found", dev->name);
528 err = -1;
529 goto no_phy;
530 }
531
532 mii_info->phyinfo = curphy;
533
534 /* Run the commands which initialize the PHY */
535 if (curphy->init) {
536 err = curphy->init(uec->mii_info);
537 if (err)
538 goto phy_init_fail;
539 }
540
541 return 0;
542
543phy_init_fail:
544no_phy:
545bus_fail:
546 free(mii_info);
547 return err;
548}
549
550static void adjust_link(struct eth_device *dev)
551{
552 uec_private_t *uec = (uec_private_t *)dev->priv;
553 uec_t *uec_regs;
554 struct uec_mii_info *mii_info = uec->mii_info;
555
556 extern void change_phy_interface_mode(struct eth_device *dev,
557 enet_interface_e mode);
558 uec_regs = uec->uec_regs;
559
560 if (mii_info->link) {
561 /* Now we make sure that we can be in full duplex mode.
562 * If not, we operate in half-duplex mode. */
563 if (mii_info->duplex != uec->oldduplex) {
564 if (!(mii_info->duplex)) {
565 uec_set_mac_duplex(uec, DUPLEX_HALF);
566 printf("%s: Half Duplex\n", dev->name);
567 } else {
568 uec_set_mac_duplex(uec, DUPLEX_FULL);
569 printf("%s: Full Duplex\n", dev->name);
570 }
571 uec->oldduplex = mii_info->duplex;
572 }
573
574 if (mii_info->speed != uec->oldspeed) {
24c3aca3
DL		 575 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
576 switch (mii_info->speed) {
7737d5c6
DL		 577 case 1000:
578 break;
579 case 100:
580 printf ("switching to rgmii 100\n");
581 /* change phy to rgmii 100 */
582 change_phy_interface_mode(dev,
583 ENET_100_RGMII);
584 /* change the MAC interface mode */
585 uec_set_mac_if_mode(uec,ENET_100_RGMII);
586 break;
587 case 10:
588 printf ("switching to rgmii 10\n");
589 /* change phy to rgmii 10 */
590 change_phy_interface_mode(dev,
591 ENET_10_RGMII);
592 /* change the MAC interface mode */
593 uec_set_mac_if_mode(uec,ENET_10_RGMII);
594 break;
595 default:
596 printf("%s: Ack,Speed(%d)is illegal\n",
597 dev->name, mii_info->speed);
598 break;
24c3aca3 599 }
7737d5c6
DL		 600 }
601
602 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
603 uec->oldspeed = mii_info->speed;
604 }
605
606 if (!uec->oldlink) {
607 printf("%s: Link is up\n", dev->name);
608 uec->oldlink = 1;
609 }
610
611 } else { /* if (mii_info->link) */
612 if (uec->oldlink) {
613 printf("%s: Link is down\n", dev->name);
614 uec->oldlink = 0;
615 uec->oldspeed = 0;
616 uec->oldduplex = -1;
617 }
618 }
619}
620
621static void phy_change(struct eth_device *dev)
622{
623 uec_private_t *uec = (uec_private_t *)dev->priv;
7737d5c6
DL		 624
625 /* Update the link, speed, duplex */
ee62ed32 626 uec->mii_info->phyinfo->read_status(uec->mii_info);
7737d5c6
DL		 627
628 /* Adjust the interface according to speed */
ee62ed32 629 adjust_link(dev);
7737d5c6
DL		 630}
631
632static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
633{
634 uec_t *uec_regs;
635 u32 mac_addr1;
636 u32 mac_addr2;
637
638 if (!uec) {
639 printf("%s: uec not initial\n", __FUNCTION__);
640 return -EINVAL;
641 }
642
643 uec_regs = uec->uec_regs;
644
645 /* if a station address of 0x12345678ABCD, perform a write to
646 MACSTNADDR1 of 0xCDAB7856,
647 MACSTNADDR2 of 0x34120000 */
648
649 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
650 (mac_addr[3] << 8) | (mac_addr[2]);
651 out_be32(&uec_regs->macstnaddr1, mac_addr1);
652
653 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
654 out_be32(&uec_regs->macstnaddr2, mac_addr2);
655
656 return 0;
657}
658
659static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
660 int *threads_num_ret)
661{
662 int num_threads_numerica;
663
664 switch (threads_num) {
665 case UEC_NUM_OF_THREADS_1:
666 num_threads_numerica = 1;
667 break;
668 case UEC_NUM_OF_THREADS_2:
669 num_threads_numerica = 2;
670 break;
671 case UEC_NUM_OF_THREADS_4:
672 num_threads_numerica = 4;
673 break;
674 case UEC_NUM_OF_THREADS_6:
675 num_threads_numerica = 6;
676 break;
677 case UEC_NUM_OF_THREADS_8:
678 num_threads_numerica = 8;
679 break;
680 default:
681 printf("%s: Bad number of threads value.",
682 __FUNCTION__);
683 return -EINVAL;
684 }
685
686 *threads_num_ret = num_threads_numerica;
687
688 return 0;
689}
690
691static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
692{
693 uec_info_t *uec_info;
694 u32 end_bd;
695 u8 bmrx = 0;
696 int i;
697
698 uec_info = uec->uec_info;
699
700 /* Alloc global Tx parameter RAM page */
701 uec->tx_glbl_pram_offset = qe_muram_alloc(
702 sizeof(uec_tx_global_pram_t),
703 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
704 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
705 qe_muram_addr(uec->tx_glbl_pram_offset);
706
707 /* Zero the global Tx prameter RAM */
708 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
709
710 /* Init global Tx parameter RAM */
711
712 /* TEMODER, RMON statistics disable, one Tx queue */
713 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
714
715 /* SQPTR */
716 uec->send_q_mem_reg_offset = qe_muram_alloc(
717 sizeof(uec_send_queue_qd_t),
718 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
719 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
720 qe_muram_addr(uec->send_q_mem_reg_offset);
721 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
722
723 /* Setup the table with TxBDs ring */
724 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
725 * SIZEOFBD;
726 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
727 (u32)(uec->p_tx_bd_ring));
728 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
729 end_bd);
730
731 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
732 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
733
734 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
735 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
736
737 /* TSTATE, global snooping, big endian, the CSB bus selected */
738 bmrx = BMR_INIT_VALUE;
739 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
740
741 /* IPH_Offset */
742 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
743 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
744 }
745
746 /* VTAG table */
747 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
748 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
749 }
750
751 /* TQPTR */
752 uec->thread_dat_tx_offset = qe_muram_alloc(
753 num_threads_tx * sizeof(uec_thread_data_tx_t) +
754 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
755
756 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
757 qe_muram_addr(uec->thread_dat_tx_offset);
758 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
759}
760
761static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
762{
763 u8 bmrx = 0;
764 int i;
765 uec_82xx_address_filtering_pram_t *p_af_pram;
766
767 /* Allocate global Rx parameter RAM page */
768 uec->rx_glbl_pram_offset = qe_muram_alloc(
769 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
770 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
771 qe_muram_addr(uec->rx_glbl_pram_offset);
772
773 /* Zero Global Rx parameter RAM */
774 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
775
776 /* Init global Rx parameter RAM */
777 /* REMODER, Extended feature mode disable, VLAN disable,
778 LossLess flow control disable, Receive firmware statisic disable,
779 Extended address parsing mode disable, One Rx queues,
780 Dynamic maximum/minimum frame length disable, IP checksum check
781 disable, IP address alignment disable
782 */
783 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
784
785 /* RQPTR */
786 uec->thread_dat_rx_offset = qe_muram_alloc(
787 num_threads_rx * sizeof(uec_thread_data_rx_t),
788 UEC_THREAD_DATA_ALIGNMENT);
789 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
790 qe_muram_addr(uec->thread_dat_rx_offset);
791 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
792
793 /* Type_or_Len */
794 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
795
796 /* RxRMON base pointer, we don't need it */
797 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
798
799 /* IntCoalescingPTR, we don't need it, no interrupt */
800 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
801
802 /* RSTATE, global snooping, big endian, the CSB bus selected */
803 bmrx = BMR_INIT_VALUE;
804 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
805
806 /* MRBLR */
807 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
808
809 /* RBDQPTR */
810 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
811 sizeof(uec_rx_bd_queues_entry_t) + \
812 sizeof(uec_rx_prefetched_bds_t),
813 UEC_RX_BD_QUEUES_ALIGNMENT);
814 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
815 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
816
817 /* Zero it */
818 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
819 sizeof(uec_rx_prefetched_bds_t));
820 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
821 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
822 (u32)uec->p_rx_bd_ring);
823
824 /* MFLR */
825 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
826 /* MINFLR */
827 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
828 /* MAXD1 */
829 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
830 /* MAXD2 */
831 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
832 /* ECAM_PTR */
833 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
834 /* L2QT */
835 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
836 /* L3QT */
837 for (i = 0; i < 8; i++) {
838 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
839 }
840
841 /* VLAN_TYPE */
842 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
843 /* TCI */
844 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
845
846 /* Clear PQ2 style address filtering hash table */
847 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
848 uec->p_rx_glbl_pram->addressfiltering;
849
850 p_af_pram->iaddr_h = 0;
851 p_af_pram->iaddr_l = 0;
852 p_af_pram->gaddr_h = 0;
853 p_af_pram->gaddr_l = 0;
854}
855
856static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
857 int thread_tx, int thread_rx)
858{
859 uec_init_cmd_pram_t *p_init_enet_param;
860 u32 init_enet_param_offset;
861 uec_info_t *uec_info;
862 int i;
863 int snum;
864 u32 init_enet_offset;
865 u32 entry_val;
866 u32 command;
867 u32 cecr_subblock;
868
869 uec_info = uec->uec_info;
870
871 /* Allocate init enet command parameter */
872 uec->init_enet_param_offset = qe_muram_alloc(
873 sizeof(uec_init_cmd_pram_t), 4);
874 init_enet_param_offset = uec->init_enet_param_offset;
875 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
876 qe_muram_addr(uec->init_enet_param_offset);
877
878 /* Zero init enet command struct */
879 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
880
881 /* Init the command struct */
882 p_init_enet_param = uec->p_init_enet_param;
883 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
884 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
885 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
886 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
887 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
888 p_init_enet_param->largestexternallookupkeysize = 0;
889
890 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
891 << ENET_INIT_PARAM_RGF_SHIFT;
892 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
893 << ENET_INIT_PARAM_TGF_SHIFT;
894
895 /* Init Rx global parameter pointer */
896 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
897 (u32)uec_info->riscRx;
898
899 /* Init Rx threads */
900 for (i = 0; i < (thread_rx + 1); i++) {
901 if ((snum = qe_get_snum()) < 0) {
902 printf("%s can not get snum\n", __FUNCTION__);
903 return -ENOMEM;
904 }
905
906 if (i==0) {
907 init_enet_offset = 0;
908 } else {
909 init_enet_offset = qe_muram_alloc(
910 sizeof(uec_thread_rx_pram_t),
911 UEC_THREAD_RX_PRAM_ALIGNMENT);
912 }
913
914 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
915 init_enet_offset | (u32)uec_info->riscRx;
916 p_init_enet_param->rxthread[i] = entry_val;
917 }
918
919 /* Init Tx global parameter pointer */
920 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
921 (u32)uec_info->riscTx;
922
923 /* Init Tx threads */
924 for (i = 0; i < thread_tx; i++) {
925 if ((snum = qe_get_snum()) < 0) {
926 printf("%s can not get snum\n", __FUNCTION__);
927 return -ENOMEM;
928 }
929
930 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
931 UEC_THREAD_TX_PRAM_ALIGNMENT);
932
933 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
934 init_enet_offset | (u32)uec_info->riscTx;
935 p_init_enet_param->txthread[i] = entry_val;
936 }
937
938 __asm__ __volatile__("sync");
939
940 /* Issue QE command */
941 command = QE_INIT_TX_RX;
942 cecr_subblock = ucc_fast_get_qe_cr_subblock(
943 uec->uec_info->uf_info.ucc_num);
944 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
945 init_enet_param_offset);
946
947 return 0;
948}
949
950static int uec_startup(uec_private_t *uec)
951{
952 uec_info_t *uec_info;
953 ucc_fast_info_t *uf_info;
954 ucc_fast_private_t *uccf;
955 ucc_fast_t *uf_regs;
956 uec_t *uec_regs;
957 int num_threads_tx;
958 int num_threads_rx;
959 u32 utbipar;
960 enet_interface_e enet_interface;
961 u32 length;
962 u32 align;
963 qe_bd_t *bd;
964 u8 *buf;
965 int i;
966
967 if (!uec || !uec->uec_info) {
968 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
969 return -EINVAL;
970 }
971
972 uec_info = uec->uec_info;
973 uf_info = &(uec_info->uf_info);
974
975 /* Check if Rx BD ring len is illegal */
976 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
977 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
978 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
979 __FUNCTION__);
980 return -EINVAL;
981 }
982
983 /* Check if Tx BD ring len is illegal */
984 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
985 printf("%s: Tx BD ring length must not be smaller than 2.\n",
986 __FUNCTION__);
987 return -EINVAL;
988 }
989
990 /* Check if MRBLR is illegal */
991 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
992 printf("%s: max rx buffer length must be mutliple of 128.\n",
993 __FUNCTION__);
994 return -EINVAL;
995 }
996
997 /* Both Rx and Tx are stopped */
998 uec->grace_stopped_rx = 1;
999 uec->grace_stopped_tx = 1;
1000
1001 /* Init UCC fast */
1002 if (ucc_fast_init(uf_info, &uccf)) {
1003 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1004 return -ENOMEM;
1005 }
1006
1007 /* Save uccf */
1008 uec->uccf = uccf;
1009
1010 /* Convert the Tx threads number */
1011 if (uec_convert_threads_num(uec_info->num_threads_tx,
1012 &num_threads_tx)) {
1013 return -EINVAL;
1014 }
1015
1016 /* Convert the Rx threads number */
1017 if (uec_convert_threads_num(uec_info->num_threads_rx,
1018 &num_threads_rx)) {
1019 return -EINVAL;
1020 }
1021
1022 uf_regs = uccf->uf_regs;
1023
1024 /* UEC register is following UCC fast registers */
1025 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1026
1027 /* Save the UEC register pointer to UEC private struct */
1028 uec->uec_regs = uec_regs;
1029
1030 /* Init UPSMR, enable hardware statistics (UCC) */
1031 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1032
1033 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1034 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1035
1036 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1037 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1038
1039 /* Setup MAC interface mode */
1040 uec_set_mac_if_mode(uec, uec_info->enet_interface);
1041
da9d4610
AF		 1042 /* Setup MII management base */
1043#ifndef CONFIG_eTSEC_MDIO_BUS
1044 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1045#else
1046 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1047#endif
1048
7737d5c6
DL		 1049 /* Setup MII master clock source */
1050 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1051
1052 /* Setup UTBIPAR */
1053 utbipar = in_be32(&uec_regs->utbipar);
1054 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1055 enet_interface = uec->uec_info->enet_interface;
1056 if (enet_interface == ENET_1000_TBI ||
1057 enet_interface == ENET_1000_RTBI) {
1058 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1059 << UTBIPAR_PHY_ADDRESS_SHIFT;
1060 } else {
1061 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1062 << UTBIPAR_PHY_ADDRESS_SHIFT;
1063 }
1064
1065 out_be32(&uec_regs->utbipar, utbipar);
1066
1067 /* Allocate Tx BDs */
1068 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1069 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1070 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1071 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1072 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1073 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1074 }
1075
1076 align = UEC_TX_BD_RING_ALIGNMENT;
1077 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1078 if (uec->tx_bd_ring_offset != 0) {
1079 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1080 & ~(align - 1));
1081 }
1082
1083 /* Zero all of Tx BDs */
1084 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1085
1086 /* Allocate Rx BDs */
1087 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1088 align = UEC_RX_BD_RING_ALIGNMENT;
1089 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1090 if (uec->rx_bd_ring_offset != 0) {
1091 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1092 & ~(align - 1));
1093 }
1094
1095 /* Zero all of Rx BDs */
1096 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1097
1098 /* Allocate Rx buffer */
1099 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1100 align = UEC_RX_DATA_BUF_ALIGNMENT;
1101 uec->rx_buf_offset = (u32)malloc(length + align);
1102 if (uec->rx_buf_offset != 0) {
1103 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1104 & ~(align - 1));
1105 }
1106
1107 /* Zero all of the Rx buffer */
1108 memset((void *)(uec->rx_buf_offset), 0, length + align);
1109
1110 /* Init TxBD ring */
1111 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1112 uec->txBd = bd;
1113
1114 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1115 BD_DATA_CLEAR(bd);
1116 BD_STATUS_SET(bd, 0);
1117 BD_LENGTH_SET(bd, 0);
1118 bd ++;
1119 }
1120 BD_STATUS_SET((--bd), TxBD_WRAP);
1121
1122 /* Init RxBD ring */
1123 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1124 uec->rxBd = bd;
1125 buf = uec->p_rx_buf;
1126 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1127 BD_DATA_SET(bd, buf);
1128 BD_LENGTH_SET(bd, 0);
1129 BD_STATUS_SET(bd, RxBD_EMPTY);
1130 buf += MAX_RXBUF_LEN;
1131 bd ++;
1132 }
1133 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1134
1135 /* Init global Tx parameter RAM */
1136 uec_init_tx_parameter(uec, num_threads_tx);
1137
1138 /* Init global Rx parameter RAM */
1139 uec_init_rx_parameter(uec, num_threads_rx);
1140
1141 /* Init ethernet Tx and Rx parameter command */
1142 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1143 num_threads_rx)) {
1144 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1145 return -ENOMEM;
1146 }
1147
1148 return 0;
1149}
1150
1151static int uec_init(struct eth_device* dev, bd_t *bd)
1152{
1153 uec_private_t *uec;
ee62ed32
KP		 1154 int err, i;
1155 struct phy_info *curphy;
7737d5c6
DL		 1156
1157 uec = (uec_private_t *)dev->priv;
1158
1159 if (uec->the_first_run == 0) {
ee62ed32
KP		 1160 err = init_phy(dev);
1161 if (err) {
1162 printf("%s: Cannot initialize PHY, aborting.\n",
1163 dev->name);
1164 return err;
7737d5c6 1165 }
ee62ed32
KP		 1166
1167 curphy = uec->mii_info->phyinfo;
1168
1169 if (curphy->config_aneg) {
1170 err = curphy->config_aneg(uec->mii_info);
1171 if (err) {
1172 printf("%s: Can't negotiate PHY\n", dev->name);
1173 return err;
1174 }
1175 }
1176
1177 /* Give PHYs up to 5 sec to report a link */
1178 i = 50;
1179 do {
1180 err = curphy->read_status(uec->mii_info);
1181 udelay(100000);
1182 } while (((i-- > 0) && !uec->mii_info->link) || err);
1183
1184 if (err || i <= 0)
1185 printf("warning: %s: timeout on PHY link\n", dev->name);
1186
7737d5c6
DL		 1187 uec->the_first_run = 1;
1188 }
1189
ee62ed32
KP		 1190 /* Set up the MAC address */
1191 if (dev->enetaddr[0] & 0x01) {
1192 printf("%s: MacAddress is multcast address\n",
1193 __FUNCTION__);
1194 return -1;
1195 }
1196 uec_set_mac_address(uec, dev->enetaddr);
1197
1198
7737d5c6
DL		 1199 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1200 if (err) {
1201 printf("%s: cannot enable UEC device\n", dev->name);
422b1a01 1202 return -1;
7737d5c6
DL		 1203 }
1204
ee62ed32
KP		 1205 phy_change(dev);
1206
422b1a01 1207 return (uec->mii_info->link ? 0 : -1);
7737d5c6
DL		 1208}
1209
1210static void uec_halt(struct eth_device* dev)
1211{
1212 uec_private_t *uec = (uec_private_t *)dev->priv;
1213 uec_stop(uec, COMM_DIR_RX_AND_TX);
1214}
1215
1216static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1217{
1218 uec_private_t *uec;
1219 ucc_fast_private_t *uccf;
1220 volatile qe_bd_t *bd;
ddd02492 1221 u16 status;
7737d5c6
DL		 1222 int i;
1223 int result = 0;
1224
1225 uec = (uec_private_t *)dev->priv;
1226 uccf = uec->uccf;
1227 bd = uec->txBd;
1228
1229 /* Find an empty TxBD */
ddd02492 1230 for (i = 0; bd->status & TxBD_READY; i++) {
7737d5c6
DL		 1231 if (i > 0x100000) {
1232 printf("%s: tx buffer not ready\n", dev->name);
1233 return result;
1234 }
1235 }
1236
1237 /* Init TxBD */
1238 BD_DATA_SET(bd, buf);
1239 BD_LENGTH_SET(bd, len);
a28899c9 1240 status = bd->status;
7737d5c6
DL		 1241 status &= BD_WRAP;
1242 status |= (TxBD_READY | TxBD_LAST);
1243 BD_STATUS_SET(bd, status);
1244
1245 /* Tell UCC to transmit the buffer */
1246 ucc_fast_transmit_on_demand(uccf);
1247
1248 /* Wait for buffer to be transmitted */
ddd02492 1249 for (i = 0; bd->status & TxBD_READY; i++) {
7737d5c6
DL		 1250 if (i > 0x100000) {
1251 printf("%s: tx error\n", dev->name);
1252 return result;
1253 }
7737d5c6
DL		 1254 }
1255
1256 /* Ok, the buffer be transimitted */
1257 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1258 uec->txBd = bd;
1259 result = 1;
1260
1261 return result;
1262}
1263
1264static int uec_recv(struct eth_device* dev)
1265{
1266 uec_private_t *uec = dev->priv;
1267 volatile qe_bd_t *bd;
ddd02492 1268 u16 status;
7737d5c6
DL		 1269 u16 len;
1270 u8 *data;
1271
1272 bd = uec->rxBd;
ddd02492 1273 status = bd->status;
7737d5c6
DL		 1274
1275 while (!(status & RxBD_EMPTY)) {
1276 if (!(status & RxBD_ERROR)) {
1277 data = BD_DATA(bd);
1278 len = BD_LENGTH(bd);
1279 NetReceive(data, len);
1280 } else {
1281 printf("%s: Rx error\n", dev->name);
1282 }
1283 status &= BD_CLEAN;
1284 BD_LENGTH_SET(bd, 0);
1285 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1286 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
ddd02492 1287 status = bd->status;
7737d5c6
DL		 1288 }
1289 uec->rxBd = bd;
1290
1291 return 1;
1292}
1293
1294int uec_initialize(int index)
1295{
1296 struct eth_device *dev;
1297 int i;
1298 uec_private_t *uec;
1299 uec_info_t *uec_info;
1300 int err;
1301
1302 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1303 if (!dev)
1304 return 0;
1305 memset(dev, 0, sizeof(struct eth_device));
1306
1307 /* Allocate the UEC private struct */
1308 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1309 if (!uec) {
1310 return -ENOMEM;
1311 }
1312 memset(uec, 0, sizeof(uec_private_t));
1313
1314 /* Init UEC private struct, they come from board.h */
06c428bc 1315 uec_info = NULL;
7737d5c6
DL		 1316 if (index == 0) {
1317#ifdef CONFIG_UEC_ETH1
1318 uec_info = &eth1_uec_info;
1319#endif
1320 } else if (index == 1) {
1321#ifdef CONFIG_UEC_ETH2
1322 uec_info = &eth2_uec_info;
ccf21c31
JT		 1323#endif
1324 } else if (index == 2) {
1325#ifdef CONFIG_UEC_ETH3
1326 uec_info = &eth3_uec_info;
2465665b
DS		 1327#endif
1328 } else if (index == 3) {
1329#ifdef CONFIG_UEC_ETH4
1330 uec_info = &eth4_uec_info;
7737d5c6
DL		 1331#endif
1332 } else {
1333 printf("%s: index is illegal.\n", __FUNCTION__);
1334 return -EINVAL;
1335 }
1336
1337 uec->uec_info = uec_info;
1338
1339 sprintf(dev->name, "FSL UEC%d", index);
1340 dev->iobase = 0;
1341 dev->priv = (void *)uec;
1342 dev->init = uec_init;
1343 dev->halt = uec_halt;
1344 dev->send = uec_send;
1345 dev->recv = uec_recv;
1346
1347 /* Clear the ethnet address */
1348 for (i = 0; i < 6; i++)
1349 dev->enetaddr[i] = 0;
1350
1351 eth_register(dev);
1352
1353 err = uec_startup(uec);
1354 if (err) {
1355 printf("%s: Cannot configure net device, aborting.",dev->name);
1356 return err;
1357 }
1358
7737d5c6
DL		 1359 return 1;
1360}
1361#endif /* CONFIG_QE */
"Das U-Boot" Source Tree