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7737d5c6 | 1 | /* |
f8c42495 | 2 | * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. |
7737d5c6 DL |
3 | * |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * based on source code of Shlomi Gridish | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
7737d5c6 DL |
8 | */ |
9 | ||
10 | #ifndef __UEC_H__ | |
11 | #define __UEC_H__ | |
12 | ||
d77c779b | 13 | #include "uccf.h" |
2459afb1 | 14 | #include <fsl_qe.h> |
865ff856 | 15 | #include <phy.h> |
d77c779b | 16 | |
7737d5c6 DL |
17 | #define MAX_TX_THREADS 8 |
18 | #define MAX_RX_THREADS 8 | |
19 | #define MAX_TX_QUEUES 8 | |
20 | #define MAX_RX_QUEUES 8 | |
21 | #define MAX_PREFETCHED_BDS 4 | |
22 | #define MAX_IPH_OFFSET_ENTRY 8 | |
23 | #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 | |
24 | #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 | |
25 | ||
26 | /* UEC UPSMR (Protocol Specific Mode Register) | |
27 | */ | |
28 | #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ | |
29 | #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ | |
30 | #define UPSMR_PRO 0x00400000 /* Promiscuous */ | |
31 | #define UPSMR_CAP 0x00200000 /* CAM polarity */ | |
32 | #define UPSMR_RSH 0x00100000 /* Receive Short Frames */ | |
33 | #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ | |
34 | #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ | |
35 | #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ | |
36 | #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ | |
37 | #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ | |
38 | #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ | |
39 | #define UPSMR_BRO 0x00000200 /* Broadcast Address */ | |
40 | #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ | |
e8efef7c | 41 | #define UPSMR_SGMM 0x00000020 /* SGMII mode */ |
7737d5c6 DL |
42 | |
43 | #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) | |
44 | ||
45 | /* UEC MACCFG1 (MAC Configuration 1 Register) | |
46 | */ | |
47 | #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ | |
48 | #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ | |
49 | #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ | |
50 | #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ | |
51 | #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ | |
52 | #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ | |
53 | ||
54 | #define MACCFG1_INIT_VALUE (0) | |
55 | ||
56 | /* UEC MACCFG2 (MAC Configuration 2 Register) | |
57 | */ | |
58 | #define MACCFG2_PREL 0x00007000 | |
59 | #define MACCFG2_PREL_SHIFT (31 - 19) | |
60 | #define MACCFG2_PREL_MASK 0x0000f000 | |
61 | #define MACCFG2_SRP 0x00000080 | |
62 | #define MACCFG2_STP 0x00000040 | |
63 | #define MACCFG2_RESERVED_1 0x00000020 /* must be set */ | |
64 | #define MACCFG2_LC 0x00000010 /* Length Check */ | |
65 | #define MACCFG2_MPE 0x00000008 | |
66 | #define MACCFG2_FDX 0x00000001 /* Full Duplex */ | |
67 | #define MACCFG2_FDX_MASK 0x00000001 | |
68 | #define MACCFG2_PAD_CRC 0x00000004 | |
69 | #define MACCFG2_CRC_EN 0x00000002 | |
70 | #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 | |
71 | #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 | |
72 | #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 | |
73 | #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 | |
74 | #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 | |
75 | #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 | |
76 | ||
77 | #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ | |
78 | MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) | |
79 | ||
80 | /* UEC Event Register | |
81 | */ | |
82 | #define UCCE_MPD 0x80000000 | |
83 | #define UCCE_SCAR 0x40000000 | |
84 | #define UCCE_GRA 0x20000000 | |
85 | #define UCCE_CBPR 0x10000000 | |
86 | #define UCCE_BSY 0x08000000 | |
87 | #define UCCE_RXC 0x04000000 | |
88 | #define UCCE_TXC 0x02000000 | |
89 | #define UCCE_TXE 0x01000000 | |
90 | #define UCCE_TXB7 0x00800000 | |
91 | #define UCCE_TXB6 0x00400000 | |
92 | #define UCCE_TXB5 0x00200000 | |
93 | #define UCCE_TXB4 0x00100000 | |
94 | #define UCCE_TXB3 0x00080000 | |
95 | #define UCCE_TXB2 0x00040000 | |
96 | #define UCCE_TXB1 0x00020000 | |
97 | #define UCCE_TXB0 0x00010000 | |
98 | #define UCCE_RXB7 0x00008000 | |
99 | #define UCCE_RXB6 0x00004000 | |
100 | #define UCCE_RXB5 0x00002000 | |
101 | #define UCCE_RXB4 0x00001000 | |
102 | #define UCCE_RXB3 0x00000800 | |
103 | #define UCCE_RXB2 0x00000400 | |
104 | #define UCCE_RXB1 0x00000200 | |
105 | #define UCCE_RXB0 0x00000100 | |
106 | #define UCCE_RXF7 0x00000080 | |
107 | #define UCCE_RXF6 0x00000040 | |
108 | #define UCCE_RXF5 0x00000020 | |
109 | #define UCCE_RXF4 0x00000010 | |
110 | #define UCCE_RXF3 0x00000008 | |
111 | #define UCCE_RXF2 0x00000004 | |
112 | #define UCCE_RXF1 0x00000002 | |
113 | #define UCCE_RXF0 0x00000001 | |
114 | ||
115 | #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ | |
116 | UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) | |
117 | #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ | |
118 | UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) | |
119 | #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ | |
120 | UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) | |
121 | #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ | |
122 | UCCE_RXC | UCCE_TXC | UCCE_TXE) | |
123 | ||
124 | /* UEC TEMODR Register | |
125 | */ | |
126 | #define TEMODER_SCHEDULER_ENABLE 0x2000 | |
127 | #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 | |
128 | #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 | |
129 | #define TEMODER_RMON_STATISTICS 0x0100 | |
130 | #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) | |
131 | ||
132 | #define TEMODER_INIT_VALUE 0xc000 | |
133 | ||
134 | /* UEC REMODR Register | |
135 | */ | |
136 | #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 | |
137 | #define REMODER_RX_EXTENDED_FEATURES 0x80000000 | |
138 | #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) | |
139 | #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) | |
140 | #define REMODER_RX_QOS_MODE_SHIFT (31-15) | |
141 | #define REMODER_RMON_STATISTICS 0x00001000 | |
142 | #define REMODER_RX_EXTENDED_FILTERING 0x00000800 | |
143 | #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) | |
144 | #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 | |
145 | #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 | |
146 | #define REMODER_IP_CHECKSUM_CHECK 0x00000002 | |
147 | #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 | |
148 | ||
149 | #define REMODER_INIT_VALUE 0 | |
150 | ||
151 | /* BMRx - Bus Mode Register */ | |
152 | #define BMR_GLB 0x20 | |
153 | #define BMR_BO_BE 0x10 | |
154 | #define BMR_DTB_SECONDARY_BUS 0x02 | |
155 | #define BMR_BDB_SECONDARY_BUS 0x01 | |
156 | ||
157 | #define BMR_SHIFT 24 | |
158 | #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) | |
159 | ||
160 | /* UEC UCCS (Ethernet Status Register) | |
161 | */ | |
162 | #define UCCS_BPR 0x02 | |
163 | #define UCCS_PAU 0x02 | |
164 | #define UCCS_MPD 0x01 | |
165 | ||
166 | /* UEC MIIMCFG (MII Management Configuration Register) | |
167 | */ | |
168 | #define MIIMCFG_RESET_MANAGEMENT 0x80000000 | |
169 | #define MIIMCFG_NO_PREAMBLE 0x00000010 | |
170 | #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) | |
171 | #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f | |
172 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 | |
173 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 | |
174 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 | |
175 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 | |
176 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 | |
177 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 | |
178 | #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 | |
179 | ||
180 | #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ | |
181 | MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 | |
182 | ||
183 | /* UEC MIIMCOM (MII Management Command Register) | |
184 | */ | |
185 | #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ | |
186 | #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ | |
187 | ||
188 | /* UEC MIIMADD (MII Management Address Register) | |
189 | */ | |
190 | #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) | |
191 | #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) | |
192 | ||
193 | /* UEC MIIMCON (MII Management Control Register) | |
194 | */ | |
195 | #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) | |
196 | #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) | |
197 | ||
198 | /* UEC MIIMIND (MII Management Indicator Register) | |
199 | */ | |
200 | #define MIIMIND_NOT_VALID 0x00000004 | |
201 | #define MIIMIND_SCAN 0x00000002 | |
202 | #define MIIMIND_BUSY 0x00000001 | |
203 | ||
204 | /* UEC UTBIPAR (Ten Bit Interface Physical Address Register) | |
205 | */ | |
206 | #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) | |
207 | #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f | |
208 | ||
209 | /* UEC UESCR (Ethernet Statistics Control Register) | |
210 | */ | |
211 | #define UESCR_AUTOZ 0x8000 | |
212 | #define UESCR_CLRCNT 0x4000 | |
213 | #define UESCR_MAXCOV_SHIFT (15 - 7) | |
214 | #define UESCR_SCOV_SHIFT (15 - 15) | |
215 | ||
216 | /****** Tx data struct collection ******/ | |
217 | /* Tx thread data, each Tx thread has one this struct. | |
218 | */ | |
219 | typedef struct uec_thread_data_tx { | |
220 | u8 res0[136]; | |
221 | } __attribute__ ((packed)) uec_thread_data_tx_t; | |
222 | ||
223 | /* Tx thread parameter, each Tx thread has one this struct. | |
224 | */ | |
225 | typedef struct uec_thread_tx_pram { | |
226 | u8 res0[64]; | |
227 | } __attribute__ ((packed)) uec_thread_tx_pram_t; | |
228 | ||
229 | /* Send queue queue-descriptor, each Tx queue has one this QD | |
230 | */ | |
231 | typedef struct uec_send_queue_qd { | |
232 | u32 bd_ring_base; /* pointer to BD ring base address */ | |
233 | u8 res0[0x8]; | |
234 | u32 last_bd_completed_address; /* last entry in BD ring */ | |
235 | u8 res1[0x30]; | |
236 | } __attribute__ ((packed)) uec_send_queue_qd_t; | |
237 | ||
238 | /* Send queue memory region */ | |
239 | typedef struct uec_send_queue_mem_region { | |
240 | uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; | |
241 | } __attribute__ ((packed)) uec_send_queue_mem_region_t; | |
242 | ||
243 | /* Scheduler struct | |
244 | */ | |
245 | typedef struct uec_scheduler { | |
246 | u16 cpucount0; /* CPU packet counter */ | |
247 | u16 cpucount1; /* CPU packet counter */ | |
248 | u16 cecount0; /* QE packet counter */ | |
249 | u16 cecount1; /* QE packet counter */ | |
250 | u16 cpucount2; /* CPU packet counter */ | |
251 | u16 cpucount3; /* CPU packet counter */ | |
252 | u16 cecount2; /* QE packet counter */ | |
253 | u16 cecount3; /* QE packet counter */ | |
254 | u16 cpucount4; /* CPU packet counter */ | |
255 | u16 cpucount5; /* CPU packet counter */ | |
256 | u16 cecount4; /* QE packet counter */ | |
257 | u16 cecount5; /* QE packet counter */ | |
258 | u16 cpucount6; /* CPU packet counter */ | |
259 | u16 cpucount7; /* CPU packet counter */ | |
260 | u16 cecount6; /* QE packet counter */ | |
261 | u16 cecount7; /* QE packet counter */ | |
262 | u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ | |
263 | u32 rtsrshadow; /* temporary variable handled by QE */ | |
264 | u32 time; /* temporary variable handled by QE */ | |
265 | u32 ttl; /* temporary variable handled by QE */ | |
266 | u32 mblinterval; /* max burst length interval */ | |
267 | u16 nortsrbytetime; /* normalized value of byte time in tsr units */ | |
268 | u8 fracsiz; | |
269 | u8 res0[1]; | |
270 | u8 strictpriorityq; /* Strict Priority Mask register */ | |
271 | u8 txasap; /* Transmit ASAP register */ | |
272 | u8 extrabw; /* Extra BandWidth register */ | |
273 | u8 oldwfqmask; /* temporary variable handled by QE */ | |
274 | u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ | |
275 | u32 minw; /* temporary variable handled by QE */ | |
276 | u8 res1[0x70-0x64]; | |
277 | } __attribute__ ((packed)) uec_scheduler_t; | |
278 | ||
279 | /* Tx firmware counters | |
280 | */ | |
281 | typedef struct uec_tx_firmware_statistics_pram { | |
282 | u32 sicoltx; /* single collision */ | |
283 | u32 mulcoltx; /* multiple collision */ | |
284 | u32 latecoltxfr; /* late collision */ | |
285 | u32 frabortduecol; /* frames aborted due to tx collision */ | |
286 | u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ | |
287 | u32 carriersenseertx; /* carrier sense error */ | |
288 | u32 frtxok; /* frames transmitted OK */ | |
289 | u32 txfrexcessivedefer; | |
290 | u32 txpkts256; /* total packets(including bad) 256~511 B */ | |
291 | u32 txpkts512; /* total packets(including bad) 512~1023B */ | |
292 | u32 txpkts1024; /* total packets(including bad) 1024~1518B */ | |
293 | u32 txpktsjumbo; /* total packets(including bad) >1024 */ | |
294 | } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; | |
295 | ||
296 | /* Tx global parameter table | |
297 | */ | |
298 | typedef struct uec_tx_global_pram { | |
299 | u16 temoder; | |
300 | u8 res0[0x38-0x02]; | |
301 | u32 sqptr; | |
302 | u32 schedulerbasepointer; | |
303 | u32 txrmonbaseptr; | |
304 | u32 tstate; | |
305 | u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; | |
306 | u32 vtagtable[0x8]; | |
307 | u32 tqptr; | |
308 | u8 res2[0x80-0x74]; | |
309 | } __attribute__ ((packed)) uec_tx_global_pram_t; | |
310 | ||
311 | ||
312 | /****** Rx data struct collection ******/ | |
313 | /* Rx thread data, each Rx thread has one this struct. | |
314 | */ | |
315 | typedef struct uec_thread_data_rx { | |
316 | u8 res0[40]; | |
317 | } __attribute__ ((packed)) uec_thread_data_rx_t; | |
318 | ||
319 | /* Rx thread parameter, each Rx thread has one this struct. | |
320 | */ | |
321 | typedef struct uec_thread_rx_pram { | |
322 | u8 res0[128]; | |
323 | } __attribute__ ((packed)) uec_thread_rx_pram_t; | |
324 | ||
325 | /* Rx firmware counters | |
326 | */ | |
327 | typedef struct uec_rx_firmware_statistics_pram { | |
328 | u32 frrxfcser; /* frames with crc error */ | |
329 | u32 fraligner; /* frames with alignment error */ | |
330 | u32 inrangelenrxer; /* in range length error */ | |
331 | u32 outrangelenrxer; /* out of range length error */ | |
332 | u32 frtoolong; /* frame too long */ | |
333 | u32 runt; /* runt */ | |
334 | u32 verylongevent; /* very long event */ | |
335 | u32 symbolerror; /* symbol error */ | |
336 | u32 dropbsy; /* drop because of BD not ready */ | |
337 | u8 res0[0x8]; | |
338 | u32 mismatchdrop; /* drop because of MAC filtering */ | |
339 | u32 underpkts; /* total frames less than 64 octets */ | |
340 | u32 pkts256; /* total frames(including bad)256~511 B */ | |
341 | u32 pkts512; /* total frames(including bad)512~1023 B */ | |
342 | u32 pkts1024; /* total frames(including bad)1024~1518 B */ | |
343 | u32 pktsjumbo; /* total frames(including bad) >1024 B */ | |
344 | u32 frlossinmacer; | |
345 | u32 pausefr; /* pause frames */ | |
346 | u8 res1[0x4]; | |
347 | u32 removevlan; | |
348 | u32 replacevlan; | |
349 | u32 insertvlan; | |
350 | } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; | |
351 | ||
352 | /* Rx interrupt coalescing entry, each Rx queue has one this entry. | |
353 | */ | |
354 | typedef struct uec_rx_interrupt_coalescing_entry { | |
355 | u32 maxvalue; | |
356 | u32 counter; | |
357 | } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; | |
358 | ||
359 | typedef struct uec_rx_interrupt_coalescing_table { | |
360 | uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; | |
361 | } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; | |
362 | ||
363 | /* RxBD queue entry, each Rx queue has one this entry. | |
364 | */ | |
365 | typedef struct uec_rx_bd_queues_entry { | |
366 | u32 bdbaseptr; /* BD base pointer */ | |
367 | u32 bdptr; /* BD pointer */ | |
368 | u32 externalbdbaseptr; /* external BD base pointer */ | |
369 | u32 externalbdptr; /* external BD pointer */ | |
370 | } __attribute__ ((packed)) uec_rx_bd_queues_entry_t; | |
371 | ||
372 | /* Rx global paramter table | |
373 | */ | |
374 | typedef struct uec_rx_global_pram { | |
375 | u32 remoder; /* ethernet mode reg. */ | |
376 | u32 rqptr; /* base pointer to the Rx Queues */ | |
377 | u32 res0[0x1]; | |
378 | u8 res1[0x20-0xC]; | |
379 | u16 typeorlen; | |
380 | u8 res2[0x1]; | |
381 | u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ | |
382 | u32 rxrmonbaseptr; /* Rx RMON statistics base */ | |
383 | u8 res3[0x30-0x28]; | |
384 | u32 intcoalescingptr; /* Interrupt coalescing table pointer */ | |
385 | u8 res4[0x36-0x34]; | |
386 | u8 rstate; | |
387 | u8 res5[0x46-0x37]; | |
388 | u16 mrblr; /* max receive buffer length reg. */ | |
389 | u32 rbdqptr; /* RxBD parameter table description */ | |
390 | u16 mflr; /* max frame length reg. */ | |
391 | u16 minflr; /* min frame length reg. */ | |
392 | u16 maxd1; /* max dma1 length reg. */ | |
393 | u16 maxd2; /* max dma2 length reg. */ | |
394 | u32 ecamptr; /* external CAM address */ | |
395 | u32 l2qt; /* VLAN priority mapping table. */ | |
396 | u32 l3qt[0x8]; /* IP priority mapping table. */ | |
397 | u16 vlantype; /* vlan type */ | |
398 | u16 vlantci; /* default vlan tci */ | |
399 | u8 addressfiltering[64];/* address filtering data structure */ | |
400 | u32 exfGlobalParam; /* extended filtering global parameters */ | |
401 | u8 res6[0x100-0xC4]; /* Initialize to zero */ | |
402 | } __attribute__ ((packed)) uec_rx_global_pram_t; | |
403 | ||
404 | #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 | |
405 | ||
406 | ||
407 | /****** UEC common ******/ | |
408 | /* UCC statistics - hardware counters | |
409 | */ | |
410 | typedef struct uec_hardware_statistics { | |
411 | u32 tx64; | |
412 | u32 tx127; | |
413 | u32 tx255; | |
414 | u32 rx64; | |
415 | u32 rx127; | |
416 | u32 rx255; | |
417 | u32 txok; | |
418 | u16 txcf; | |
419 | u32 tmca; | |
420 | u32 tbca; | |
421 | u32 rxfok; | |
422 | u32 rxbok; | |
423 | u32 rbyt; | |
424 | u32 rmca; | |
425 | u32 rbca; | |
426 | } __attribute__ ((packed)) uec_hardware_statistics_t; | |
427 | ||
428 | /* InitEnet command parameter | |
429 | */ | |
430 | typedef struct uec_init_cmd_pram { | |
431 | u8 resinit0; | |
432 | u8 resinit1; | |
433 | u8 resinit2; | |
434 | u8 resinit3; | |
435 | u16 resinit4; | |
436 | u8 res1[0x1]; | |
437 | u8 largestexternallookupkeysize; | |
438 | u32 rgftgfrxglobal; | |
439 | u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ | |
440 | u8 res2[0x38 - 0x30]; | |
441 | u32 txglobal; /* tx global */ | |
442 | u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ | |
443 | u8 res3[0x1]; | |
444 | } __attribute__ ((packed)) uec_init_cmd_pram_t; | |
445 | ||
446 | #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) | |
447 | #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) | |
448 | ||
449 | #define ENET_INIT_PARAM_RISC_MASK 0x0000003f | |
450 | #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 | |
451 | #define ENET_INIT_PARAM_SNUM_MASK 0xff000000 | |
452 | #define ENET_INIT_PARAM_SNUM_SHIFT 24 | |
453 | ||
454 | #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 | |
455 | #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 | |
456 | #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff | |
457 | #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 | |
458 | #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 | |
459 | ||
460 | /* structure representing 82xx Address Filtering Enet Address in PRAM | |
461 | */ | |
462 | typedef struct uec_82xx_enet_address { | |
463 | u8 res1[0x2]; | |
464 | u16 h; /* address (MSB) */ | |
465 | u16 m; /* address */ | |
466 | u16 l; /* address (LSB) */ | |
467 | } __attribute__ ((packed)) uec_82xx_enet_address_t; | |
468 | ||
469 | /* structure representing 82xx Address Filtering PRAM | |
470 | */ | |
471 | typedef struct uec_82xx_address_filtering_pram { | |
472 | u32 iaddr_h; /* individual address filter, high */ | |
473 | u32 iaddr_l; /* individual address filter, low */ | |
474 | u32 gaddr_h; /* group address filter, high */ | |
475 | u32 gaddr_l; /* group address filter, low */ | |
476 | uec_82xx_enet_address_t taddr; | |
477 | uec_82xx_enet_address_t paddr[4]; | |
478 | u8 res0[0x40-0x38]; | |
479 | } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; | |
480 | ||
481 | /* Buffer Descriptor | |
482 | */ | |
483 | typedef struct buffer_descriptor { | |
484 | u16 status; | |
485 | u16 len; | |
486 | u32 data; | |
487 | } __attribute__ ((packed)) qe_bd_t, *p_bd_t; | |
488 | ||
489 | #define SIZEOFBD sizeof(qe_bd_t) | |
490 | ||
491 | /* Common BD flags | |
492 | */ | |
493 | #define BD_WRAP 0x2000 | |
494 | #define BD_INT 0x1000 | |
495 | #define BD_LAST 0x0800 | |
496 | #define BD_CLEAN 0x3000 | |
497 | ||
498 | /* TxBD status flags | |
499 | */ | |
500 | #define TxBD_READY 0x8000 | |
501 | #define TxBD_PADCRC 0x4000 | |
502 | #define TxBD_WRAP BD_WRAP | |
503 | #define TxBD_INT BD_INT | |
504 | #define TxBD_LAST BD_LAST | |
505 | #define TxBD_TXCRC 0x0400 | |
506 | #define TxBD_DEF 0x0200 | |
507 | #define TxBD_PP 0x0100 | |
508 | #define TxBD_LC 0x0080 | |
509 | #define TxBD_RL 0x0040 | |
510 | #define TxBD_RC 0x003C | |
511 | #define TxBD_UNDERRUN 0x0002 | |
512 | #define TxBD_TRUNC 0x0001 | |
513 | ||
514 | #define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) | |
515 | ||
516 | /* RxBD status flags | |
517 | */ | |
518 | #define RxBD_EMPTY 0x8000 | |
519 | #define RxBD_OWNER 0x4000 | |
520 | #define RxBD_WRAP BD_WRAP | |
521 | #define RxBD_INT BD_INT | |
522 | #define RxBD_LAST BD_LAST | |
523 | #define RxBD_FIRST 0x0400 | |
524 | #define RxBD_CMR 0x0200 | |
525 | #define RxBD_MISS 0x0100 | |
526 | #define RxBD_BCAST 0x0080 | |
527 | #define RxBD_MCAST 0x0040 | |
528 | #define RxBD_LG 0x0020 | |
529 | #define RxBD_NO 0x0010 | |
530 | #define RxBD_SHORT 0x0008 | |
531 | #define RxBD_CRCERR 0x0004 | |
532 | #define RxBD_OVERRUN 0x0002 | |
533 | #define RxBD_IPCH 0x0001 | |
534 | ||
535 | #define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ | |
536 | RxBD_CRCERR | RxBD_OVERRUN) | |
537 | ||
538 | /* BD access macros | |
539 | */ | |
540 | #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) | |
541 | #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) | |
542 | #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) | |
543 | #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) | |
544 | #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) | |
545 | #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) | |
546 | #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) | |
547 | #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) | |
548 | #define BD_ADVANCE(_bd,_status,_base) \ | |
549 | (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) | |
550 | ||
551 | /* Rx Prefetched BDs | |
552 | */ | |
553 | typedef struct uec_rx_prefetched_bds { | |
554 | qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ | |
555 | } __attribute__ ((packed)) uec_rx_prefetched_bds_t; | |
556 | ||
557 | /* Alignments | |
558 | */ | |
559 | #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 | |
560 | #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 | |
561 | #define UEC_THREAD_RX_PRAM_ALIGNMENT 128 | |
562 | #define UEC_THREAD_TX_PRAM_ALIGNMENT 64 | |
563 | #define UEC_THREAD_DATA_ALIGNMENT 256 | |
564 | #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 | |
565 | #define UEC_SCHEDULER_ALIGNMENT 4 | |
566 | #define UEC_TX_STATISTICS_ALIGNMENT 4 | |
567 | #define UEC_RX_STATISTICS_ALIGNMENT 4 | |
568 | #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 | |
569 | #define UEC_RX_BD_QUEUES_ALIGNMENT 8 | |
570 | #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 | |
571 | #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 | |
572 | #define UEC_RX_BD_RING_ALIGNMENT 32 | |
573 | #define UEC_TX_BD_RING_ALIGNMENT 32 | |
574 | #define UEC_MRBLR_ALIGNMENT 128 | |
575 | #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 | |
576 | #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 | |
577 | #define UEC_RX_DATA_BUF_ALIGNMENT 64 | |
578 | ||
579 | #define UEC_VLAN_PRIORITY_MAX 8 | |
580 | #define UEC_IP_PRIORITY_MAX 64 | |
581 | #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 | |
582 | #define UEC_RX_BD_RING_SIZE_MIN 8 | |
583 | #define UEC_TX_BD_RING_SIZE_MIN 2 | |
584 | ||
585 | /* Ethernet speed | |
586 | */ | |
587 | typedef enum enet_speed { | |
588 | ENET_SPEED_10BT, /* 10 Base T */ | |
589 | ENET_SPEED_100BT, /* 100 Base T */ | |
590 | ENET_SPEED_1000BT /* 1000 Base T */ | |
591 | } enet_speed_e; | |
592 | ||
593 | /* Ethernet Address Type. | |
594 | */ | |
595 | typedef enum enet_addr_type { | |
596 | ENET_ADDR_TYPE_INDIVIDUAL, | |
597 | ENET_ADDR_TYPE_GROUP, | |
598 | ENET_ADDR_TYPE_BROADCAST | |
599 | } enet_addr_type_e; | |
600 | ||
601 | /* TBI / MII Set Register | |
602 | */ | |
603 | typedef enum enet_tbi_mii_reg { | |
604 | ENET_TBI_MII_CR = 0x00, | |
605 | ENET_TBI_MII_SR = 0x01, | |
606 | ENET_TBI_MII_ANA = 0x04, | |
607 | ENET_TBI_MII_ANLPBPA = 0x05, | |
608 | ENET_TBI_MII_ANEX = 0x06, | |
609 | ENET_TBI_MII_ANNPT = 0x07, | |
610 | ENET_TBI_MII_ANLPANP = 0x08, | |
611 | ENET_TBI_MII_EXST = 0x0F, | |
612 | ENET_TBI_MII_JD = 0x10, | |
613 | ENET_TBI_MII_TBICON = 0x11 | |
614 | } enet_tbi_mii_reg_e; | |
615 | ||
e8efef7c HW |
616 | /* TBI MDIO register bit fields*/ |
617 | #define TBICON_CLK_SELECT 0x0020 | |
618 | #define TBIANA_ASYMMETRIC_PAUSE 0x0100 | |
619 | #define TBIANA_SYMMETRIC_PAUSE 0x0080 | |
620 | #define TBIANA_HALF_DUPLEX 0x0040 | |
621 | #define TBIANA_FULL_DUPLEX 0x0020 | |
622 | #define TBICR_PHY_RESET 0x8000 | |
623 | #define TBICR_ANEG_ENABLE 0x1000 | |
624 | #define TBICR_RESTART_ANEG 0x0200 | |
625 | #define TBICR_FULL_DUPLEX 0x0100 | |
626 | #define TBICR_SPEED1_SET 0x0040 | |
627 | ||
628 | #define TBIANA_SETTINGS ( \ | |
629 | TBIANA_ASYMMETRIC_PAUSE \ | |
630 | | TBIANA_SYMMETRIC_PAUSE \ | |
631 | | TBIANA_FULL_DUPLEX \ | |
632 | ) | |
633 | ||
634 | #define TBICR_SETTINGS ( \ | |
635 | TBICR_PHY_RESET \ | |
636 | | TBICR_ANEG_ENABLE \ | |
637 | | TBICR_FULL_DUPLEX \ | |
638 | | TBICR_SPEED1_SET \ | |
639 | ) | |
640 | ||
7737d5c6 DL |
641 | /* UEC number of threads |
642 | */ | |
643 | typedef enum uec_num_of_threads { | |
644 | UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ | |
645 | UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ | |
646 | UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ | |
647 | UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ | |
648 | UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ | |
649 | } uec_num_of_threads_e; | |
650 | ||
7737d5c6 DL |
651 | /* UEC initialization info struct |
652 | */ | |
8e55258f HW |
653 | #define STD_UEC_INFO(num) \ |
654 | { \ | |
655 | .uf_info = { \ | |
656 | .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ | |
657 | .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ | |
658 | .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ | |
659 | .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ | |
660 | }, \ | |
661 | .num_threads_tx = UEC_NUM_OF_THREADS_1, \ | |
662 | .num_threads_rx = UEC_NUM_OF_THREADS_1, \ | |
663 | .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ | |
664 | .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ | |
665 | .tx_bd_ring_len = 16, \ | |
666 | .rx_bd_ring_len = 16, \ | |
667 | .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ | |
582c55a0 HS |
668 | .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ |
669 | .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ | |
8e55258f HW |
670 | } |
671 | ||
7737d5c6 DL |
672 | typedef struct uec_info { |
673 | ucc_fast_info_t uf_info; | |
674 | uec_num_of_threads_e num_threads_tx; | |
675 | uec_num_of_threads_e num_threads_rx; | |
7211fbfa HW |
676 | unsigned int risc_tx; |
677 | unsigned int risc_rx; | |
7737d5c6 DL |
678 | u16 rx_bd_ring_len; |
679 | u16 tx_bd_ring_len; | |
680 | u8 phy_address; | |
865ff856 | 681 | phy_interface_t enet_interface_type; |
582c55a0 | 682 | int speed; |
7737d5c6 DL |
683 | } uec_info_t; |
684 | ||
685 | /* UEC driver initialized info | |
686 | */ | |
687 | #define MAX_RXBUF_LEN 1536 | |
688 | #define MAX_FRAME_LEN 1518 | |
689 | #define MIN_FRAME_LEN 64 | |
690 | #define MAX_DMA1_LEN 1520 | |
691 | #define MAX_DMA2_LEN 1520 | |
692 | ||
693 | /* UEC driver private struct | |
694 | */ | |
695 | typedef struct uec_private { | |
696 | uec_info_t *uec_info; | |
697 | ucc_fast_private_t *uccf; | |
698 | struct eth_device *dev; | |
699 | uec_t *uec_regs; | |
da9d4610 | 700 | uec_mii_t *uec_mii_regs; |
7737d5c6 DL |
701 | /* enet init command parameter */ |
702 | uec_init_cmd_pram_t *p_init_enet_param; | |
703 | u32 init_enet_param_offset; | |
704 | /* Rx and Tx paramter */ | |
705 | uec_rx_global_pram_t *p_rx_glbl_pram; | |
706 | u32 rx_glbl_pram_offset; | |
707 | uec_tx_global_pram_t *p_tx_glbl_pram; | |
708 | u32 tx_glbl_pram_offset; | |
709 | uec_send_queue_mem_region_t *p_send_q_mem_reg; | |
710 | u32 send_q_mem_reg_offset; | |
711 | uec_thread_data_tx_t *p_thread_data_tx; | |
712 | u32 thread_dat_tx_offset; | |
713 | uec_thread_data_rx_t *p_thread_data_rx; | |
714 | u32 thread_dat_rx_offset; | |
715 | uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; | |
716 | u32 rx_bd_qs_tbl_offset; | |
717 | /* BDs specific */ | |
718 | u8 *p_tx_bd_ring; | |
719 | u32 tx_bd_ring_offset; | |
720 | u8 *p_rx_bd_ring; | |
721 | u32 rx_bd_ring_offset; | |
722 | u8 *p_rx_buf; | |
723 | u32 rx_buf_offset; | |
724 | volatile qe_bd_t *txBd; | |
725 | volatile qe_bd_t *rxBd; | |
726 | /* Status */ | |
727 | int mac_tx_enabled; | |
728 | int mac_rx_enabled; | |
729 | int grace_stopped_tx; | |
730 | int grace_stopped_rx; | |
731 | int the_first_run; | |
732 | /* PHY specific */ | |
53677ef1 | 733 | struct uec_mii_info *mii_info; |
7737d5c6 DL |
734 | int oldspeed; |
735 | int oldduplex; | |
736 | int oldlink; | |
737 | } uec_private_t; | |
738 | ||
8e55258f HW |
739 | int uec_initialize(bd_t *bis, uec_info_t *uec_info); |
740 | int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num); | |
741 | int uec_standard_init(bd_t *bis); | |
7737d5c6 | 742 | #endif /* __UEC_H__ */ |