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Commit | Line | Data |
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89c1e2da SW |
1 | menu "Reset Controller Support" |
2 | ||
3 | config DM_RESET | |
4 | bool "Enable reset controllers using Driver Model" | |
5 | depends on DM && OF_CONTROL | |
6 | help | |
7 | Enable support for the reset controller driver class. Many hardware | |
8 | modules are equipped with a reset signal, typically driven by some | |
9 | reset controller hardware module within the chip. In U-Boot, reset | |
10 | controller drivers allow control over these reset signals. In some | |
11 | cases this API is applicable to chips outside the CPU as well, | |
12 | although driving such reset isgnals using GPIOs may be more | |
13 | appropriate in this case. | |
14 | ||
4581b717 SW |
15 | config SANDBOX_RESET |
16 | bool "Enable the sandbox reset test driver" | |
17 | depends on DM_MAILBOX && SANDBOX | |
18 | help | |
19 | Enable support for a test reset controller implementation, which | |
20 | simply accepts requests to reset various HW modules without actually | |
21 | doing anything beyond a little error checking. | |
22 | ||
584861ff PC |
23 | config STI_RESET |
24 | bool "Enable the STi reset" | |
25 | depends on ARCH_STI | |
26 | help | |
27 | Support for reset controllers on STMicroelectronics STiH407 family SoCs. | |
28 | Say Y if you want to control reset signals provided by system config | |
29 | block. | |
30 | ||
23a06416 PC |
31 | config STM32_RESET |
32 | bool "Enable the STM32 reset" | |
33 | depends on STM32 | |
34 | help | |
35 | Support for reset controllers on STMicroelectronics STM32 family SoCs. | |
36 | This resset driver is compatible with STM32 F4/F7 and H7 SoCs. | |
37 | ||
fe60f06d SW |
38 | config TEGRA_CAR_RESET |
39 | bool "Enable Tegra CAR-based reset driver" | |
40 | depends on TEGRA_CAR | |
41 | help | |
42 | Enable support for manipulating Tegra's on-SoC reset signals via | |
43 | direct register access to the Tegra CAR (Clock And Reset controller). | |
44 | ||
4dd99d14 SW |
45 | config TEGRA186_RESET |
46 | bool "Enable Tegra186 BPMP-based reset driver" | |
47 | depends on TEGRA186_BPMP | |
48 | help | |
49 | Enable support for manipulating Tegra's on-SoC reset signals via IPC | |
50 | requests to the BPMP (Boot and Power Management Processor). | |
51 | ||
18393f70 ÁFR |
52 | config RESET_BCM6345 |
53 | bool "Reset controller driver for BCM6345" | |
54 | depends on DM_RESET && ARCH_BMIPS | |
55 | help | |
56 | Support reset controller on BCM6345. | |
57 | ||
4fb96c48 MY |
58 | config RESET_UNIPHIER |
59 | bool "Reset controller driver for UniPhier SoCs" | |
60 | depends on ARCH_UNIPHIER | |
61 | default y | |
62 | help | |
63 | Support for reset controllers on UniPhier SoCs. | |
64 | Say Y if you want to control reset signals provided by System Control | |
65 | block, Media I/O block, Peripheral Block. | |
66 | ||
858d4976 | 67 | config AST2500_RESET |
68 | bool "Reset controller driver for AST2500 SoCs" | |
69 | depends on DM_RESET && WDT_ASPEED | |
70 | default y if ASPEED_AST2500 | |
71 | help | |
72 | Support for reset controller on AST2500 SoC. This controller uses | |
73 | watchdog to reset different peripherals and thus only supports | |
74 | resets that are supported by watchdog. The main limitation though | |
75 | is that some reset signals, like I2C or MISC reset multiple devices. | |
76 | ||
760188c1 EZ |
77 | config RESET_ROCKCHIP |
78 | bool "Reset controller driver for Rockchip SoCs" | |
79 | depends on DM_RESET && ARCH_ROCKCHIP && CLK | |
80 | default y | |
81 | help | |
82 | Support for reset controller on rockchip SoC. The main limitation | |
83 | though is that some reset signals, like I2C or MISC reset multiple | |
84 | devices. | |
85 | ||
89c1e2da | 86 | endmenu |