[people/ms/u-boot.git] / drivers / serial / serial_lpuart.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
#include <linux/compiler.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#define US1_TDRE	(1 << 7)
#define US1_RDRF	(1 << 5)
#define US1_OR		(1 << 3)
#define UC2_TE		(1 << 3)
#define UC2_RE		(1 << 2)
#define CFIFO_TXFLUSH	(1 << 7)
#define CFIFO_RXFLUSH	(1 << 6)
#define SFIFO_RXOF	(1 << 2)
#define SFIFO_RXUF	(1 << 0)

#define STAT_LBKDIF	(1 << 31)
#define STAT_RXEDGIF	(1 << 30)
#define STAT_TDRE	(1 << 23)
#define STAT_RDRF	(1 << 21)
#define STAT_IDLE	(1 << 20)
#define STAT_OR		(1 << 19)
#define STAT_NF		(1 << 18)
#define STAT_FE		(1 << 17)
#define STAT_PF		(1 << 16)
#define STAT_MA1F	(1 << 15)
#define STAT_MA2F	(1 << 14)
#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
			 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)

#define CTRL_TE		(1 << 19)
#define CTRL_RE		(1 << 18)

#define FIFO_TXFE		0x80
#define FIFO_RXFE		0x40

#define WATER_TXWATER_OFF	1
#define WATER_RXWATER_OFF	16

DECLARE_GLOBAL_DATA_PTR;

struct lpuart_serial_platdata {
	struct lpuart_fsl *reg;
};

#ifndef CONFIG_LPUART_32B_REG
static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
{
	u32 clk = mxc_get_clock(MXC_UART_CLK);
	u16 sbr;

	sbr = (u16)(clk / (16 * baudrate));

	/* place adjustment later - n/32 BRFA */
	__raw_writeb(sbr >> 8, &base->ubdh);
	__raw_writeb(sbr & 0xff, &base->ubdl);
}

static int _lpuart_serial_getc(struct lpuart_fsl *base)
{
	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
		WATCHDOG_RESET();

	barrier();

	return __raw_readb(&base->ud);
}

static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
{
	while (!(__raw_readb(&base->us1) & US1_TDRE))
		WATCHDOG_RESET();

	__raw_writeb(c, &base->ud);
}

/* Test whether a character is in the RX buffer */
static int _lpuart_serial_tstc(struct lpuart_fsl *base)
{
	if (__raw_readb(&base->urcfifo) == 0)
		return 0;

	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int _lpuart_serial_init(struct lpuart_fsl *base)
{
	u8 ctrl;

	ctrl = __raw_readb(&base->uc2);
	ctrl &= ~UC2_RE;
	ctrl &= ~UC2_TE;
	__raw_writeb(ctrl, &base->uc2);

	__raw_writeb(0, &base->umodem);
	__raw_writeb(0, &base->uc1);

	/* Disable FIFO and flush buffer */
	__raw_writeb(0x0, &base->upfifo);
	__raw_writeb(0x0, &base->utwfifo);
	__raw_writeb(0x1, &base->urwfifo);
	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);

	/* provide data bits, parity, stop bit, etc */
	_lpuart_serial_setbrg(base, gd->baudrate);

	__raw_writeb(UC2_RE | UC2_TE, &base->uc2);

	return 0;
}

static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	_lpuart_serial_setbrg(reg, baudrate);

	return 0;
}

static int lpuart_serial_getc(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	return _lpuart_serial_getc(reg);
}

static int lpuart_serial_putc(struct udevice *dev, const char c)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	_lpuart_serial_putc(reg, c);

	return 0;
}

static int lpuart_serial_pending(struct udevice *dev, bool input)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	if (input)
		return _lpuart_serial_tstc(reg);
	else
		return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
}

static int lpuart_serial_probe(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	return _lpuart_serial_init(reg);
}
#else

static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
{
	u32 clk = CONFIG_SYS_CLK_FREQ;
	u32 sbr;

	sbr = (clk / (16 * baudrate));

	/* place adjustment later - n/32 BRFA */
	out_be32(&base->baud, sbr);
}

static int _lpuart32_serial_getc(struct lpuart_fsl *base)
{
	u32 stat;

	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
		out_be32(&base->stat, STAT_FLAGS);
		WATCHDOG_RESET();
	}

	return in_be32(&base->data) & 0x3ff;
}

static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
{
	while (!(in_be32(&base->stat) & STAT_TDRE))
		WATCHDOG_RESET();

	out_be32(&base->data, c);
}

/* Test whether a character is in the RX buffer */
static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
{
	if ((in_be32(&base->water) >> 24) == 0)
		return 0;

	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int _lpuart32_serial_init(struct lpuart_fsl *base)
{
	u8 ctrl;

	ctrl = in_be32(&base->ctrl);
	ctrl &= ~CTRL_RE;
	ctrl &= ~CTRL_TE;
	out_be32(&base->ctrl, ctrl);

	out_be32(&base->modir, 0);
	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));

	out_be32(&base->match, 0);

	/* provide data bits, parity, stop bit, etc */
	_lpuart32_serial_setbrg(base, gd->baudrate);

	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);

	return 0;
}

static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	_lpuart32_serial_setbrg(reg, baudrate);

	return 0;
}

static int lpuart32_serial_getc(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	return _lpuart32_serial_getc(reg);
}

static int lpuart32_serial_putc(struct udevice *dev, const char c)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	_lpuart32_serial_putc(reg, c);

	return 0;
}

static int lpuart32_serial_pending(struct udevice *dev, bool input)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	if (input)
		return _lpuart32_serial_tstc(reg);
	else
		return in_be32(&reg->stat) & STAT_TDRE ? 0 : 1;
}

static int lpuart32_serial_probe(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	struct lpuart_fsl *reg = plat->reg;

	return _lpuart32_serial_init(reg);
}
#endif /* CONFIG_LPUART_32B_REG */

static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
{
	struct lpuart_serial_platdata *plat = dev->platdata;
	fdt_addr_t addr;

	addr = dev_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->reg = (struct lpuart_fsl *)addr;

	return 0;
}

#ifndef CONFIG_LPUART_32B_REG
static const struct dm_serial_ops lpuart_serial_ops = {
	.putc = lpuart_serial_putc,
	.pending = lpuart_serial_pending,
	.getc = lpuart_serial_getc,
	.setbrg = lpuart_serial_setbrg,
};

static const struct udevice_id lpuart_serial_ids[] = {
	{ .compatible = "fsl,vf610-lpuart" },
	{ }
};

U_BOOT_DRIVER(serial_lpuart) = {
	.name	= "serial_lpuart",
	.id	= UCLASS_SERIAL,
	.of_match = lpuart_serial_ids,
	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
	.probe = lpuart_serial_probe,
	.ops	= &lpuart_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
#else /* CONFIG_LPUART_32B_REG */
static const struct dm_serial_ops lpuart32_serial_ops = {
	.putc = lpuart32_serial_putc,
	.pending = lpuart32_serial_pending,
	.getc = lpuart32_serial_getc,
	.setbrg = lpuart32_serial_setbrg,
};

static const struct udevice_id lpuart32_serial_ids[] = {
	{ .compatible = "fsl,ls1021a-lpuart" },
	{ }
};

U_BOOT_DRIVER(serial_lpuart32) = {
	.name	= "serial_lpuart32",
	.id	= UCLASS_SERIAL,
	.of_match = lpuart32_serial_ids,
	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
	.probe = lpuart32_serial_probe,
	.ops	= &lpuart32_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_LPUART_32B_REG */
Commit	Line	Data
427eba70 AW	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
427eba70 AW	5	*/
	6
	7	#include <common.h>
fdbae099	8	#include <dm.h>
427eba70 AW	9	#include <watchdog.h>
	10	#include <asm/io.h>
	11	#include <serial.h>
	12	#include <linux/compiler.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <asm/arch/clock.h>
	15
47f1bfca BM	16	#define US1_TDRE (1 << 7)
	17	#define US1_RDRF (1 << 5)
	18	#define US1_OR (1 << 3)
	19	#define UC2_TE (1 << 3)
	20	#define UC2_RE (1 << 2)
	21	#define CFIFO_TXFLUSH (1 << 7)
	22	#define CFIFO_RXFLUSH (1 << 6)
	23	#define SFIFO_RXOF (1 << 2)
	24	#define SFIFO_RXUF (1 << 0)
427eba70	25
6209e14c JL	26	#define STAT_LBKDIF (1 << 31)
	27	#define STAT_RXEDGIF (1 << 30)
	28	#define STAT_TDRE (1 << 23)
	29	#define STAT_RDRF (1 << 21)
	30	#define STAT_IDLE (1 << 20)
	31	#define STAT_OR (1 << 19)
	32	#define STAT_NF (1 << 18)
	33	#define STAT_FE (1 << 17)
	34	#define STAT_PF (1 << 16)
	35	#define STAT_MA1F (1 << 15)
	36	#define STAT_MA2F (1 << 14)
	37	#define STAT_FLAGS (STAT_LBKDIF \| STAT_RXEDGIF \| STAT_IDLE \| STAT_OR \| \
47f1bfca	38	STAT_NF \| STAT_FE \| STAT_PF \| STAT_MA1F \| STAT_MA2F)
6209e14c JL	39
	40	#define CTRL_TE (1 << 19)
	41	#define CTRL_RE (1 << 18)
	42
	43	#define FIFO_TXFE 0x80
	44	#define FIFO_RXFE 0x40
	45
	46	#define WATER_TXWATER_OFF 1
	47	#define WATER_RXWATER_OFF 16
	48
427eba70 AW	49	DECLARE_GLOBAL_DATA_PTR;
427eba70 AW	50
fdbae099 BM	51	struct lpuart_serial_platdata {
	52	struct lpuart_fsl *reg;
	53	};
	54
6209e14c	55	#ifndef CONFIG_LPUART_32B_REG
6ca13b12	56	static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
427eba70 AW	57	{
	58	u32 clk = mxc_get_clock(MXC_UART_CLK);
	59	u16 sbr;
	60
6ca13b12	61	sbr = (u16)(clk / (16 * baudrate));
427eba70	62
47f1bfca	63	/* place adjustment later - n/32 BRFA */
427eba70 AW	64	__raw_writeb(sbr >> 8, &base->ubdh);
	65	__raw_writeb(sbr & 0xff, &base->ubdl);
	66	}
	67
6ca13b12	68	static int _lpuart_serial_getc(struct lpuart_fsl *base)
427eba70	69	{
a3db78d8	70	while (!(__raw_readb(&base->us1) & (US1_RDRF \| US1_OR)))
427eba70 AW	71	WATCHDOG_RESET();
427eba70 AW	72
a3db78d8	73	barrier();
427eba70 AW	74
	75	return __raw_readb(&base->ud);
	76	}
	77
6ca13b12	78	static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
427eba70	79	{
427eba70 AW	80	while (!(__raw_readb(&base->us1) & US1_TDRE))
	81	WATCHDOG_RESET();
	82
	83	__raw_writeb(c, &base->ud);
	84	}
	85
47f1bfca	86	/* Test whether a character is in the RX buffer */
6ca13b12	87	static int _lpuart_serial_tstc(struct lpuart_fsl *base)
427eba70 AW	88	{
	89	if (__raw_readb(&base->urcfifo) == 0)
	90	return 0;
	91
	92	return 1;
	93	}
	94
	95	/*
	96	* Initialise the serial port with the given baudrate. The settings
	97	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	98	*/
6ca13b12	99	static int _lpuart_serial_init(struct lpuart_fsl *base)
427eba70 AW	100	{
	101	u8 ctrl;
	102
	103	ctrl = __raw_readb(&base->uc2);
	104	ctrl &= ~UC2_RE;
	105	ctrl &= ~UC2_TE;
	106	__raw_writeb(ctrl, &base->uc2);
	107
	108	__raw_writeb(0, &base->umodem);
	109	__raw_writeb(0, &base->uc1);
	110
89e69fd4 SA	111	/* Disable FIFO and flush buffer */
	112	__raw_writeb(0x0, &base->upfifo);
	113	__raw_writeb(0x0, &base->utwfifo);
	114	__raw_writeb(0x1, &base->urwfifo);
	115	__raw_writeb(CFIFO_TXFLUSH \| CFIFO_RXFLUSH, &base->ucfifo);
	116
427eba70	117	/* provide data bits, parity, stop bit, etc */
6ca13b12	118	_lpuart_serial_setbrg(base, gd->baudrate);
427eba70 AW	119
	120	__raw_writeb(UC2_RE \| UC2_TE, &base->uc2);
	121
	122	return 0;
	123	}
	124
fdbae099 BM	125	static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
	126	{
	127	struct lpuart_serial_platdata *plat = dev->platdata;
	128	struct lpuart_fsl *reg = plat->reg;
	129
	130	_lpuart_serial_setbrg(reg, baudrate);
	131
	132	return 0;
	133	}
	134
	135	static int lpuart_serial_getc(struct udevice *dev)
	136	{
	137	struct lpuart_serial_platdata *plat = dev->platdata;
	138	struct lpuart_fsl *reg = plat->reg;
	139
	140	return _lpuart_serial_getc(reg);
	141	}
	142
	143	static int lpuart_serial_putc(struct udevice *dev, const char c)
	144	{
	145	struct lpuart_serial_platdata *plat = dev->platdata;
	146	struct lpuart_fsl *reg = plat->reg;
	147
	148	_lpuart_serial_putc(reg, c);
	149
	150	return 0;
	151	}
	152
	153	static int lpuart_serial_pending(struct udevice *dev, bool input)
	154	{
	155	struct lpuart_serial_platdata *plat = dev->platdata;
	156	struct lpuart_fsl *reg = plat->reg;
	157
	158	if (input)
	159	return _lpuart_serial_tstc(reg);
	160	else
	161	return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
	162	}
	163
	164	static int lpuart_serial_probe(struct udevice *dev)
	165	{
	166	struct lpuart_serial_platdata *plat = dev->platdata;
	167	struct lpuart_fsl *reg = plat->reg;
	168
	169	return _lpuart_serial_init(reg);
	170	}
6209e14c	171	#else
5160def2	172
6ca13b12	173	static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
6209e14c JL	174	{
	175	u32 clk = CONFIG_SYS_CLK_FREQ;
	176	u32 sbr;
	177
6ca13b12	178	sbr = (clk / (16 * baudrate));
6209e14c	179
47f1bfca	180	/* place adjustment later - n/32 BRFA */
6209e14c JL	181	out_be32(&base->baud, sbr);
	182	}
	183
6ca13b12	184	static int _lpuart32_serial_getc(struct lpuart_fsl *base)
6209e14c JL	185	{
	186	u32 stat;
	187
	188	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
	189	out_be32(&base->stat, STAT_FLAGS);
	190	WATCHDOG_RESET();
	191	}
	192
	193	return in_be32(&base->data) & 0x3ff;
	194	}
	195
6ca13b12	196	static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
6209e14c	197	{
6209e14c JL	198	while (!(in_be32(&base->stat) & STAT_TDRE))
	199	WATCHDOG_RESET();
	200
	201	out_be32(&base->data, c);
	202	}
	203
47f1bfca	204	/* Test whether a character is in the RX buffer */
6ca13b12	205	static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
6209e14c JL	206	{
	207	if ((in_be32(&base->water) >> 24) == 0)
	208	return 0;
	209
	210	return 1;
	211	}
	212
	213	/*
	214	* Initialise the serial port with the given baudrate. The settings
	215	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	216	*/
6ca13b12	217	static int _lpuart32_serial_init(struct lpuart_fsl *base)
6209e14c JL	218	{
	219	u8 ctrl;
	220
	221	ctrl = in_be32(&base->ctrl);
	222	ctrl &= ~CTRL_RE;
	223	ctrl &= ~CTRL_TE;
	224	out_be32(&base->ctrl, ctrl);
	225
	226	out_be32(&base->modir, 0);
	227	out_be32(&base->fifo, ~(FIFO_TXFE \| FIFO_RXFE));
	228
	229	out_be32(&base->match, 0);
6209e14c	230
47f1bfca	231	/* provide data bits, parity, stop bit, etc */
6ca13b12	232	_lpuart32_serial_setbrg(base, gd->baudrate);
6209e14c JL	233
	234	out_be32(&base->ctrl, CTRL_RE \| CTRL_TE);
	235
	236	return 0;
	237	}
	238
fdbae099 BM	239	static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
	240	{
	241	struct lpuart_serial_platdata *plat = dev->platdata;
	242	struct lpuart_fsl *reg = plat->reg;
	243
	244	_lpuart32_serial_setbrg(reg, baudrate);
	245
	246	return 0;
	247	}
	248
	249	static int lpuart32_serial_getc(struct udevice *dev)
	250	{
	251	struct lpuart_serial_platdata *plat = dev->platdata;
	252	struct lpuart_fsl *reg = plat->reg;
	253
	254	return _lpuart32_serial_getc(reg);
	255	}
	256
	257	static int lpuart32_serial_putc(struct udevice *dev, const char c)
	258	{
	259	struct lpuart_serial_platdata *plat = dev->platdata;
	260	struct lpuart_fsl *reg = plat->reg;
	261
	262	_lpuart32_serial_putc(reg, c);
	263
	264	return 0;
	265	}
	266
	267	static int lpuart32_serial_pending(struct udevice *dev, bool input)
	268	{
	269	struct lpuart_serial_platdata *plat = dev->platdata;
	270	struct lpuart_fsl *reg = plat->reg;
	271
	272	if (input)
	273	return _lpuart32_serial_tstc(reg);
	274	else
	275	return in_be32(&reg->stat) & STAT_TDRE ? 0 : 1;
	276	}
	277
	278	static int lpuart32_serial_probe(struct udevice *dev)
	279	{
	280	struct lpuart_serial_platdata *plat = dev->platdata;
	281	struct lpuart_fsl *reg = plat->reg;
	282
	283	return _lpuart32_serial_init(reg);
	284	}
5160def2	285	#endif /* CONFIG_LPUART_32B_REG */
427eba70	286
fdbae099 BM	287	static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
	288	{
	289	struct lpuart_serial_platdata *plat = dev->platdata;
	290	fdt_addr_t addr;
	291
	292	addr = dev_get_addr(dev);
	293	if (addr == FDT_ADDR_T_NONE)
	294	return -EINVAL;
	295
	296	plat->reg = (struct lpuart_fsl *)addr;
	297
	298	return 0;
	299	}
	300
	301	#ifndef CONFIG_LPUART_32B_REG
	302	static const struct dm_serial_ops lpuart_serial_ops = {
	303	.putc = lpuart_serial_putc,
	304	.pending = lpuart_serial_pending,
	305	.getc = lpuart_serial_getc,
	306	.setbrg = lpuart_serial_setbrg,
	307	};
	308
	309	static const struct udevice_id lpuart_serial_ids[] = {
	310	{ .compatible = "fsl,vf610-lpuart" },
	311	{ }
	312	};
	313
	314	U_BOOT_DRIVER(serial_lpuart) = {
	315	.name = "serial_lpuart",
	316	.id = UCLASS_SERIAL,
	317	.of_match = lpuart_serial_ids,
	318	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
	319	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
	320	.probe = lpuart_serial_probe,
	321	.ops = &lpuart_serial_ops,
	322	.flags = DM_FLAG_PRE_RELOC,
	323	};
	324	#else /* CONFIG_LPUART_32B_REG */
	325	static const struct dm_serial_ops lpuart32_serial_ops = {
	326	.putc = lpuart32_serial_putc,
	327	.pending = lpuart32_serial_pending,
	328	.getc = lpuart32_serial_getc,
	329	.setbrg = lpuart32_serial_setbrg,
	330	};
	331
	332	static const struct udevice_id lpuart32_serial_ids[] = {
	333	{ .compatible = "fsl,ls1021a-lpuart" },
	334	{ }
	335	};
	336
	337	U_BOOT_DRIVER(serial_lpuart32) = {
	338	.name = "serial_lpuart32",
	339	.id = UCLASS_SERIAL,
	340	.of_match = lpuart32_serial_ids,
	341	.ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
	342	.platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
	343	.probe = lpuart32_serial_probe,
	344	.ops = &lpuart32_serial_ops,
	345	.flags = DM_FLAG_PRE_RELOC,
	346	};
	347	#endif /* CONFIG_LPUART_32B_REG */