[people/ms/u-boot.git] / drivers / serial / serial_max3100.c

/*
 * (C) Copyright 2003
 *
 * Pantelis Antoniou <panto@intracom.gr>
 * Intracom S.A.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <watchdog.h>
#include <serial.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

/**************************************************************/

/* convienient macros */
#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)

#define MAX3100_SPI_TXD(x) \
	do { \
		if (x) \
			MAX3100_SPI_TXD_PORT |=  MAX3100_SPI_TXD_BIT; \
		else \
			MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
	} while(0)

#define MAX3100_SPI_CLK(x) \
	do { \
		if (x) \
			MAX3100_SPI_CLK_PORT |=  MAX3100_SPI_CLK_BIT; \
		else \
			MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
	} while(0)

#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)

#define MAX3100_CS(x) \
	do { \
		if (x) \
			MAX3100_CS_PORT |=  MAX3100_CS_BIT; \
		else \
			MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
	} while(0)

/**************************************************************/

/* MAX3100 definitions */

#define MAX3100_WC	(3 << 14)		/* write configuration */
#define MAX3100_RC	(1 << 14)		/* read  configuration */
#define MAX3100_WD	(2 << 14)		/* write data          */
#define MAX3100_RD	(0 << 14)		/* read  data          */

/* configuration register bits */
#define MAX3100_FEN	(1 << 13)		/* FIFO enable           */
#define MAX3100_SHDN    (1 << 12)		/* shutdown bit          */
#define MAX3100_TM	(1 << 11)		/* T bit irq mask        */
#define MAX3100_RM	(1 << 10)		/* R bit irq mask        */
#define MAX3100_PM	(1 <<  9)		/* P bit irq mask        */
#define MAX3100_RAM	(1 <<  8)		/* mask for RA/FE bit    */
#define MAX3100_IR	(1 <<  7)		/* IRDA timing mode      */
#define MAX3100_ST	(1 <<  6)		/* transmit stop bit     */
#define MAX3100_PE	(1 <<  5)		/* parity enable bit     */
#define MAX3100_L	(1 <<  4)		/* Length bit            */
#define MAX3100_B_MASK	(0x000F)		/* baud rate bits mask   */
#define MAX3100_B(x)	((x) & 0x000F)	/* baud rate select bits */

/* data register bits (write) */
#define MAX3100_TE	(1 << 10)		/* transmit enable bit (active low)        */
#define MAX3100_RTS	(1 <<  9)		/* request-to-send bit (inverted ~RTS pin) */

/* data register bits (read) */
#define MAX3100_RA	(1 << 10)		/* receiver activity when in shutdown mode */
#define MAX3100_FE	(1 << 10)		/* framing error when in normal mode       */
#define MAX3100_CTS	(1 <<  9)		/* clear-to-send bit (inverted ~CTS pin)   */

/* data register bits (both directions) */
#define MAX3100_R	(1 << 15)		/* receive bit    */
#define MAX3100_T	(1 << 14)		/* transmit bit   */
#define MAX3100_P	(1 <<  8)		/* parity bit     */
#define MAX3100_D_MASK	0x00FF                  /* data bits mask */
#define MAX3100_D(x)	((x) & 0x00FF)		/* data bits      */

/* these definitions are valid only for fOSC = 3.6864MHz */
#define MAX3100_B_230400        MAX3100_B(0)
#define MAX3100_B_115200        MAX3100_B(1)
#define MAX3100_B_57600         MAX3100_B(2)
#define MAX3100_B_38400         MAX3100_B(9)
#define MAX3100_B_19200         MAX3100_B(10)
#define MAX3100_B_9600          MAX3100_B(11)
#define MAX3100_B_4800          MAX3100_B(12)
#define MAX3100_B_2400          MAX3100_B(13)
#define MAX3100_B_1200          MAX3100_B(14)
#define MAX3100_B_600           MAX3100_B(15)

/**************************************************************/

static inline unsigned int max3100_transfer(unsigned int val)
{
	unsigned int rx;
	int b;

	MAX3100_SPI_CLK(0);
	MAX3100_CS(0);

	rx = 0; b = 16;
	while (--b >= 0) {
		MAX3100_SPI_TXD(val & 0x8000);
		val <<= 1;
		MAX3100_SPI_CLK_TOGGLE();
		udelay(1);
		rx <<= 1;
		if (MAX3100_SPI_RXD())
			rx |= 1;
		MAX3100_SPI_CLK_TOGGLE();
		udelay(1);
	}

	MAX3100_SPI_CLK(1);
	MAX3100_CS(1);

	return rx;
}

/**************************************************************/

/* must be power of 2 */
#define RXFIFO_SZ	16

static int rxfifo_cnt;
static int rxfifo_in;
static int rxfifo_out;
static unsigned char rxfifo_buf[16];

static void max3100_serial_putc_raw(int c)
{
	unsigned int rx;

	while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0)
		WATCHDOG_RESET();

	rx = max3100_transfer(MAX3100_WD | (c & 0xff));
	if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) {
		rxfifo_cnt++;
		rxfifo_buf[rxfifo_in++] = rx & 0xff;
		rxfifo_in &= RXFIFO_SZ - 1;
	}
}

static int max3100_serial_getc(void)
{
	int c;
	unsigned int rx;

	while (rxfifo_cnt == 0) {
		rx = max3100_transfer(MAX3100_RD);
		if ((rx & MAX3100_R) != 0) {
			do {
				rxfifo_cnt++;
				rxfifo_buf[rxfifo_in++] = rx & 0xff;
				rxfifo_in &= RXFIFO_SZ - 1;

				if (rxfifo_cnt >= RXFIFO_SZ)
					break;
			} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
		}
		WATCHDOG_RESET();
	}

	rxfifo_cnt--;
	c = rxfifo_buf[rxfifo_out++];
	rxfifo_out &= RXFIFO_SZ - 1;
	return c;
}

static int max3100_serial_tstc(void)
{
	unsigned int rx;

	if (rxfifo_cnt > 0)
		return 1;

	rx = max3100_transfer(MAX3100_RD);
	if ((rx & MAX3100_R) == 0)
		return 0;

	do {
		rxfifo_cnt++;
		rxfifo_buf[rxfifo_in++] = rx & 0xff;
		rxfifo_in &= RXFIFO_SZ - 1;

		if (rxfifo_cnt >= RXFIFO_SZ)
			break;
	} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);

	return 1;
}

static int max3100_serial_init(void)
{
	unsigned int wconf, rconf;
	int i;

	wconf = 0;

	/* Set baud rate */
	switch (gd->baudrate) {
		case 1200:
			wconf = MAX3100_B_1200;
			break;
		case 2400:
			wconf = MAX3100_B_2400;
			break;
		case 4800:
			wconf = MAX3100_B_4800;
			break;
		case 9600:
			wconf = MAX3100_B_9600;
			break;
		case 19200:
			wconf = MAX3100_B_19200;
			break;
		case 38400:
			wconf = MAX3100_B_38400;
			break;
		case 57600:
			wconf = MAX3100_B_57600;
			break;
		default:
		case 115200:
			wconf = MAX3100_B_115200;
			break;
		case 230400:
			wconf = MAX3100_B_230400;
			break;
	}

	/* try for 10ms, with a 100us gap */
	for (i = 0; i < 10000; i += 100) {

		max3100_transfer(MAX3100_WC | wconf);
		rconf = max3100_transfer(MAX3100_RC) & 0x3fff;

		if (rconf == wconf)
			break;
		udelay(100);
	}

	rxfifo_in = rxfifo_out = rxfifo_cnt = 0;

	return (0);
}

static void max3100_serial_putc(const char c)
{
	if (c == '\n')
		max3100_serial_putc_raw('\r');

	max3100_serial_putc_raw(c);
}

static void max3100_serial_puts(const char *s)
{
	while (*s)
		max3100_serial_putc_raw(*s++);
}

static void max3100_serial_setbrg(void)
{
}

static struct serial_device max3100_serial_drv = {
	.name	= "max3100_serial",
	.start	= max3100_serial_init,
	.stop	= NULL,
	.setbrg	= max3100_serial_setbrg,
	.putc	= max3100_serial_putc,
	.puts	= max3100_serial_puts,
	.getc	= max3100_serial_getc,
	.tstc	= max3100_serial_tstc,
};

void max3100_serial_initialize(void)
{
	serial_register(&max3100_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &max3100_serial_drv;
}
Commit	Line	Data
993cad93 WD	1	/*
	2	* (C) Copyright 2003
	3	*
	4	* Pantelis Antoniou <panto@intracom.gr>
	5	* Intracom S.A.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
993cad93 WD	8	*/
	9
	10	#include <common.h>
	11	#include <watchdog.h>
7cd851a5 MV	12	#include <serial.h>
7cd851a5 MV	13	#include <linux/compiler.h>
993cad93	14
d87080b7 WD	15	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	16
993cad93 WD	17	/**************************************************************/
	18
	19	/* convienient macros */
	20	#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)
	21
	22	#define MAX3100_SPI_TXD(x) \
	23	do { \
	24	if (x) \
	25	MAX3100_SPI_TXD_PORT \|= MAX3100_SPI_TXD_BIT; \
	26	else \
	27	MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
	28	} while(0)
	29
	30	#define MAX3100_SPI_CLK(x) \
	31	do { \
	32	if (x) \
	33	MAX3100_SPI_CLK_PORT \|= MAX3100_SPI_CLK_BIT; \
	34	else \
	35	MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
	36	} while(0)
	37
	38	#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)
	39
	40	#define MAX3100_CS(x) \
	41	do { \
	42	if (x) \
	43	MAX3100_CS_PORT \|= MAX3100_CS_BIT; \
	44	else \
	45	MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
	46	} while(0)
	47
	48	/**************************************************************/
	49
	50	/* MAX3100 definitions */
	51
	52	#define MAX3100_WC (3 << 14) /* write configuration */
	53	#define MAX3100_RC (1 << 14) /* read configuration */
	54	#define MAX3100_WD (2 << 14) /* write data */
	55	#define MAX3100_RD (0 << 14) /* read data */
	56
	57	/* configuration register bits */
	58	#define MAX3100_FEN (1 << 13) /* FIFO enable */
	59	#define MAX3100_SHDN (1 << 12) /* shutdown bit */
	60	#define MAX3100_TM (1 << 11) /* T bit irq mask */
	61	#define MAX3100_RM (1 << 10) /* R bit irq mask */
	62	#define MAX3100_PM (1 << 9) /* P bit irq mask */
	63	#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */
	64	#define MAX3100_IR (1 << 7) /* IRDA timing mode */
	65	#define MAX3100_ST (1 << 6) /* transmit stop bit */
	66	#define MAX3100_PE (1 << 5) /* parity enable bit */
	67	#define MAX3100_L (1 << 4) /* Length bit */
	68	#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */
	69	#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */
	70
	71	/* data register bits (write) */
	72	#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */
	73	#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */
	74
	75	/* data register bits (read) */
	76	#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */
	77	#define MAX3100_FE (1 << 10) /* framing error when in normal mode */
	78	#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */
	79
	80	/* data register bits (both directions) */
53677ef1	81	#define MAX3100_R (1 << 15) /* receive bit */
993cad93 WD	82	#define MAX3100_T (1 << 14) /* transmit bit */
	83	#define MAX3100_P (1 << 8) /* parity bit */
	84	#define MAX3100_D_MASK 0x00FF /* data bits mask */
	85	#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */
	86
	87	/* these definitions are valid only for fOSC = 3.6864MHz */
	88	#define MAX3100_B_230400 MAX3100_B(0)
	89	#define MAX3100_B_115200 MAX3100_B(1)
	90	#define MAX3100_B_57600 MAX3100_B(2)
	91	#define MAX3100_B_38400 MAX3100_B(9)
	92	#define MAX3100_B_19200 MAX3100_B(10)
	93	#define MAX3100_B_9600 MAX3100_B(11)
	94	#define MAX3100_B_4800 MAX3100_B(12)
	95	#define MAX3100_B_2400 MAX3100_B(13)
	96	#define MAX3100_B_1200 MAX3100_B(14)
	97	#define MAX3100_B_600 MAX3100_B(15)
	98
	99	/**************************************************************/
	100
	101	static inline unsigned int max3100_transfer(unsigned int val)
	102	{
	103	unsigned int rx;
	104	int b;
	105
	106	MAX3100_SPI_CLK(0);
	107	MAX3100_CS(0);
	108
	109	rx = 0; b = 16;
	110	while (--b >= 0) {
	111	MAX3100_SPI_TXD(val & 0x8000);
	112	val <<= 1;
	113	MAX3100_SPI_CLK_TOGGLE();
	114	udelay(1);
	115	rx <<= 1;
	116	if (MAX3100_SPI_RXD())
	117	rx \|= 1;
	118	MAX3100_SPI_CLK_TOGGLE();
	119	udelay(1);
	120	}
	121
	122	MAX3100_SPI_CLK(1);
	123	MAX3100_CS(1);
	124
	125	return rx;
	126	}
	127
	128	/**************************************************************/
	129
	130	/* must be power of 2 */
	131	#define RXFIFO_SZ 16
	132
	133	static int rxfifo_cnt;
	134	static int rxfifo_in;
	135	static int rxfifo_out;
	136	static unsigned char rxfifo_buf[16];
	137
7cd851a5	138	static void max3100_serial_putc_raw(int c)
993cad93 WD	139	{
	140	unsigned int rx;
	141
	142	while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0)
	143	WATCHDOG_RESET();
	144
	145	rx = max3100_transfer(MAX3100_WD \| (c & 0xff));
	146	if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) {
	147	rxfifo_cnt++;
	148	rxfifo_buf[rxfifo_in++] = rx & 0xff;
	149	rxfifo_in &= RXFIFO_SZ - 1;
	150	}
	151	}
	152
7cd851a5	153	static int max3100_serial_getc(void)
993cad93 WD	154	{
	155	int c;
	156	unsigned int rx;
	157
	158	while (rxfifo_cnt == 0) {
	159	rx = max3100_transfer(MAX3100_RD);
	160	if ((rx & MAX3100_R) != 0) {
	161	do {
	162	rxfifo_cnt++;
	163	rxfifo_buf[rxfifo_in++] = rx & 0xff;
	164	rxfifo_in &= RXFIFO_SZ - 1;
	165
	166	if (rxfifo_cnt >= RXFIFO_SZ)
	167	break;
	168	} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
	169	}
	170	WATCHDOG_RESET();
	171	}
	172
	173	rxfifo_cnt--;
	174	c = rxfifo_buf[rxfifo_out++];
	175	rxfifo_out &= RXFIFO_SZ - 1;
	176	return c;
	177	}
	178
7cd851a5	179	static int max3100_serial_tstc(void)
993cad93 WD	180	{
	181	unsigned int rx;
	182
	183	if (rxfifo_cnt > 0)
	184	return 1;
	185
	186	rx = max3100_transfer(MAX3100_RD);
	187	if ((rx & MAX3100_R) == 0)
	188	return 0;
	189
	190	do {
	191	rxfifo_cnt++;
	192	rxfifo_buf[rxfifo_in++] = rx & 0xff;
	193	rxfifo_in &= RXFIFO_SZ - 1;
	194
	195	if (rxfifo_cnt >= RXFIFO_SZ)
	196	break;
	197	} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
	198
	199	return 1;
	200	}
	201
7cd851a5	202	static int max3100_serial_init(void)
993cad93 WD	203	{
	204	unsigned int wconf, rconf;
	205	int i;
993cad93 WD	206
	207	wconf = 0;
	208
	209	/* Set baud rate */
	210	switch (gd->baudrate) {
	211	case 1200:
	212	wconf = MAX3100_B_1200;
	213	break;
	214	case 2400:
	215	wconf = MAX3100_B_2400;
	216	break;
	217	case 4800:
	218	wconf = MAX3100_B_4800;
	219	break;
	220	case 9600:
	221	wconf = MAX3100_B_9600;
	222	break;
	223	case 19200:
	224	wconf = MAX3100_B_19200;
	225	break;
	226	case 38400:
	227	wconf = MAX3100_B_38400;
	228	break;
	229	case 57600:
	230	wconf = MAX3100_B_57600;
	231	break;
	232	default:
	233	case 115200:
	234	wconf = MAX3100_B_115200;
	235	break;
	236	case 230400:
	237	wconf = MAX3100_B_230400;
	238	break;
	239	}
	240
	241	/* try for 10ms, with a 100us gap */
	242	for (i = 0; i < 10000; i += 100) {
	243
	244	max3100_transfer(MAX3100_WC \| wconf);
	245	rconf = max3100_transfer(MAX3100_RC) & 0x3fff;
	246
	247	if (rconf == wconf)
	248	break;
	249	udelay(100);
	250	}
	251
	252	rxfifo_in = rxfifo_out = rxfifo_cnt = 0;
	253
	254	return (0);
	255	}
	256
7cd851a5	257	static void max3100_serial_putc(const char c)
993cad93 WD	258	{
993cad93 WD	259	if (c == '\n')
7cd851a5	260	max3100_serial_putc_raw('\r');
993cad93	261
7cd851a5	262	max3100_serial_putc_raw(c);
993cad93 WD	263	}
993cad93 WD	264
7cd851a5	265	static void max3100_serial_puts(const char *s)
993cad93 WD	266	{
993cad93 WD	267	while (*s)
7cd851a5	268	max3100_serial_putc_raw(*s++);
993cad93 WD	269	}
993cad93 WD	270
7cd851a5	271	static void max3100_serial_setbrg(void)
993cad93	272	{
993cad93 WD	273	}
993cad93 WD	274
7cd851a5 MV	275	static struct serial_device max3100_serial_drv = {
	276	.name = "max3100_serial",
	277	.start = max3100_serial_init,
	278	.stop = NULL,
	279	.setbrg = max3100_serial_setbrg,
	280	.putc = max3100_serial_putc,
	281	.puts = max3100_serial_puts,
	282	.getc = max3100_serial_getc,
	283	.tstc = max3100_serial_tstc,
	284	};
	285
	286	void max3100_serial_initialize(void)
	287	{
	288	serial_register(&max3100_serial_drv);
	289	}
	290
	291	__weak struct serial_device *default_serial_console(void)
	292	{
	293	return &max3100_serial_drv;
	294	}