serial: mxc: Add debug uart support
[people/ms/u-boot.git] / drivers / serial / serial_mxc.c
CommitLineData
9b56f4f0
SH
1/*
2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
3 *
1a459660 4 * SPDX-License-Identifier: GPL-2.0+
9b56f4f0
SH
5 */
6
7#include <common.h>
a8ba569c
SG
8#include <dm.h>
9#include <errno.h>
4ec3d2a7 10#include <watchdog.h>
47d19da4
IY
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/clock.h>
86256b79 13#include <dm/platform_data/serial_mxc.h>
a943472c
MV
14#include <serial.h>
15#include <linux/compiler.h>
9b56f4f0 16
9b56f4f0 17/* UART Control Register Bit Fields.*/
52c14cab
JT
18#define URXD_CHARRDY (1<<15)
19#define URXD_ERR (1<<14)
20#define URXD_OVRRUN (1<<13)
21#define URXD_FRMERR (1<<12)
22#define URXD_BRK (1<<11)
23#define URXD_PRERR (1<<10)
24#define URXD_RX_DATA (0xFF)
25#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
26#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
27#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
28#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
29#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
30#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
31#define UCR1_IREN (1<<7) /* Infrared interface enable */
32#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
33#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
34#define UCR1_SNDBRK (1<<4) /* Send break */
35#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
36#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
37#define UCR1_DOZE (1<<1) /* Doze */
38#define UCR1_UARTEN (1<<0) /* UART enabled */
39#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
40#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
41#define UCR2_CTSC (1<<13) /* CTS pin control */
42#define UCR2_CTS (1<<12) /* Clear to send */
43#define UCR2_ESCEN (1<<11) /* Escape enable */
44#define UCR2_PREN (1<<8) /* Parity enable */
45#define UCR2_PROE (1<<7) /* Parity odd/even */
46#define UCR2_STPB (1<<6) /* Stop */
47#define UCR2_WS (1<<5) /* Word size */
48#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
49#define UCR2_TXEN (1<<2) /* Transmitter enabled */
50#define UCR2_RXEN (1<<1) /* Receiver enabled */
51#define UCR2_SRST (1<<0) /* SW reset */
52#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
53#define UCR3_PARERREN (1<<12) /* Parity enable */
54#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
55#define UCR3_DSR (1<<10) /* Data set ready */
56#define UCR3_DCD (1<<9) /* Data carrier detect */
57#define UCR3_RI (1<<8) /* Ring indicator */
58#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
59#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
60#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
61#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
62#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
63#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
64#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
65#define UCR3_BPEN (1<<0) /* Preset registers enable */
66#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
67#define UCR4_INVR (1<<9) /* Inverted infrared reception */
68#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
69#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
70#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
71#define UCR4_IRSC (1<<5) /* IR special case */
72#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
73#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
74#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
75#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
76#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
77#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
78#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
79#define RFDIV 4 /* divide input clock by 2 */
80#define UFCR_DCEDTE (1<<6) /* DTE mode select */
81#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
82#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
83#define USR1_RTSS (1<<14) /* RTS pin status */
84#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
85#define USR1_RTSD (1<<12) /* RTS delta */
86#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
87#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
88#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
89#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
90#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
91#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
92#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
93#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
94#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
95#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
96#define USR2_IDLE (1<<12) /* Idle condition */
97#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
98#define USR2_WAKE (1<<7) /* Wake */
99#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
100#define USR2_TXDC (1<<3) /* Transmitter complete */
101#define USR2_BRCD (1<<2) /* Break condition */
102#define USR2_ORE (1<<1) /* Overrun error */
103#define USR2_RDR (1<<0) /* Recv data ready */
104#define UTS_FRCPERR (1<<13) /* Force parity error */
105#define UTS_LOOP (1<<12) /* Loop tx and rx */
106#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
107#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
108#define UTS_TXFULL (1<<4) /* TxFIFO full */
109#define UTS_RXFULL (1<<3) /* RxFIFO full */
110#define UTS_SOFTRS (1<<0) /* Software reset */
45d97511
JT
111#define TXTL 2 /* reset default */
112#define RXTL 1 /* reset default */
9b56f4f0 113
a99546ab
SA
114DECLARE_GLOBAL_DATA_PTR;
115
ffa8bcd7
JT
116struct mxc_uart {
117 u32 rxd;
118 u32 spare0[15];
119
120 u32 txd;
121 u32 spare1[15];
122
123 u32 cr1;
124 u32 cr2;
125 u32 cr3;
126 u32 cr4;
127
128 u32 fcr;
129 u32 sr1;
130 u32 sr2;
131 u32 esc;
132
133 u32 tim;
134 u32 bir;
135 u32 bmr;
136 u32 brc;
137
138 u32 onems;
139 u32 ts;
140};
141
97548d59
JT
142static void _mxc_serial_init(struct mxc_uart *base)
143{
144 writel(0, &base->cr1);
145 writel(0, &base->cr2);
146
147 while (!(readl(&base->cr2) & UCR2_SRST));
148
149 writel(0x704 | UCR3_ADNIMP, &base->cr3);
150 writel(0x8000, &base->cr4);
151 writel(0x2b, &base->esc);
152 writel(0, &base->tim);
153
154 writel(0, &base->ts);
155}
156
45d97511
JT
157static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
158 unsigned long baudrate, bool use_dte)
159{
160 u32 tmp;
161
162 tmp = RFDIV << UFCR_RFDIV_SHF;
163 if (use_dte)
164 tmp |= UFCR_DCEDTE;
165 else
166 tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
167 writel(tmp, &base->fcr);
168
169 writel(0xf, &base->bir);
170 writel(clk / (2 * baudrate), &base->bmr);
171
172 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
173 &base->cr2);
174 writel(UCR1_UARTEN, &base->cr1);
175}
176
a8ba569c
SG
177#ifndef CONFIG_DM_SERIAL
178
179#ifndef CONFIG_MXC_UART_BASE
180#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
181#endif
182
ffa8bcd7 183#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
a8ba569c 184
a943472c 185static void mxc_serial_setbrg(void)
9b56f4f0 186{
71d64c0e 187 u32 clk = imx_get_uartclk();
9b56f4f0
SH
188
189 if (!gd->baudrate)
190 gd->baudrate = CONFIG_BAUDRATE;
191
45d97511 192 _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
9b56f4f0
SH
193}
194
a943472c 195static int mxc_serial_getc(void)
9b56f4f0 196{
ffa8bcd7 197 while (readl(&mxc_base->ts) & UTS_RXEMPTY)
4ec3d2a7 198 WATCHDOG_RESET();
ffa8bcd7 199 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
9b56f4f0
SH
200}
201
a943472c 202static void mxc_serial_putc(const char c)
9b56f4f0 203{
055457ef
AW
204 /* If \n, also do \r */
205 if (c == '\n')
206 serial_putc('\r');
207
ffa8bcd7 208 writel(c, &mxc_base->txd);
9b56f4f0
SH
209
210 /* wait for transmitter to be ready */
ffa8bcd7 211 while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
4ec3d2a7 212 WATCHDOG_RESET();
9b56f4f0
SH
213}
214
52c14cab 215/* Test whether a character is in the RX buffer */
a943472c 216static int mxc_serial_tstc(void)
9b56f4f0
SH
217{
218 /* If receive fifo is empty, return false */
ffa8bcd7 219 if (readl(&mxc_base->ts) & UTS_RXEMPTY)
9b56f4f0
SH
220 return 0;
221 return 1;
222}
223
9b56f4f0
SH
224/*
225 * Initialise the serial port with the given baudrate. The settings
226 * are always 8 data bits, no parity, 1 stop bit, no start bits.
9b56f4f0 227 */
a943472c 228static int mxc_serial_init(void)
9b56f4f0 229{
97548d59 230 _mxc_serial_init(mxc_base);
9b56f4f0
SH
231
232 serial_setbrg();
233
9b56f4f0
SH
234 return 0;
235}
a943472c 236
a943472c
MV
237static struct serial_device mxc_serial_drv = {
238 .name = "mxc_serial",
239 .start = mxc_serial_init,
240 .stop = NULL,
241 .setbrg = mxc_serial_setbrg,
242 .putc = mxc_serial_putc,
ec3fd689 243 .puts = default_serial_puts,
a943472c
MV
244 .getc = mxc_serial_getc,
245 .tstc = mxc_serial_tstc,
246};
247
248void mxc_serial_initialize(void)
249{
250 serial_register(&mxc_serial_drv);
251}
252
253__weak struct serial_device *default_serial_console(void)
254{
255 return &mxc_serial_drv;
256}
a8ba569c
SG
257#endif
258
259#ifdef CONFIG_DM_SERIAL
260
a8ba569c
SG
261int mxc_serial_setbrg(struct udevice *dev, int baudrate)
262{
263 struct mxc_serial_platdata *plat = dev->platdata;
a8ba569c 264 u32 clk = imx_get_uartclk();
83fd908f 265
45d97511 266 _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
a8ba569c
SG
267
268 return 0;
269}
270
271static int mxc_serial_probe(struct udevice *dev)
272{
273 struct mxc_serial_platdata *plat = dev->platdata;
a8ba569c 274
97548d59 275 _mxc_serial_init(plat->reg);
a8ba569c
SG
276
277 return 0;
278}
279
280static int mxc_serial_getc(struct udevice *dev)
281{
282 struct mxc_serial_platdata *plat = dev->platdata;
283 struct mxc_uart *const uart = plat->reg;
284
285 if (readl(&uart->ts) & UTS_RXEMPTY)
286 return -EAGAIN;
287
288 return readl(&uart->rxd) & URXD_RX_DATA;
289}
290
291static int mxc_serial_putc(struct udevice *dev, const char ch)
292{
293 struct mxc_serial_platdata *plat = dev->platdata;
294 struct mxc_uart *const uart = plat->reg;
295
296 if (!(readl(&uart->ts) & UTS_TXEMPTY))
297 return -EAGAIN;
298
299 writel(ch, &uart->txd);
300
301 return 0;
302}
303
304static int mxc_serial_pending(struct udevice *dev, bool input)
305{
306 struct mxc_serial_platdata *plat = dev->platdata;
307 struct mxc_uart *const uart = plat->reg;
308 uint32_t sr2 = readl(&uart->sr2);
309
310 if (input)
311 return sr2 & USR2_RDR ? 1 : 0;
312 else
313 return sr2 & USR2_TXDC ? 0 : 1;
314}
315
316static const struct dm_serial_ops mxc_serial_ops = {
317 .putc = mxc_serial_putc,
318 .pending = mxc_serial_pending,
319 .getc = mxc_serial_getc,
320 .setbrg = mxc_serial_setbrg,
321};
322
a99546ab
SA
323#if CONFIG_IS_ENABLED(OF_CONTROL)
324static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
325{
326 struct mxc_serial_platdata *plat = dev->platdata;
327 fdt_addr_t addr;
328
a821c4af 329 addr = devfdt_get_addr(dev);
a99546ab
SA
330 if (addr == FDT_ADDR_T_NONE)
331 return -EINVAL;
332
333 plat->reg = (struct mxc_uart *)addr;
334
e160f7d4 335 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
a99546ab
SA
336 "fsl,dte-mode");
337 return 0;
338}
339
340static const struct udevice_id mxc_serial_ids[] = {
3a5d6363 341 { .compatible = "fsl,imx6ul-uart" },
a99546ab
SA
342 { .compatible = "fsl,imx7d-uart" },
343 { }
344};
345#endif
346
a8ba569c
SG
347U_BOOT_DRIVER(serial_mxc) = {
348 .name = "serial_mxc",
349 .id = UCLASS_SERIAL,
a99546ab
SA
350#if CONFIG_IS_ENABLED(OF_CONTROL)
351 .of_match = mxc_serial_ids,
352 .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
353 .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
354#endif
a8ba569c
SG
355 .probe = mxc_serial_probe,
356 .ops = &mxc_serial_ops,
357 .flags = DM_FLAG_PRE_RELOC,
358};
359#endif
61366b71
JT
360
361#ifdef CONFIG_DEBUG_UART_MXC
362#include <debug_uart.h>
363
364static inline void _debug_uart_init(void)
365{
366 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
367
368 _mxc_serial_init(base);
369 _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
370 CONFIG_BAUDRATE, false);
371}
372
373static inline void _debug_uart_putc(int ch)
374{
375 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
376
377 while (!(readl(&base->ts) & UTS_TXEMPTY))
378 WATCHDOG_RESET();
379
380 writel(ch, &base->txd);
381}
382
383DEBUG_UART_FUNCS
384
385#endif