[people/ms/u-boot.git] / drivers / serial / serial_mxc.c

/*
 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <dm/platform_data/serial_mxc.h>
#include <serial.h>
#include <linux/compiler.h>

/* UART Control Register Bit Fields.*/
#define  URXD_CHARRDY    (1<<15)
#define  URXD_ERR        (1<<14)
#define  URXD_OVRRUN     (1<<13)
#define  URXD_FRMERR     (1<<12)
#define  URXD_BRK        (1<<11)
#define  URXD_PRERR      (1<<10)
#define  URXD_RX_DATA    (0xFF)
#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
#define  UCR1_DOZE       (1<<1)	 /* Doze */
#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
#define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
#define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
#define  UCR2_CTSC	 (1<<13) /* CTS pin control */
#define  UCR2_CTS        (1<<12) /* Clear to send */
#define  UCR2_ESCEN      (1<<11) /* Escape enable */
#define  UCR2_PREN       (1<<8)  /* Parity enable */
#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
#define  UCR2_STPB       (1<<6)	 /* Stop */
#define  UCR2_WS         (1<<5)	 /* Word size */
#define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
#define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
#define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
#define  UCR2_SRST	 (1<<0)	 /* SW reset */
#define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
#define  UCR3_PARERREN   (1<<12) /* Parity enable */
#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
#define  UCR3_DSR        (1<<10) /* Data set ready */
#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
#define  UCR3_RI         (1<<8)  /* Ring indicator */
#define  UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
#define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
#define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
#define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
#define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
#define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
#define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
#define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
#define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
#define  UCR4_IRSC	 (1<<5)  /* IR special case */
#define  UCR4_TCEN	 (1<<3)  /* Transmit complete interrupt enable */
#define  UCR4_BKEN	 (1<<2)  /* Break condition interrupt enable */
#define  UCR4_OREN	 (1<<1)  /* Receiver overrun interrupt enable */
#define  UCR4_DREN	 (1<<0)  /* Recv data ready interrupt enable */
#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
#define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
#define RFDIV		4 /* divide input clock by 2 */
#define  UFCR_DCEDTE	 (1<<6)  /* DTE mode select */
#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
#define  USR1_RTSS	 (1<<14) /* RTS pin status */
#define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
#define  USR1_RTSD	 (1<<12) /* RTS delta */
#define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
#define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
#define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
#define  USR1_RXDS	 (1<<6)	 /* Receiver idle interrupt flag */
#define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
#define  USR1_AWAKE	 (1<<4)	 /* Aysnc wake interrupt flag */
#define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
#define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
#define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
#define  USR2_IDLE	 (1<<12) /* Idle condition */
#define  USR2_IRINT	 (1<<8)	 /* Serial infrared interrupt flag */
#define  USR2_WAKE	 (1<<7)	 /* Wake */
#define  USR2_RTSF	 (1<<4)	 /* RTS edge interrupt flag */
#define  USR2_TXDC	 (1<<3)	 /* Transmitter complete */
#define  USR2_BRCD	 (1<<2)	 /* Break condition */
#define  USR2_ORE        (1<<1)	 /* Overrun error */
#define  USR2_RDR        (1<<0)	 /* Recv data ready */
#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
#define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
#define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
#define  UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
#define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
#define  UTS_SOFTRS	(1<<0)	 /* Software reset */

DECLARE_GLOBAL_DATA_PTR;

struct mxc_uart {
	u32 rxd;
	u32 spare0[15];

	u32 txd;
	u32 spare1[15];

	u32 cr1;
	u32 cr2;
	u32 cr3;
	u32 cr4;

	u32 fcr;
	u32 sr1;
	u32 sr2;
	u32 esc;

	u32 tim;
	u32 bir;
	u32 bmr;
	u32 brc;

	u32 onems;
	u32 ts;
};

static void _mxc_serial_init(struct mxc_uart *base)
{
	writel(0, &base->cr1);
	writel(0, &base->cr2);

	while (!(readl(&base->cr2) & UCR2_SRST));

	writel(0x704 | UCR3_ADNIMP, &base->cr3);
	writel(0x8000, &base->cr4);
	writel(0x2b, &base->esc);
	writel(0, &base->tim);

	writel(0, &base->ts);
}

#ifndef CONFIG_DM_SERIAL

#ifndef CONFIG_MXC_UART_BASE
#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
#endif

#define mxc_base	((struct mxc_uart *)CONFIG_MXC_UART_BASE)

#define TXTL  2 /* reset default */
#define RXTL  1 /* reset default */

static void mxc_serial_setbrg(void)
{
	u32 clk = imx_get_uartclk();

	if (!gd->baudrate)
		gd->baudrate = CONFIG_BAUDRATE;

	writel(((RFDIV << UFCR_RFDIV_SHF) |
		(TXTL << UFCR_TXTL_SHF) |
		(RXTL << UFCR_RXTL_SHF)),
		&mxc_base->fcr);
	writel(0xf, &mxc_base->bir);
	writel(clk / (2 * gd->baudrate), &mxc_base->bmr);

	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
	       &mxc_base->cr2);
	writel(UCR1_UARTEN, &mxc_base->cr1);
}

static int mxc_serial_getc(void)
{
	while (readl(&mxc_base->ts) & UTS_RXEMPTY)
		WATCHDOG_RESET();
	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
}

static void mxc_serial_putc(const char c)
{
	/* If \n, also do \r */
	if (c == '\n')
		serial_putc('\r');

	writel(c, &mxc_base->txd);

	/* wait for transmitter to be ready */
	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
		WATCHDOG_RESET();
}

/*
 * Test whether a character is in the RX buffer
 */
static int mxc_serial_tstc(void)
{
	/* If receive fifo is empty, return false */
	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
		return 0;
	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 *
 */
static int mxc_serial_init(void)
{
	_mxc_serial_init(mxc_base);

	serial_setbrg();

	return 0;
}

static struct serial_device mxc_serial_drv = {
	.name	= "mxc_serial",
	.start	= mxc_serial_init,
	.stop	= NULL,
	.setbrg	= mxc_serial_setbrg,
	.putc	= mxc_serial_putc,
	.puts	= default_serial_puts,
	.getc	= mxc_serial_getc,
	.tstc	= mxc_serial_tstc,
};

void mxc_serial_initialize(void)
{
	serial_register(&mxc_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &mxc_serial_drv;
}
#endif

#ifdef CONFIG_DM_SERIAL

int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct mxc_serial_platdata *plat = dev->platdata;
	struct mxc_uart *const uart = plat->reg;
	u32 clk = imx_get_uartclk();
	u32 tmp;

	tmp = RFDIV << UFCR_RFDIV_SHF;
	if (plat->use_dte)
		tmp |= UFCR_DCEDTE;
	writel(tmp, &uart->fcr);

	writel(0xf, &uart->bir);
	writel(clk / (2 * baudrate), &uart->bmr);

	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
	       &uart->cr2);
	writel(UCR1_UARTEN, &uart->cr1);

	return 0;
}

static int mxc_serial_probe(struct udevice *dev)
{
	struct mxc_serial_platdata *plat = dev->platdata;

	_mxc_serial_init(plat->reg);

	return 0;
}

static int mxc_serial_getc(struct udevice *dev)
{
	struct mxc_serial_platdata *plat = dev->platdata;
	struct mxc_uart *const uart = plat->reg;

	if (readl(&uart->ts) & UTS_RXEMPTY)
		return -EAGAIN;

	return readl(&uart->rxd) & URXD_RX_DATA;
}

static int mxc_serial_putc(struct udevice *dev, const char ch)
{
	struct mxc_serial_platdata *plat = dev->platdata;
	struct mxc_uart *const uart = plat->reg;

	if (!(readl(&uart->ts) & UTS_TXEMPTY))
		return -EAGAIN;

	writel(ch, &uart->txd);

	return 0;
}

static int mxc_serial_pending(struct udevice *dev, bool input)
{
	struct mxc_serial_platdata *plat = dev->platdata;
	struct mxc_uart *const uart = plat->reg;
	uint32_t sr2 = readl(&uart->sr2);

	if (input)
		return sr2 & USR2_RDR ? 1 : 0;
	else
		return sr2 & USR2_TXDC ? 0 : 1;
}

static const struct dm_serial_ops mxc_serial_ops = {
	.putc = mxc_serial_putc,
	.pending = mxc_serial_pending,
	.getc = mxc_serial_getc,
	.setbrg = mxc_serial_setbrg,
};

#if CONFIG_IS_ENABLED(OF_CONTROL)
static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
{
	struct mxc_serial_platdata *plat = dev->platdata;
	fdt_addr_t addr;

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->reg = (struct mxc_uart *)addr;

	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
					"fsl,dte-mode");
	return 0;
}

static const struct udevice_id mxc_serial_ids[] = {
	{ .compatible = "fsl,imx6ul-uart" },
	{ .compatible = "fsl,imx7d-uart" },
	{ }
};
#endif

U_BOOT_DRIVER(serial_mxc) = {
	.name	= "serial_mxc",
	.id	= UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
	.of_match = mxc_serial_ids,
	.ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
#endif
	.probe = mxc_serial_probe,
	.ops	= &mxc_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
#endif
Commit	Line	Data
9b56f4f0 SH	1	/*
	2	* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
9b56f4f0 SH	5	*/
	6
	7	#include <common.h>
a8ba569c SG	8	#include <dm.h>
a8ba569c SG	9	#include <errno.h>
4ec3d2a7	10	#include <watchdog.h>
47d19da4 IY	11	#include <asm/arch/imx-regs.h>
47d19da4 IY	12	#include <asm/arch/clock.h>
86256b79	13	#include <dm/platform_data/serial_mxc.h>
a943472c MV	14	#include <serial.h>
a943472c MV	15	#include <linux/compiler.h>
9b56f4f0	16
9b56f4f0 SH	17	/* UART Control Register Bit Fields.*/
	18	#define URXD_CHARRDY (1<<15)
	19	#define URXD_ERR (1<<14)
	20	#define URXD_OVRRUN (1<<13)
	21	#define URXD_FRMERR (1<<12)
	22	#define URXD_BRK (1<<11)
	23	#define URXD_PRERR (1<<10)
d92ea21b	24	#define URXD_RX_DATA (0xFF)
9b56f4f0 SH	25	#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
	26	#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
	27	#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
	28	#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
	29	#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
	30	#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
	31	#define UCR1_IREN (1<<7) /* Infrared interface enable */
	32	#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
	33	#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
	34	#define UCR1_SNDBRK (1<<4) /* Send break */
	35	#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
	36	#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
	37	#define UCR1_DOZE (1<<1) /* Doze */
	38	#define UCR1_UARTEN (1<<0) /* UART enabled */
53677ef1 WD	39	#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
	40	#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
	41	#define UCR2_CTSC (1<<13) /* CTS pin control */
9b56f4f0 SH	42	#define UCR2_CTS (1<<12) /* Clear to send */
	43	#define UCR2_ESCEN (1<<11) /* Escape enable */
	44	#define UCR2_PREN (1<<8) /* Parity enable */
	45	#define UCR2_PROE (1<<7) /* Parity odd/even */
	46	#define UCR2_STPB (1<<6) /* Stop */
	47	#define UCR2_WS (1<<5) /* Word size */
	48	#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
	49	#define UCR2_TXEN (1<<2) /* Transmitter enabled */
	50	#define UCR2_RXEN (1<<1) /* Receiver enabled */
53677ef1 WD	51	#define UCR2_SRST (1<<0) /* SW reset */
53677ef1 WD	52	#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
9b56f4f0 SH	53	#define UCR3_PARERREN (1<<12) /* Parity enable */
	54	#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
	55	#define UCR3_DSR (1<<10) /* Data set ready */
	56	#define UCR3_DCD (1<<9) /* Data carrier detect */
	57	#define UCR3_RI (1<<8) /* Ring indicator */
3a564825	58	#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
9b56f4f0 SH	59	#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
	60	#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
	61	#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
53677ef1 WD	62	#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
	63	#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
	64	#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
	65	#define UCR3_BPEN (1<<0) /* Preset registers enable */
9b56f4f0	66	#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
53677ef1 WD	67	#define UCR4_INVR (1<<9) /* Inverted infrared reception */
	68	#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
	69	#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
	70	#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
	71	#define UCR4_IRSC (1<<5) /* IR special case */
	72	#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
	73	#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
	74	#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
	75	#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
9b56f4f0 SH	76	#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
9b56f4f0 SH	77	#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
434afa80	78	#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
62af03ee	79	#define RFDIV 4 /* divide input clock by 2 */
83fd908f	80	#define UFCR_DCEDTE (1<<6) /* DTE mode select */
9b56f4f0 SH	81	#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
9b56f4f0 SH	82	#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
53677ef1 WD	83	#define USR1_RTSS (1<<14) /* RTS pin status */
	84	#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
	85	#define USR1_RTSD (1<<12) /* RTS delta */
	86	#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
9b56f4f0 SH	87	#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
	88	#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
	89	#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
53677ef1	90	#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
9b56f4f0	91	#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
53677ef1 WD	92	#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
	93	#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
	94	#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
	95	#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
	96	#define USR2_IDLE (1<<12) /* Idle condition */
	97	#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
	98	#define USR2_WAKE (1<<7) /* Wake */
	99	#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
	100	#define USR2_TXDC (1<<3) /* Transmitter complete */
	101	#define USR2_BRCD (1<<2) /* Break condition */
9b56f4f0 SH	102	#define USR2_ORE (1<<1) /* Overrun error */
	103	#define USR2_RDR (1<<0) /* Recv data ready */
	104	#define UTS_FRCPERR (1<<13) /* Force parity error */
	105	#define UTS_LOOP (1<<12) /* Loop tx and rx */
	106	#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
	107	#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
53677ef1 WD	108	#define UTS_TXFULL (1<<4) /* TxFIFO full */
53677ef1 WD	109	#define UTS_RXFULL (1<<3) /* RxFIFO full */
62af03ee	110	#define UTS_SOFTRS (1<<0) /* Software reset */
9b56f4f0	111
a99546ab SA	112	DECLARE_GLOBAL_DATA_PTR;
a99546ab SA	113
ffa8bcd7 JT	114	struct mxc_uart {
	115	u32 rxd;
	116	u32 spare0[15];
	117
	118	u32 txd;
	119	u32 spare1[15];
	120
	121	u32 cr1;
	122	u32 cr2;
	123	u32 cr3;
	124	u32 cr4;
	125
	126	u32 fcr;
	127	u32 sr1;
	128	u32 sr2;
	129	u32 esc;
	130
	131	u32 tim;
	132	u32 bir;
	133	u32 bmr;
	134	u32 brc;
	135
	136	u32 onems;
	137	u32 ts;
	138	};
	139
97548d59 JT	140	static void _mxc_serial_init(struct mxc_uart *base)
	141	{
	142	writel(0, &base->cr1);
	143	writel(0, &base->cr2);
	144
	145	while (!(readl(&base->cr2) & UCR2_SRST));
	146
	147	writel(0x704 \| UCR3_ADNIMP, &base->cr3);
	148	writel(0x8000, &base->cr4);
	149	writel(0x2b, &base->esc);
	150	writel(0, &base->tim);
	151
	152	writel(0, &base->ts);
	153	}
	154
a8ba569c SG	155	#ifndef CONFIG_DM_SERIAL
	156
	157	#ifndef CONFIG_MXC_UART_BASE
	158	#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
	159	#endif
	160
ffa8bcd7	161	#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
a8ba569c	162
434afa80 MS	163	#define TXTL 2 /* reset default */
434afa80 MS	164	#define RXTL 1 /* reset default */
434afa80	165
a943472c	166	static void mxc_serial_setbrg(void)
9b56f4f0	167	{
71d64c0e	168	u32 clk = imx_get_uartclk();
9b56f4f0 SH	169
	170	if (!gd->baudrate)
	171	gd->baudrate = CONFIG_BAUDRATE;
	172
ffa8bcd7 JT	173	writel(((RFDIV << UFCR_RFDIV_SHF) \|
	174	(TXTL << UFCR_TXTL_SHF) \|
	175	(RXTL << UFCR_RXTL_SHF)),
	176	&mxc_base->fcr);
	177	writel(0xf, &mxc_base->bir);
	178	writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
9b56f4f0	179
57d3e98f JT	180	writel(UCR2_WS \| UCR2_IRTS \| UCR2_RXEN \| UCR2_TXEN \| UCR2_SRST,
	181	&mxc_base->cr2);
	182	writel(UCR1_UARTEN, &mxc_base->cr1);
9b56f4f0 SH	183	}
9b56f4f0 SH	184
a943472c	185	static int mxc_serial_getc(void)
9b56f4f0	186	{
ffa8bcd7	187	while (readl(&mxc_base->ts) & UTS_RXEMPTY)
4ec3d2a7	188	WATCHDOG_RESET();
ffa8bcd7	189	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
9b56f4f0 SH	190	}
9b56f4f0 SH	191
a943472c	192	static void mxc_serial_putc(const char c)
9b56f4f0	193	{
055457ef AW	194	/* If \n, also do \r */
	195	if (c == '\n')
	196	serial_putc('\r');
	197
ffa8bcd7	198	writel(c, &mxc_base->txd);
9b56f4f0 SH	199
9b56f4f0 SH	200	/* wait for transmitter to be ready */
ffa8bcd7	201	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
4ec3d2a7	202	WATCHDOG_RESET();
9b56f4f0 SH	203	}
	204
	205	/*
	206	* Test whether a character is in the RX buffer
	207	*/
a943472c	208	static int mxc_serial_tstc(void)
9b56f4f0 SH	209	{
9b56f4f0 SH	210	/* If receive fifo is empty, return false */
ffa8bcd7	211	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
9b56f4f0 SH	212	return 0;
	213	return 1;
	214	}
	215
9b56f4f0 SH	216	/*
	217	* Initialise the serial port with the given baudrate. The settings
	218	* are always 8 data bits, no parity, 1 stop bit, no start bits.
	219	*
	220	*/
a943472c	221	static int mxc_serial_init(void)
9b56f4f0	222	{
97548d59	223	_mxc_serial_init(mxc_base);
9b56f4f0 SH	224
	225	serial_setbrg();
	226
9b56f4f0 SH	227	return 0;
9b56f4f0 SH	228	}
a943472c	229
a943472c MV	230	static struct serial_device mxc_serial_drv = {
	231	.name = "mxc_serial",
	232	.start = mxc_serial_init,
	233	.stop = NULL,
	234	.setbrg = mxc_serial_setbrg,
	235	.putc = mxc_serial_putc,
ec3fd689	236	.puts = default_serial_puts,
a943472c MV	237	.getc = mxc_serial_getc,
	238	.tstc = mxc_serial_tstc,
	239	};
	240
	241	void mxc_serial_initialize(void)
	242	{
	243	serial_register(&mxc_serial_drv);
	244	}
	245
	246	__weak struct serial_device *default_serial_console(void)
	247	{
	248	return &mxc_serial_drv;
	249	}
a8ba569c SG	250	#endif
	251
	252	#ifdef CONFIG_DM_SERIAL
	253
a8ba569c SG	254	int mxc_serial_setbrg(struct udevice *dev, int baudrate)
	255	{
	256	struct mxc_serial_platdata *plat = dev->platdata;
	257	struct mxc_uart *const uart = plat->reg;
	258	u32 clk = imx_get_uartclk();
83fd908f SA	259	u32 tmp;
83fd908f SA	260
62af03ee	261	tmp = RFDIV << UFCR_RFDIV_SHF;
83fd908f SA	262	if (plat->use_dte)
	263	tmp \|= UFCR_DCEDTE;
	264	writel(tmp, &uart->fcr);
a8ba569c	265
a8ba569c SG	266	writel(0xf, &uart->bir);
	267	writel(clk / (2 * baudrate), &uart->bmr);
	268
	269	writel(UCR2_WS \| UCR2_IRTS \| UCR2_RXEN \| UCR2_TXEN \| UCR2_SRST,
	270	&uart->cr2);
	271	writel(UCR1_UARTEN, &uart->cr1);
	272
	273	return 0;
	274	}
	275
	276	static int mxc_serial_probe(struct udevice *dev)
	277	{
	278	struct mxc_serial_platdata *plat = dev->platdata;
a8ba569c	279
97548d59	280	_mxc_serial_init(plat->reg);
a8ba569c SG	281
	282	return 0;
	283	}
	284
	285	static int mxc_serial_getc(struct udevice *dev)
	286	{
	287	struct mxc_serial_platdata *plat = dev->platdata;
	288	struct mxc_uart *const uart = plat->reg;
	289
	290	if (readl(&uart->ts) & UTS_RXEMPTY)
	291	return -EAGAIN;
	292
	293	return readl(&uart->rxd) & URXD_RX_DATA;
	294	}
	295
	296	static int mxc_serial_putc(struct udevice *dev, const char ch)
	297	{
	298	struct mxc_serial_platdata *plat = dev->platdata;
	299	struct mxc_uart *const uart = plat->reg;
	300
	301	if (!(readl(&uart->ts) & UTS_TXEMPTY))
	302	return -EAGAIN;
	303
	304	writel(ch, &uart->txd);
	305
	306	return 0;
	307	}
	308
	309	static int mxc_serial_pending(struct udevice *dev, bool input)
	310	{
	311	struct mxc_serial_platdata *plat = dev->platdata;
	312	struct mxc_uart *const uart = plat->reg;
	313	uint32_t sr2 = readl(&uart->sr2);
	314
	315	if (input)
	316	return sr2 & USR2_RDR ? 1 : 0;
	317	else
	318	return sr2 & USR2_TXDC ? 0 : 1;
	319	}
	320
	321	static const struct dm_serial_ops mxc_serial_ops = {
	322	.putc = mxc_serial_putc,
	323	.pending = mxc_serial_pending,
	324	.getc = mxc_serial_getc,
	325	.setbrg = mxc_serial_setbrg,
	326	};
	327
a99546ab SA	328	#if CONFIG_IS_ENABLED(OF_CONTROL)
	329	static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
	330	{
	331	struct mxc_serial_platdata *plat = dev->platdata;
	332	fdt_addr_t addr;
	333
a821c4af	334	addr = devfdt_get_addr(dev);
a99546ab SA	335	if (addr == FDT_ADDR_T_NONE)
	336	return -EINVAL;
	337
	338	plat->reg = (struct mxc_uart *)addr;
	339
e160f7d4	340	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
a99546ab SA	341	"fsl,dte-mode");
	342	return 0;
	343	}
	344
	345	static const struct udevice_id mxc_serial_ids[] = {
3a5d6363	346	{ .compatible = "fsl,imx6ul-uart" },
a99546ab SA	347	{ .compatible = "fsl,imx7d-uart" },
	348	{ }
	349	};
	350	#endif
	351
a8ba569c SG	352	U_BOOT_DRIVER(serial_mxc) = {
	353	.name = "serial_mxc",
	354	.id = UCLASS_SERIAL,
a99546ab SA	355	#if CONFIG_IS_ENABLED(OF_CONTROL)
	356	.of_match = mxc_serial_ids,
	357	.ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
	358	.platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
	359	#endif
a8ba569c SG	360	.probe = mxc_serial_probe,
	361	.ops = &mxc_serial_ops,
	362	.flags = DM_FLAG_PRE_RELOC,
	363	};
	364	#endif