[people/ms/u-boot.git] / drivers / serial / serial_pl01x.c

/*
 * (C) Copyright 2000
 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
 *
 * (C) Copyright 2004
 * ARM Ltd.
 * Philippe Robin, <philippe.robin@arm.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
#include <asm/io.h>
#include <serial.h>
#include <dm/platform_data/serial_pl01x.h>
#include <linux/compiler.h>
#include "serial_pl01x_internal.h"
#include <fdtdec.h>

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_DM_SERIAL

static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))

#endif

static int pl01x_putc(struct pl01x_regs *regs, char c)
{
	/* Wait until there is space in the FIFO */
	if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
		return -EAGAIN;

	/* Send the character */
	writel(c, &regs->dr);

	return 0;
}

static int pl01x_getc(struct pl01x_regs *regs)
{
	unsigned int data;

	/* Wait until there is data in the FIFO */
	if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
		return -EAGAIN;

	data = readl(&regs->dr);

	/* Check for an error flag */
	if (data & 0xFFFFFF00) {
		/* Clear the error */
		writel(0xFFFFFFFF, &regs->ecr);
		return -1;
	}

	return (int) data;
}

static int pl01x_tstc(struct pl01x_regs *regs)
{
	WATCHDOG_RESET();
	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
}

static int pl01x_generic_serial_init(struct pl01x_regs *regs,
				     enum pl01x_type type)
{
	switch (type) {
	case TYPE_PL010:
		/* disable everything */
		writel(0, &regs->pl010_cr);
		break;
	case TYPE_PL011:
		/* disable everything */
		writel(0, &regs->pl011_cr);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int pl011_set_line_control(struct pl01x_regs *regs)
{
	unsigned int lcr;
	/*
	 * Internal update of baud rate register require line
	 * control register write
	 */
	lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
	writel(lcr, &regs->pl011_lcrh);
	return 0;
}

static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
				int clock, int baudrate)
{
	switch (type) {
	case TYPE_PL010: {
		unsigned int divisor;

		/* disable everything */
		writel(0, &regs->pl010_cr);

		switch (baudrate) {
		case 9600:
			divisor = UART_PL010_BAUD_9600;
			break;
		case 19200:
			divisor = UART_PL010_BAUD_9600;
			break;
		case 38400:
			divisor = UART_PL010_BAUD_38400;
			break;
		case 57600:
			divisor = UART_PL010_BAUD_57600;
			break;
		case 115200:
			divisor = UART_PL010_BAUD_115200;
			break;
		default:
			divisor = UART_PL010_BAUD_38400;
		}

		writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
		writel(divisor & 0xff, &regs->pl010_lcrl);

		/*
		 * Set line control for the PL010 to be 8 bits, 1 stop bit,
		 * no parity, fifo enabled
		 */
		writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
		       &regs->pl010_lcrh);
		/* Finally, enable the UART */
		writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
		break;
	}
	case TYPE_PL011: {
		unsigned int temp;
		unsigned int divider;
		unsigned int remainder;
		unsigned int fraction;

		/*
		* Set baud rate
		*
		* IBRD = UART_CLK / (16 * BAUD_RATE)
		* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
		*		/ (16 * BAUD_RATE))
		*/
		temp = 16 * baudrate;
		divider = clock / temp;
		remainder = clock % temp;
		temp = (8 * remainder) / baudrate;
		fraction = (temp >> 1) + (temp & 1);

		writel(divider, &regs->pl011_ibrd);
		writel(fraction, &regs->pl011_fbrd);

		pl011_set_line_control(regs);
		/* Finally, enable the UART */
		writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
		       UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
		break;
	}
	default:
		return -EINVAL;
	}

	return 0;
}

#ifndef CONFIG_DM_SERIAL
static void pl01x_serial_init_baud(int baudrate)
{
	int clock = 0;

#if defined(CONFIG_PL010_SERIAL)
	pl01x_type = TYPE_PL010;
#elif defined(CONFIG_PL011_SERIAL)
	pl01x_type = TYPE_PL011;
	clock = CONFIG_PL011_CLOCK;
#endif
	base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];

	pl01x_generic_serial_init(base_regs, pl01x_type);
	pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
}

/*
 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 * Versatile PB has four UARTs.
 */
int pl01x_serial_init(void)
{
	pl01x_serial_init_baud(CONFIG_BAUDRATE);

	return 0;
}

static void pl01x_serial_putc(const char c)
{
	if (c == '\n')
		while (pl01x_putc(base_regs, '\r') == -EAGAIN);

	while (pl01x_putc(base_regs, c) == -EAGAIN);
}

static int pl01x_serial_getc(void)
{
	while (1) {
		int ch = pl01x_getc(base_regs);

		if (ch == -EAGAIN) {
			WATCHDOG_RESET();
			continue;
		}

		return ch;
	}
}

static int pl01x_serial_tstc(void)
{
	return pl01x_tstc(base_regs);
}

static void pl01x_serial_setbrg(void)
{
	/*
	 * Flush FIFO and wait for non-busy before changing baudrate to avoid
	 * crap in console
	 */
	while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
		WATCHDOG_RESET();
	while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
		WATCHDOG_RESET();
	pl01x_serial_init_baud(gd->baudrate);
}

static struct serial_device pl01x_serial_drv = {
	.name	= "pl01x_serial",
	.start	= pl01x_serial_init,
	.stop	= NULL,
	.setbrg	= pl01x_serial_setbrg,
	.putc	= pl01x_serial_putc,
	.puts	= default_serial_puts,
	.getc	= pl01x_serial_getc,
	.tstc	= pl01x_serial_tstc,
};

void pl01x_serial_initialize(void)
{
	serial_register(&pl01x_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &pl01x_serial_drv;
}

#endif /* nCONFIG_DM_SERIAL */

#ifdef CONFIG_DM_SERIAL

struct pl01x_priv {
	struct pl01x_regs *regs;
	enum pl01x_type type;
};

static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	struct pl01x_priv *priv = dev_get_priv(dev);

	if (!plat->skip_init) {
		pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
				     baudrate);
	}

	return 0;
}

static int pl01x_serial_probe(struct udevice *dev)
{
	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	struct pl01x_priv *priv = dev_get_priv(dev);

	priv->regs = (struct pl01x_regs *)plat->base;
	priv->type = plat->type;
	if (!plat->skip_init)
		return pl01x_generic_serial_init(priv->regs, priv->type);
	else
		return 0;
}

static int pl01x_serial_getc(struct udevice *dev)
{
	struct pl01x_priv *priv = dev_get_priv(dev);

	return pl01x_getc(priv->regs);
}

static int pl01x_serial_putc(struct udevice *dev, const char ch)
{
	struct pl01x_priv *priv = dev_get_priv(dev);

	return pl01x_putc(priv->regs, ch);
}

static int pl01x_serial_pending(struct udevice *dev, bool input)
{
	struct pl01x_priv *priv = dev_get_priv(dev);
	unsigned int fr = readl(&priv->regs->fr);

	if (input)
		return pl01x_tstc(priv->regs);
	else
		return fr & UART_PL01x_FR_TXFF ? 0 : 1;
}

static const struct dm_serial_ops pl01x_serial_ops = {
	.putc = pl01x_serial_putc,
	.pending = pl01x_serial_pending,
	.getc = pl01x_serial_getc,
	.setbrg = pl01x_serial_setbrg,
};

#if CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id pl01x_serial_id[] ={
	{.compatible = "arm,pl011", .data = TYPE_PL011},
	{.compatible = "arm,pl010", .data = TYPE_PL010},
	{}
};

static int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
{
	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	fdt_addr_t addr;

	addr = dev_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->base = addr;
	plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
				     1);
	plat->type = dev_get_driver_data(dev);
	plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
	                                  "skip-init");
	return 0;
}
#endif

U_BOOT_DRIVER(serial_pl01x) = {
	.name	= "serial_pl01x",
	.id	= UCLASS_SERIAL,
	.of_match = of_match_ptr(pl01x_serial_id),
	.ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
	.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
	.probe = pl01x_serial_probe,
	.ops	= &pl01x_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
	.priv_auto_alloc_size = sizeof(struct pl01x_priv),
};

#endif

#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)

#include <debug_uart.h>

static void _debug_uart_init(void)
{
#ifndef CONFIG_DEBUG_UART_SKIP_INIT
	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
	enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
				TYPE_PL011 : TYPE_PL010;

	pl01x_generic_serial_init(regs, type);
	pl01x_generic_setbrg(regs, type,
			     CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
#endif
}

static inline void _debug_uart_putc(int ch)
{
	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;

	pl01x_putc(regs, ch);
}

DEBUG_UART_FUNCS

#endif
Commit	Line	Data
3d3befa7 WD	1	/*
	2	* (C) Copyright 2000
	3	* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
	4	*
	5	* (C) Copyright 2004
	6	* ARM Ltd.
	7	* Philippe Robin, <philippe.robin@arm.com>
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
3d3befa7 WD	10	*/
3d3befa7 WD	11
48d0192f	12	/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
3d3befa7 WD	13
3d3befa7 WD	14	#include <common.h>
8a9cd5ad	15	#include <dm.h>
aed2fbef	16	#include <errno.h>
8b616edb	17	#include <watchdog.h>
249d5219	18	#include <asm/io.h>
39f61477	19	#include <serial.h>
86256b79	20	#include <dm/platform_data/serial_pl01x.h>
39f61477	21	#include <linux/compiler.h>
aed2fbef	22	#include "serial_pl01x_internal.h"
69751729 VM	23	#include <fdtdec.h>
	24
	25	DECLARE_GLOBAL_DATA_PTR;
3d3befa7	26
8a9cd5ad SG	27	#ifndef CONFIG_DM_SERIAL
8a9cd5ad SG	28
6705d81e	29	static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
aed2fbef SG	30	static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
aed2fbef SG	31	static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
6705d81e	32	#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
3d3befa7	33
8a9cd5ad	34	#endif
3d3befa7	35
aed2fbef	36	static int pl01x_putc(struct pl01x_regs *regs, char c)
72d5e44c	37	{
aed2fbef SG	38	/* Wait until there is space in the FIFO */
	39	if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
	40	return -EAGAIN;
42dfe7a1	41
aed2fbef SG	42	/* Send the character */
aed2fbef SG	43	writel(c, &regs->dr);
42dfe7a1	44
aed2fbef SG	45	return 0;
aed2fbef SG	46	}
42dfe7a1	47
aed2fbef SG	48	static int pl01x_getc(struct pl01x_regs *regs)
	49	{
	50	unsigned int data;
42dfe7a1	51
aed2fbef SG	52	/* Wait until there is data in the FIFO */
	53	if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
	54	return -EAGAIN;
42dfe7a1	55
aed2fbef	56	data = readl(&regs->dr);
42dfe7a1	57
aed2fbef SG	58	/* Check for an error flag */
	59	if (data & 0xFFFFFF00) {
	60	/* Clear the error */
	61	writel(0xFFFFFFFF, &regs->ecr);
	62	return -1;
42dfe7a1 WD	63	}
42dfe7a1 WD	64
aed2fbef	65	return (int) data;
3d3befa7 WD	66	}
3d3befa7 WD	67
aed2fbef SG	68	static int pl01x_tstc(struct pl01x_regs *regs)
	69	{
	70	WATCHDOG_RESET();
	71	return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
	72	}
20c9226c	73
aed2fbef SG	74	static int pl01x_generic_serial_init(struct pl01x_regs *regs,
aed2fbef SG	75	enum pl01x_type type)
20c9226c	76	{
eb8a4fe0 VM	77	switch (type) {
	78	case TYPE_PL010:
	79	/* disable everything */
	80	writel(0, &regs->pl010_cr);
	81	break;
	82	case TYPE_PL011:
f7e517b4 VM	83	/* disable everything */
f7e517b4 VM	84	writel(0, &regs->pl011_cr);
d2ca9fd2 VM	85	break;
	86	default:
	87	return -EINVAL;
	88	}
	89
	90	return 0;
	91	}
	92
d77447fd	93	static int pl011_set_line_control(struct pl01x_regs *regs)
d2ca9fd2 VM	94	{
	95	unsigned int lcr;
	96	/*
	97	* Internal update of baud rate register require line
	98	* control register write
	99	*/
	100	lcr = UART_PL011_LCRH_WLEN_8 \| UART_PL011_LCRH_FEN;
d2ca9fd2	101	writel(lcr, &regs->pl011_lcrh);
20c9226c AE	102	return 0;
	103	}
	104
aed2fbef SG	105	static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
aed2fbef SG	106	int clock, int baudrate)
3d3befa7	107	{
aed2fbef SG	108	switch (type) {
	109	case TYPE_PL010: {
	110	unsigned int divisor;
	111
d77447fd LW	112	/* disable everything */
	113	writel(0, &regs->pl010_cr);
	114
aed2fbef SG	115	switch (baudrate) {
	116	case 9600:
	117	divisor = UART_PL010_BAUD_9600;
	118	break;
	119	case 19200:
	120	divisor = UART_PL010_BAUD_9600;
	121	break;
	122	case 38400:
	123	divisor = UART_PL010_BAUD_38400;
	124	break;
	125	case 57600:
	126	divisor = UART_PL010_BAUD_57600;
	127	break;
	128	case 115200:
	129	divisor = UART_PL010_BAUD_115200;
	130	break;
	131	default:
	132	divisor = UART_PL010_BAUD_38400;
	133	}
	134
	135	writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
	136	writel(divisor & 0xff, &regs->pl010_lcrl);
	137
d77447fd LW	138	/*
	139	* Set line control for the PL010 to be 8 bits, 1 stop bit,
	140	* no parity, fifo enabled
	141	*/
	142	writel(UART_PL010_LCRH_WLEN_8 \| UART_PL010_LCRH_FEN,
	143	&regs->pl010_lcrh);
aed2fbef SG	144	/* Finally, enable the UART */
	145	writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
	146	break;
	147	}
	148	case TYPE_PL011: {
	149	unsigned int temp;
	150	unsigned int divider;
	151	unsigned int remainder;
	152	unsigned int fraction;
3d3befa7	153
aed2fbef SG	154	/*
	155	* Set baud rate
	156	*
	157	* IBRD = UART_CLK / (16 * BAUD_RATE)
	158	* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
	159	* / (16 * BAUD_RATE))
	160	*/
	161	temp = 16 * baudrate;
	162	divider = clock / temp;
	163	remainder = clock % temp;
	164	temp = (8 * remainder) / baudrate;
	165	fraction = (temp >> 1) + (temp & 1);
	166
	167	writel(divider, &regs->pl011_ibrd);
	168	writel(fraction, &regs->pl011_fbrd);
	169
d77447fd	170	pl011_set_line_control(regs);
aed2fbef SG	171	/* Finally, enable the UART */
	172	writel(UART_PL011_CR_UARTEN \| UART_PL011_CR_TXE \|
	173	UART_PL011_CR_RXE \| UART_PL011_CR_RTS, &regs->pl011_cr);
	174	break;
	175	}
	176	default:
	177	return -EINVAL;
	178	}
3d3befa7	179
aed2fbef	180	return 0;
3d3befa7 WD	181	}
3d3befa7 WD	182
aed2fbef SG	183	#ifndef CONFIG_DM_SERIAL
aed2fbef SG	184	static void pl01x_serial_init_baud(int baudrate)
3d3befa7	185	{
aed2fbef SG	186	int clock = 0;
	187
	188	#if defined(CONFIG_PL010_SERIAL)
	189	pl01x_type = TYPE_PL010;
	190	#elif defined(CONFIG_PL011_SERIAL)
	191	pl01x_type = TYPE_PL011;
	192	clock = CONFIG_PL011_CLOCK;
	193	#endif
	194	base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
	195
	196	pl01x_generic_serial_init(base_regs, pl01x_type);
a7deea69	197	pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
3d3befa7 WD	198	}
3d3befa7 WD	199
aed2fbef SG	200	/*
	201	* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
	202	* Integrator CP has two UARTs, use the first one, at 38400-8-N-1
	203	* Versatile PB has four UARTs.
	204	*/
	205	int pl01x_serial_init(void)
3d3befa7	206	{
aed2fbef	207	pl01x_serial_init_baud(CONFIG_BAUDRATE);
96baa4c3	208
aed2fbef	209	return 0;
3d3befa7 WD	210	}
3d3befa7 WD	211
aed2fbef	212	static void pl01x_serial_putc(const char c)
3d3befa7	213	{
aed2fbef SG	214	if (c == '\n')
aed2fbef SG	215	while (pl01x_putc(base_regs, '\r') == -EAGAIN);
42dfe7a1	216
aed2fbef	217	while (pl01x_putc(base_regs, c) == -EAGAIN);
3d3befa7 WD	218	}
3d3befa7 WD	219
aed2fbef	220	static int pl01x_serial_getc(void)
3d3befa7	221	{
aed2fbef SG	222	while (1) {
aed2fbef SG	223	int ch = pl01x_getc(base_regs);
42dfe7a1	224
aed2fbef SG	225	if (ch == -EAGAIN) {
	226	WATCHDOG_RESET();
	227	continue;
	228	}
42dfe7a1	229
aed2fbef	230	return ch;
42dfe7a1	231	}
3d3befa7 WD	232	}
3d3befa7 WD	233
aed2fbef	234	static int pl01x_serial_tstc(void)
3d3befa7	235	{
aed2fbef SG	236	return pl01x_tstc(base_regs);
aed2fbef SG	237	}
72d5e44c	238
aed2fbef SG	239	static void pl01x_serial_setbrg(void)
	240	{
	241	/*
	242	* Flush FIFO and wait for non-busy before changing baudrate to avoid
	243	* crap in console
	244	*/
	245	while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
	246	WATCHDOG_RESET();
	247	while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
	248	WATCHDOG_RESET();
	249	pl01x_serial_init_baud(gd->baudrate);
3d3befa7	250	}
39f61477	251
39f61477 MV	252	static struct serial_device pl01x_serial_drv = {
	253	.name = "pl01x_serial",
	254	.start = pl01x_serial_init,
	255	.stop = NULL,
	256	.setbrg = pl01x_serial_setbrg,
	257	.putc = pl01x_serial_putc,
ec3fd689	258	.puts = default_serial_puts,
39f61477 MV	259	.getc = pl01x_serial_getc,
	260	.tstc = pl01x_serial_tstc,
	261	};
	262
	263	void pl01x_serial_initialize(void)
	264	{
	265	serial_register(&pl01x_serial_drv);
	266	}
	267
	268	__weak struct serial_device *default_serial_console(void)
	269	{
	270	return &pl01x_serial_drv;
	271	}
aed2fbef SG	272
aed2fbef SG	273	#endif /* nCONFIG_DM_SERIAL */
8a9cd5ad SG	274
	275	#ifdef CONFIG_DM_SERIAL
	276
	277	struct pl01x_priv {
	278	struct pl01x_regs *regs;
	279	enum pl01x_type type;
	280	};
	281
	282	static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
	283	{
	284	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	285	struct pl01x_priv *priv = dev_get_priv(dev);
	286
cd0fa5bf EA	287	if (!plat->skip_init) {
	288	pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
	289	baudrate);
	290	}
8a9cd5ad SG	291
	292	return 0;
	293	}
	294
	295	static int pl01x_serial_probe(struct udevice *dev)
	296	{
	297	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	298	struct pl01x_priv *priv = dev_get_priv(dev);
	299
	300	priv->regs = (struct pl01x_regs *)plat->base;
	301	priv->type = plat->type;
cd0fa5bf EA	302	if (!plat->skip_init)
	303	return pl01x_generic_serial_init(priv->regs, priv->type);
	304	else
	305	return 0;
8a9cd5ad SG	306	}
	307
	308	static int pl01x_serial_getc(struct udevice *dev)
	309	{
	310	struct pl01x_priv *priv = dev_get_priv(dev);
	311
	312	return pl01x_getc(priv->regs);
	313	}
	314
	315	static int pl01x_serial_putc(struct udevice *dev, const char ch)
	316	{
	317	struct pl01x_priv *priv = dev_get_priv(dev);
	318
	319	return pl01x_putc(priv->regs, ch);
	320	}
	321
	322	static int pl01x_serial_pending(struct udevice *dev, bool input)
	323	{
	324	struct pl01x_priv *priv = dev_get_priv(dev);
	325	unsigned int fr = readl(&priv->regs->fr);
	326
	327	if (input)
	328	return pl01x_tstc(priv->regs);
	329	else
	330	return fr & UART_PL01x_FR_TXFF ? 0 : 1;
	331	}
	332
	333	static const struct dm_serial_ops pl01x_serial_ops = {
	334	.putc = pl01x_serial_putc,
	335	.pending = pl01x_serial_pending,
	336	.getc = pl01x_serial_getc,
	337	.setbrg = pl01x_serial_setbrg,
	338	};
	339
0f925822	340	#if CONFIG_IS_ENABLED(OF_CONTROL)
69751729 VM	341	static const struct udevice_id pl01x_serial_id[] ={
	342	{.compatible = "arm,pl011", .data = TYPE_PL011},
	343	{.compatible = "arm,pl010", .data = TYPE_PL010},
	344	{}
	345	};
	346
	347	static int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
	348	{
	349	struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
	350	fdt_addr_t addr;
	351
4e9838c1	352	addr = dev_get_addr(dev);
69751729 VM	353	if (addr == FDT_ADDR_T_NONE)
	354	return -EINVAL;
	355
	356	plat->base = addr;
e160f7d4 SG	357	plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
e160f7d4 SG	358	1);
69751729	359	plat->type = dev_get_driver_data(dev);
e160f7d4	360	plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
165316e3	361	"skip-init");
69751729 VM	362	return 0;
	363	}
	364	#endif
	365
8a9cd5ad SG	366	U_BOOT_DRIVER(serial_pl01x) = {
	367	.name = "serial_pl01x",
	368	.id = UCLASS_SERIAL,
69751729 VM	369	.of_match = of_match_ptr(pl01x_serial_id),
	370	.ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
	371	.platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
8a9cd5ad SG	372	.probe = pl01x_serial_probe,
	373	.ops = &pl01x_serial_ops,
	374	.flags = DM_FLAG_PRE_RELOC,
59c73d75	375	.priv_auto_alloc_size = sizeof(struct pl01x_priv),
8a9cd5ad SG	376	};
	377
	378	#endif
b81406db ST	379
	380	#if defined(CONFIG_DEBUG_UART_PL010) \|\| defined(CONFIG_DEBUG_UART_PL011)
	381
	382	#include <debug_uart.h>
	383
	384	static void _debug_uart_init(void)
	385	{
	386	#ifndef CONFIG_DEBUG_UART_SKIP_INIT
	387	struct pl01x_regs regs = (struct pl01x_regs )CONFIG_DEBUG_UART_BASE;
	388	enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
	389	TYPE_PL011 : TYPE_PL010;
	390
	391	pl01x_generic_serial_init(regs, type);
	392	pl01x_generic_setbrg(regs, type,
	393	CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
	394	#endif
	395	}
	396
	397	static inline void _debug_uart_putc(int ch)
	398	{
	399	struct pl01x_regs regs = (struct pl01x_regs )CONFIG_DEBUG_UART_BASE;
	400
	401	pl01x_putc(regs, ch);
	402	}
	403
	404	DEBUG_UART_FUNCS
	405
	406	#endif