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[people/ms/u-boot.git] / drivers / serial / serial_sh.h
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3f6c8e36
NI		 1/*
2 * Copy and modify from linux/drivers/serial/sh-sci.h
3 */
4
59088e4a
NI		 5#include <dm/platform_data/serial_sh.h>
6
3f6c8e36
NI		 7struct uart_port {
8 unsigned long iobase; /* in/out[bwl] */
9 unsigned char *membase; /* read/write[bwl] */
10 unsigned long mapbase; /* for ioremap */
59088e4a
NI		 11 enum sh_serial_type type; /* port type */
12 enum sh_clk_mode clk_mode; /* clock mode */
3f6c8e36
NI		 13};
14
3f6c8e36
NI		 15#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
16#include <asm/regs306x.h>
17#endif
18#if defined(CONFIG_H8S2678)
19#include <asm/regs267x.h>
20#endif
21
22#if defined(CONFIG_CPU_SH7706) || \
23 defined(CONFIG_CPU_SH7707) || \
24 defined(CONFIG_CPU_SH7708) || \
25 defined(CONFIG_CPU_SH7709)
26# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
27# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
28# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
29#elif defined(CONFIG_CPU_SH7705)
30# define SCIF0 0xA4400000
31# define SCIF2 0xA4410000
32# define SCSMR_Ir 0xA44A0000
33# define IRDA_SCIF SCIF0
34# define SCPCR 0xA4000116
35# define SCPDR 0xA4000136
36
37/* Set the clock source,
38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
40 */
41# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
42#elif defined(CONFIG_CPU_SH7720) || \
43 defined(CONFIG_CPU_SH7721) || \
44 defined(CONFIG_ARCH_SH7367) || \
45 defined(CONFIG_ARCH_SH7377) || \
c3d6a357 46 defined(CONFIG_ARCH_SH7372) || \
d61678e0
HS		 47 defined(CONFIG_SH73A0) || \
48 defined(CONFIG_R8A7740)
3f6c8e36
NI		 49# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
50# define PORT_PTCR 0xA405011EUL
51# define PORT_PVCR 0xA4050122UL
52# define SCIF_ORER 0x0200 /* overrun error bit */
53#elif defined(CONFIG_SH_RTS7751R2D)
54# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56# define SCIF_ORER 0x0001 /* overrun error bit */
57# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58#elif defined(CONFIG_CPU_SH7750) || \
59 defined(CONFIG_CPU_SH7750R) || \
60 defined(CONFIG_CPU_SH7750S) || \
61 defined(CONFIG_CPU_SH7091) || \
62 defined(CONFIG_CPU_SH7751) || \
63 defined(CONFIG_CPU_SH7751R)
64# define SCSPTR1 0xffe0001c /* 8 bit SCI */
65# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
70#elif defined(CONFIG_CPU_SH7760)
71# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
72# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
73# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */
75# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
76#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCIF_ORER 0x0001 /* overrun error bit */
79# define PACR 0xa4050100
80# define PBCR 0xa4050102
81# define SCSCR_INIT(port) 0x3B
82#elif defined(CONFIG_CPU_SH7343)
83# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
86# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
87# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
88#elif defined(CONFIG_CPU_SH7722)
89# define PADR 0xA4050120
99057064 90# undef PSDR
3f6c8e36
NI		 91# define PSDR 0xA405013e
92# define PWDR 0xA4050166
93# define PSCR 0xA405011E
94# define SCIF_ORER 0x0001 /* overrun error bit */
95# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96#elif defined(CONFIG_CPU_SH7366)
97# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
98# define SCSPTR0 SCPDR0
99# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101#elif defined(CONFIG_CPU_SH7723)
102# define SCSPTR0 0xa4050160
103# define SCSPTR1 0xa405013e
104# define SCSPTR2 0xa4050160
105# define SCSPTR3 0xa405013e
106# define SCSPTR4 0xa4050128
107# define SCSPTR5 0xa4050128
108# define SCIF_ORER 0x0001 /* overrun error bit */
109# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
110#elif defined(CONFIG_CPU_SH7724)
111# define SCIF_ORER 0x0001 /* overrun error bit */
112# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
2a57e7ec
NI		 115#elif defined(CONFIG_CPU_SH7734)
116# define SCSPTR0 0xFFE40020
117# define SCSPTR1 0xFFE41020
118# define SCSPTR2 0xFFE42020
119# define SCSPTR3 0xFFE43020
120# define SCSPTR4 0xFFE44020
121# define SCSPTR5 0xFFE45020
122# define SCIF_ORER 0x0001 /* overrun error bit */
123# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
3f6c8e36
NI		 124#elif defined(CONFIG_CPU_SH4_202)
125# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
126# define SCIF_ORER 0x0001 /* overrun error bit */
127# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
128#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
129# define SCIF_BASE_ADDR 0x01030000
130# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
131# define SCIF_PTR2_OFFS 0x0000020
132# define SCIF_LSR2_OFFS 0x0000024
133# define SCSPTR\
134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
135# define SCLSR2\
136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
137# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
138#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
139# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
140# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
141#elif defined(CONFIG_H8S2678)
142# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
143# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
f3bf212a
YS		 144#elif defined(CONFIG_CPU_SH7757) || \
145 defined(CONFIG_CPU_SH7752) || \
146 defined(CONFIG_CPU_SH7753)
3f6c8e36
NI		 147# define SCSPTR0 0xfe4b0020
148# define SCSPTR1 0xfe4b0020
149# define SCSPTR2 0xfe4b0020
150# define SCIF_ORER 0x0001
151# define SCSCR_INIT(port) 0x38
152# define SCIF_ONLY
153#elif defined(CONFIG_CPU_SH7763)
154# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
155# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
156# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
157# define SCIF_ORER 0x0001 /* overrun error bit */
158# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
159#elif defined(CONFIG_CPU_SH7770)
160# define SCSPTR0 0xff923020 /* 16 bit SCIF */
161# define SCSPTR1 0xff924020 /* 16 bit SCIF */
162# define SCSPTR2 0xff925020 /* 16 bit SCIF */
163# define SCIF_ORER 0x0001 /* overrun error bit */
164# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
165#elif defined(CONFIG_CPU_SH7780)
166# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
167# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
168# define SCIF_ORER 0x0001 /* Overrun error bit */
169
170#if defined(CONFIG_SH_SH2007)
171/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
172# define SCSCR_INIT(port) 0x38
173#else
174/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
175# define SCSCR_INIT(port) 0x3a
176#endif
177
178#elif defined(CONFIG_CPU_SH7785) || \
179 defined(CONFIG_CPU_SH7786)
180# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
181# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
182# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
183# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
184# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
185# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
186# define SCIF_ORER 0x0001 /* Overrun error bit */
187# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
188#elif defined(CONFIG_CPU_SH7201) || \
189 defined(CONFIG_CPU_SH7203) || \
190 defined(CONFIG_CPU_SH7206) || \
7fbeb642
PE		 191 defined(CONFIG_CPU_SH7263) || \
192 defined(CONFIG_CPU_SH7264)
3f6c8e36
NI		 193# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
194# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
195# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
196# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
197# if defined(CONFIG_CPU_SH7201)
198# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
199# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
200# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
201# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
202# endif
203# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
99744b7e
PE		 204#elif defined(CONFIG_CPU_SH7269)
205# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
206# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
207# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
208# define SCSPTR3 0xe8008820 /* 16 bit SCIF */
209# define SCSPTR4 0xe8009020 /* 16 bit SCIF */
210# define SCSPTR5 0xe8009820 /* 16 bit SCIF */
211# define SCSPTR6 0xe800a020 /* 16 bit SCIF */
212# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
213# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
3f6c8e36
NI		 214#elif defined(CONFIG_CPU_SH7619)
215# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
216# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
217# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
218# define SCIF_ORER 0x0001 /* overrun error bit */
219# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
220#elif defined(CONFIG_CPU_SHX3)
221# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
222# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
223# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
224# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
225# define SCIF_ORER 0x0001 /* Overrun error bit */
226# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
8591ac8b
CB		 227#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
228 defined(CONFIG_R7S72100)
53be7bf2
VB		 229# if defined(CONFIG_SCIF_A)
230# define SCIF_ORER 0x0200
231# else
232# define SCIF_ORER 0x0001
233# endif
2cbb17c0
VB		 234# define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
235 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
3f6c8e36
NI		 236#else
237# error CPU subtype not defined
238#endif
239
240/* SCSCR */
241#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
242#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
243#define SCI_CTRL_FLAGS_TE 0x20 /* all */
244#define SCI_CTRL_FLAGS_RE 0x10 /* all */
245#if defined(CONFIG_CPU_SH7750) || \
246 defined(CONFIG_CPU_SH7091) || \
247 defined(CONFIG_CPU_SH7750R) || \
248 defined(CONFIG_CPU_SH7722) || \
2a57e7ec 249 defined(CONFIG_CPU_SH7734) || \
3f6c8e36
NI		 250 defined(CONFIG_CPU_SH7750S) || \
251 defined(CONFIG_CPU_SH7751) || \
252 defined(CONFIG_CPU_SH7751R) || \
253 defined(CONFIG_CPU_SH7763) || \
254 defined(CONFIG_CPU_SH7780) || \
255 defined(CONFIG_CPU_SH7785) || \
256 defined(CONFIG_CPU_SH7786) || \
257 defined(CONFIG_CPU_SHX3)
258#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
259#elif defined(CONFIG_CPU_SH7724)
260#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
261#else
262#define SCI_CTRL_FLAGS_REIE 0
263#endif
264/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
265/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
266/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
267/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
268
269/* SCxSR SCI */
270#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
271#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
272#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
273#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
274#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
275#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
276/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
277/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
278
279#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
280
281/* SCxSR SCIF */
282#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
283#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
284#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
285#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
286#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
287#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
288#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
289#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
290
291#if defined(CONFIG_CPU_SH7705) || \
292 defined(CONFIG_CPU_SH7720) || \
293 defined(CONFIG_CPU_SH7721) || \
294 defined(CONFIG_ARCH_SH7367) || \
295 defined(CONFIG_ARCH_SH7377) || \
c3d6a357 296 defined(CONFIG_ARCH_SH7372) || \
d61678e0
HS		 297 defined(CONFIG_SH73A0) || \
298 defined(CONFIG_R8A7740)
3f6c8e36
NI		 299# define SCIF_ORER 0x0200
300# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
301# define SCIF_RFDC_MASK 0x007f
302# define SCIF_TXROOM_MAX 64
303#elif defined(CONFIG_CPU_SH7763)
304# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
305# define SCIF_RFDC_MASK 0x007f
306# define SCIF_TXROOM_MAX 64
307/* SH7763 SCIF2 support */
308# define SCIF2_RFDC_MASK 0x001f
309# define SCIF2_TXROOM_MAX 16
a6e25b2e 310#elif defined(CONFIG_RCAR_GEN2)
48ca882c 311# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
53be7bf2
VB		 312# if defined(CONFIG_SCIF_A)
313# define SCIF_RFDC_MASK 0x007f
314# else
315# define SCIF_RFDC_MASK 0x001f
316# endif
3f6c8e36
NI		 317#else
318# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
319# define SCIF_RFDC_MASK 0x001f
320# define SCIF_TXROOM_MAX 16
321#endif
322
323#ifndef SCIF_ORER
324#define SCIF_ORER 0x0000
325#endif
326
327#define SCxSR_TEND(port)\
328 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
329#define SCxSR_ERRORS(port)\
330 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
331#define SCxSR_RDxF(port)\
332 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
333#define SCxSR_TDxE(port)\
334 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
335#define SCxSR_FER(port)\
336 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
337#define SCxSR_PER(port)\
338 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
339#define SCxSR_BRK(port)\
340 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
341#define SCxSR_ORER(port)\
342 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
343
344#if defined(CONFIG_CPU_SH7705) || \
345 defined(CONFIG_CPU_SH7720) || \
346 defined(CONFIG_CPU_SH7721) || \
347 defined(CONFIG_ARCH_SH7367) || \
348 defined(CONFIG_ARCH_SH7377) || \
c3d6a357 349 defined(CONFIG_ARCH_SH7372) || \
d61678e0
HS		 350 defined(CONFIG_SH73A0) || \
351 defined(CONFIG_R8A7740)
3f6c8e36
NI		 352# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
353# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
354# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
355# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
356#else
357# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
358# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
359# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
360# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
361#endif
362
363/* SCFCR */
364#define SCFCR_RFRST 0x0002
365#define SCFCR_TFRST 0x0004
366#define SCFCR_TCRST 0x4000
367#define SCFCR_MCE 0x0008
368
369#define SCI_MAJOR 204
370#define SCI_MINOR_START 8
371
372/* Generic serial flags */
373#define SCI_RX_THROTTLE 0x0000001
374
375#define SCI_MAGIC 0xbabeface
376
377/*
378 * Events are used to schedule things to happen at timer-interrupt
379 * time, instead of at rs interrupt time.
380 */
381#define SCI_EVENT_WRITE_WAKEUP 0
382
383#define SCI_IN(size, offset)\
384 if ((size) == 8) {\
385 return readb(port->membase + (offset));\
386 } else {\
387 return readw(port->membase + (offset));\
388 }
389#define SCI_OUT(size, offset, value)\
390 if ((size) == 8) {\
391 writeb(value, port->membase + (offset));\
392 } else if ((size) == 16) {\
393 writew(value, port->membase + (offset));\
394 }
395
396#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
397 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
398 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
399 SCI_IN(scif_size, scif_offset)\
400 } else { /* PORT_SCI or PORT_SCIFA */\
401 SCI_IN(sci_size, sci_offset);\
402 }\
403 }\
404static inline void sci_##name##_out(struct uart_port *port,\
405 unsigned int value) {\
406 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
407 SCI_OUT(scif_size, scif_offset, value)\
408 } else { /* PORT_SCI or PORT_SCIFA */\
409 SCI_OUT(sci_size, sci_offset, value);\
410 }\
411}
412
413#ifdef CONFIG_H8300
414/* h8300 don't have SCIF */
415#define CPU_SCIF_FNS(name) \
416 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
417 return 0;\
418 }\
419 static inline void sci_##name##_out(struct uart_port *port,\
420 unsigned int value) {\
421 }
422#else
423#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
424 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
425 SCI_IN(scif_size, scif_offset);\
426 }\
427 static inline void sci_##name##_out(struct uart_port *port,\
428 unsigned int value) {\
429 SCI_OUT(scif_size, scif_offset, value);\
430 }
431#endif
432
433#define CPU_SCI_FNS(name, sci_offset, sci_size)\
434 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
435 SCI_IN(sci_size, sci_offset);\
436 }\
437 static inline void sci_##name##_out(struct uart_port *port,\
438 unsigned int value) {\
439 SCI_OUT(sci_size, sci_offset, value);\
440 }
441
7d236662 442#if defined(CONFIG_CPU_SH3) || \
3f6c8e36
NI		 443 defined(CONFIG_ARCH_SH7367) || \
444 defined(CONFIG_ARCH_SH7377) || \
c3d6a357 445 defined(CONFIG_ARCH_SH7372) || \
d61678e0
HS		 446 defined(CONFIG_SH73A0) || \
447 defined(CONFIG_R8A7740)
3f6c8e36
NI		 448#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
449#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
450 sh4_sci_offset, sh4_sci_size, \
451 sh3_scif_offset, sh3_scif_size, \
452 sh4_scif_offset, sh4_scif_size, \
453 h8_sci_offset, h8_sci_size) \
454 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
455 sh4_scif_offset, sh4_scif_size)
456#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
457 sh4_scif_offset, sh4_scif_size) \
458 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
459#elif defined(CONFIG_CPU_SH7705) || \
460 defined(CONFIG_CPU_SH7720) || \
461 defined(CONFIG_CPU_SH7721) || \
462 defined(CONFIG_ARCH_SH7367) || \
c3d6a357
NI		 463 defined(CONFIG_ARCH_SH7377) || \
464 defined(CONFIG_SH73A0)
3f6c8e36
NI		 465#define SCIF_FNS(name, scif_offset, scif_size) \
466 CPU_SCIF_FNS(name, scif_offset, scif_size)
d61678e0
HS		 467#elif defined(CONFIG_ARCH_SH7372) || \
468 defined(CONFIG_R8A7740)
3f6c8e36
NI		 469#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
470 sh4_scifb_offset, sh4_scifb_size) \
471 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
472 sh4_scifb_offset, sh4_scifb_size)
473#define SCIF_FNS(name, scif_offset, scif_size) \
474 CPU_SCIF_FNS(name, scif_offset, scif_size)
475#else
476#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
477 sh4_sci_offset, sh4_sci_size, \
478 sh3_scif_offset, sh3_scif_size,\
479 sh4_scif_offset, sh4_scif_size, \
480 h8_sci_offset, h8_sci_size) \
481 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
482 sh3_scif_offset, sh3_scif_size)
483#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
484 sh4_scif_offset, sh4_scif_size) \
485 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
486#endif
487#elif defined(__H8300H__) || defined(__H8300S__)
488#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
489 sh4_sci_offset, sh4_sci_size, \
490 sh3_scif_offset, sh3_scif_size,\
491 sh4_scif_offset, sh4_scif_size, \
492 h8_sci_offset, h8_sci_size) \
493 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
494#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
495 sh4_scif_offset, sh4_scif_size) \
496 CPU_SCIF_FNS(name)
497#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
498 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
499 sh4_scif_offset, sh4_scif_size) \
500 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
501 sh4_scif_offset, sh4_scif_size)
502 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
503 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
504#else
505#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
506 sh4_sci_offset, sh4_sci_size, \
507 sh3_scif_offset, sh3_scif_size,\
508 sh4_scif_offset, sh4_scif_size, \
509 h8_sci_offset, h8_sci_size) \
510 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
511 sh4_scif_offset, sh4_scif_size)
512#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
513 sh4_scif_offset, sh4_scif_size) \
514 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
515#endif
516
517#if defined(CONFIG_CPU_SH7705) || \
518 defined(CONFIG_CPU_SH7720) || \
519 defined(CONFIG_CPU_SH7721) || \
520 defined(CONFIG_ARCH_SH7367) || \
c3d6a357
NI		 521 defined(CONFIG_ARCH_SH7377) || \
522 defined(CONFIG_SH73A0)
3f6c8e36
NI		 523
524SCIF_FNS(SCSMR, 0x00, 16)
525SCIF_FNS(SCBRR, 0x04, 8)
526SCIF_FNS(SCSCR, 0x08, 16)
527SCIF_FNS(SCTDSR, 0x0c, 8)
528SCIF_FNS(SCFER, 0x10, 16)
529SCIF_FNS(SCxSR, 0x14, 16)
530SCIF_FNS(SCFCR, 0x18, 16)
531SCIF_FNS(SCFDR, 0x1c, 16)
532SCIF_FNS(SCxTDR, 0x20, 8)
533SCIF_FNS(SCxRDR, 0x24, 8)
534SCIF_FNS(SCLSR, 0x00, 0)
59088e4a 535SCIF_FNS(DL, 0x00, 0) /* dummy */
d61678e0
HS		 536#elif defined(CONFIG_ARCH_SH7372) || \
537 defined(CONFIG_R8A7740)
3f6c8e36
NI		 538SCIF_FNS(SCSMR, 0x00, 16)
539SCIF_FNS(SCBRR, 0x04, 8)
540SCIF_FNS(SCSCR, 0x08, 16)
541SCIF_FNS(SCTDSR, 0x0c, 16)
542SCIF_FNS(SCFER, 0x10, 16)
543SCIF_FNS(SCxSR, 0x14, 16)
544SCIF_FNS(SCFCR, 0x18, 16)
545SCIF_FNS(SCFDR, 0x1c, 16)
546SCIF_FNS(SCTFDR, 0x38, 16)
547SCIF_FNS(SCRFDR, 0x3c, 16)
548SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
549SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
550SCIF_FNS(SCLSR, 0x00, 0)
59088e4a 551SCIF_FNS(DL, 0x00, 0) /* dummy */
3f6c8e36
NI		 552#elif defined(CONFIG_CPU_SH7723) ||\
553 defined(CONFIG_CPU_SH7724)
554SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
555SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
556SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
557SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
558SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
559SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
560SCIx_FNS(SCSPTR, 0, 0, 0, 0)
561SCIF_FNS(SCTDSR, 0x0c, 8)
562SCIF_FNS(SCFER, 0x10, 16)
563SCIF_FNS(SCFCR, 0x18, 16)
564SCIF_FNS(SCFDR, 0x1c, 16)
565SCIF_FNS(SCLSR, 0x24, 16)
59088e4a 566SCIF_FNS(DL, 0x00, 0) /* dummy */
a6e25b2e 567#elif defined(CONFIG_RCAR_GEN2)
53be7bf2
VB		 568/* SCIFA and SCIF register offsets and size */
569SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
570SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
571SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
572SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
573SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
574SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
575SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
576SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
577SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
578SCIF_FNS(DL, 0, 0, 0x30, 16)
579SCIF_FNS(CKS, 0, 0, 0x34, 16)
580#if defined(CONFIG_SCIF_A)
581SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
582#else
583SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
584#endif
3f6c8e36
NI		 585#else
586/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
587/* name off sz off sz off sz off sz off sz*/
588SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
589SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
590SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
591SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
592SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
593SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
594SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
595#if defined(CONFIG_CPU_SH7760) || \
596 defined(CONFIG_CPU_SH7780) || \
597 defined(CONFIG_CPU_SH7785) || \
598 defined(CONFIG_CPU_SH7786)
599SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
600SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
601SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
602SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
603SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
604#elif defined(CONFIG_CPU_SH7763)
605SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
606SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
607SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
608SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
609SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
610SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
611SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
612#else
59088e4a 613
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NI		 614SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
615#if defined(CONFIG_CPU_SH7722)
616SCIF_FNS(SCSPTR, 0, 0, 0, 0)
617#else
618SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
619#endif
59088e4a
NI		 620SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
621#endif
59088e4a 622SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
3f6c8e36 623#endif
3f6c8e36
NI		 624#define sci_in(port, reg) sci_##reg##_in(port)
625#define sci_out(port, reg, value) sci_##reg##_out(port, value)
626
627/* H8/300 series SCI pins assignment */
628#if defined(__H8300H__) || defined(__H8300S__)
629static const struct __attribute__((packed)) {
630 int port; /* GPIO port no */
631 unsigned short rx, tx; /* GPIO bit no */
632} h8300_sci_pins[] = {
633#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
634 { /* SCI0 */
635 .port = H8300_GPIO_P9,
636 .rx = H8300_GPIO_B2,
637 .tx = H8300_GPIO_B0,
638 },
639 { /* SCI1 */
640 .port = H8300_GPIO_P9,
641 .rx = H8300_GPIO_B3,
642 .tx = H8300_GPIO_B1,
643 },
644 { /* SCI2 */
645 .port = H8300_GPIO_PB,
646 .rx = H8300_GPIO_B7,
647 .tx = H8300_GPIO_B6,
648 }
649#elif defined(CONFIG_H8S2678)
650 { /* SCI0 */
651 .port = H8300_GPIO_P3,
652 .rx = H8300_GPIO_B2,
653 .tx = H8300_GPIO_B0,
654 },
655 { /* SCI1 */
656 .port = H8300_GPIO_P3,
657 .rx = H8300_GPIO_B3,
658 .tx = H8300_GPIO_B1,
659 },
660 { /* SCI2 */
661 .port = H8300_GPIO_P5,
662 .rx = H8300_GPIO_B1,
663 .tx = H8300_GPIO_B0,
664 }
665#endif
666};
667#endif
668
669#if defined(CONFIG_CPU_SH7706) || \
670 defined(CONFIG_CPU_SH7707) || \
671 defined(CONFIG_CPU_SH7708) || \
672 defined(CONFIG_CPU_SH7709)
673static inline int sci_rxd_in(struct uart_port *port)
674{
675 if (port->mapbase == 0xfffffe80)
676 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
677 return 1;
678}
679#elif defined(CONFIG_CPU_SH7750) || \
680 defined(CONFIG_CPU_SH7751) || \
681 defined(CONFIG_CPU_SH7751R) || \
682 defined(CONFIG_CPU_SH7750R) || \
683 defined(CONFIG_CPU_SH7750S) || \
684 defined(CONFIG_CPU_SH7091)
685static inline int sci_rxd_in(struct uart_port *port)
686{
687 if (port->mapbase == 0xffe00000)
688 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
689 return 1;
690}
691#elif defined(__H8300H__) || defined(__H8300S__)
692static inline int sci_rxd_in(struct uart_port *port)
693{
694 int ch = (port->mapbase - SMR0) >> 3;
695 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
696}
697#else /* default case for non-SCI processors */
698static inline int sci_rxd_in(struct uart_port *port)
699{
700 return 1;
701}
702#endif
703
704/*
705 * Values for the BitRate Register (SCBRR)
706 *
707 * The values are actually divisors for a frequency which can
708 * be internal to the SH3 (14.7456MHz) or derived from an external
709 * clock source. This driver assumes the internal clock is used;
710 * to support using an external clock source, config options or
711 * possibly command-line options would need to be added.
712 *
713 * Also, to support speeds below 2400 (why?) the lower 2 bits of
714 * the SCSMR register would also need to be set to non-zero values.
715 *
716 * -- Greg Banks 27Feb2000
717 *
718 * Answer: The SCBRR register is only eight bits, and the value in
719 * it gets larger with lower baud rates. At around 2400 (depending on
720 * the peripherial module clock) you run out of bits. However the
721 * lower two bits of SCSMR allow the module clock to be divided down,
722 * scaling the value which is needed in SCBRR.
723 *
724 * -- Stuart Menefy - 23 May 2000
725 *
726 * I meant, why would anyone bother with bitrates below 2400.
727 *
728 * -- Greg Banks - 7Jul2000
729 *
730 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
731 * tape reader as a console!
732 *
733 * -- Mitch Davis - 15 Jul 2000
734 */
735
736#if (defined(CONFIG_CPU_SH7780) || \
737 defined(CONFIG_CPU_SH7785) || \
738 defined(CONFIG_CPU_SH7786)) && \
739 !defined(CONFIG_SH_SH2007)
740#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
741#elif defined(CONFIG_CPU_SH7705) || \
742 defined(CONFIG_CPU_SH7720) || \
743 defined(CONFIG_CPU_SH7721) || \
744 defined(CONFIG_ARCH_SH7367) || \
745 defined(CONFIG_ARCH_SH7377) || \
c3d6a357 746 defined(CONFIG_ARCH_SH7372) || \
d61678e0
HS		 747 defined(CONFIG_SH73A0) || \
748 defined(CONFIG_R8A7740)
3f6c8e36
NI		 749#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
750#elif defined(CONFIG_CPU_SH7723) ||\
751 defined(CONFIG_CPU_SH7724)
59088e4a 752static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
3f6c8e36 753{
59088e4a 754 if (port->type == PORT_SCIF)
3f6c8e36
NI		 755 return (clk+16*bps)/(32*bps)-1;
756 else
757 return ((clk*2)+16*bps)/(16*bps)-1;
758}
59088e4a 759#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
3f6c8e36
NI		 760#elif defined(__H8300H__) || defined(__H8300S__)
761#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
a6e25b2e 762#elif defined(CONFIG_RCAR_GEN2)
53022c31 763#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
53be7bf2
VB		 764 #if defined(CONFIG_SCIF_A)
765 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
766 #else
767 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
768 #endif
3f6c8e36
NI		 769#else /* Generic SH */
770#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
771#endif
59088e4a
NI		 772
773#ifndef DL_VALUE
774#define DL_VALUE(bps, clk) 0
775#endif
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