[people/ms/u-boot.git] / drivers / serial / serial_stm32x7.c

/*
 * (C) Copyright 2016
 * Vikas Manocha, <vikas.manocha@st.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <asm/io.h>
#include <serial.h>
#include <asm/arch/stm32.h>
#include "serial_stm32x7.h"

DECLARE_GLOBAL_DATA_PTR;

static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	fdt_addr_t base = plat->base;
	u32 int_div, mantissa, fraction, oversampling;

	int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);

	if (int_div < 16) {
		oversampling = 8;
		setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
	} else {
		oversampling = 16;
		clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
	}

	mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
	fraction = int_div % oversampling;

	writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));

	return 0;
}

static int stm32_serial_getc(struct udevice *dev)
{
	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	fdt_addr_t base = plat->base;

	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
		return -EAGAIN;

	return readl(base + RDR_OFFSET(stm32f4));
}

static int stm32_serial_putc(struct udevice *dev, const char c)
{
	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	fdt_addr_t base = plat->base;

	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
		return -EAGAIN;

	writel(c, base + TDR_OFFSET(stm32f4));

	return 0;
}

static int stm32_serial_pending(struct udevice *dev, bool input)
{
	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	bool stm32f4 = plat->uart_info->stm32f4;
	fdt_addr_t base = plat->base;

	if (input)
		return readl(base + ISR_OFFSET(stm32f4)) &
			USART_SR_FLAG_RXNE ? 1 : 0;
	else
		return readl(base + ISR_OFFSET(stm32f4)) &
			USART_SR_FLAG_TXE ? 0 : 1;
}

static int stm32_serial_probe(struct udevice *dev)
{
	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	fdt_addr_t base = plat->base;
	bool stm32f4;
	u8 uart_enable_bit;

	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
	stm32f4 = plat->uart_info->stm32f4;
	uart_enable_bit = plat->uart_info->uart_enable_bit;

#ifdef CONFIG_CLK
	int ret;
	struct clk clk;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}
#endif

	plat->clock_rate = clk_get_rate(&clk);
	if (plat->clock_rate < 0) {
		clk_disable(&clk);
		return plat->clock_rate;
	};

	/* Disable uart-> disable overrun-> enable uart */
	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
		     BIT(uart_enable_bit));
	if (plat->uart_info->has_overrun_disable)
		setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
		     BIT(uart_enable_bit));

	return 0;
}

#if CONFIG_IS_ENABLED(OF_CONTROL)
static const struct udevice_id stm32_serial_id[] = {
	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32x7_info},
	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32x7_info},
	{}
};

static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
{
	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);

	plat->base = devfdt_get_addr(dev);
	if (plat->base == FDT_ADDR_T_NONE)
		return -EINVAL;

	return 0;
}
#endif

static const struct dm_serial_ops stm32_serial_ops = {
	.putc = stm32_serial_putc,
	.pending = stm32_serial_pending,
	.getc = stm32_serial_getc,
	.setbrg = stm32_serial_setbrg,
};

U_BOOT_DRIVER(serial_stm32) = {
	.name = "serial_stm32x7",
	.id = UCLASS_SERIAL,
	.of_match = of_match_ptr(stm32_serial_id),
	.ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
	.platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
	.ops = &stm32_serial_ops,
	.probe = stm32_serial_probe,
	.flags = DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
6a12cebd VM	1	/*
	2	* (C) Copyright 2016
	3	* Vikas Manocha, <vikas.manocha@st.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
fd03b83a	9	#include <clk.h>
6a12cebd VM	10	#include <dm.h>
	11	#include <asm/io.h>
	12	#include <serial.h>
ba0a3c16	13	#include <asm/arch/stm32.h>
6a12cebd VM	14	#include "serial_stm32x7.h"
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
	19	{
60a996ba PC	20	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	21	bool stm32f4 = plat->uart_info->stm32f4;
	22	fdt_addr_t base = plat->base;
27265cee	23	u32 int_div, mantissa, fraction, oversampling;
ba0a3c16	24
27265cee	25	int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
1afcf9cb PC	26
	27	if (int_div < 16) {
	28	oversampling = 8;
60a996ba	29	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
1afcf9cb PC	30	} else {
1afcf9cb PC	31	oversampling = 16;
60a996ba	32	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
1afcf9cb PC	33	}
	34
	35	mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
	36	fraction = int_div % oversampling;
	37
60a996ba	38	writel(mantissa \| fraction, base + BRR_OFFSET(stm32f4));
6a12cebd VM	39
	40	return 0;
	41	}
	42
	43	static int stm32_serial_getc(struct udevice *dev)
	44	{
60a996ba PC	45	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	46	bool stm32f4 = plat->uart_info->stm32f4;
	47	fdt_addr_t base = plat->base;
6a12cebd	48
60a996ba	49	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
6a12cebd VM	50	return -EAGAIN;
6a12cebd VM	51
60a996ba	52	return readl(base + RDR_OFFSET(stm32f4));
6a12cebd VM	53	}
	54
	55	static int stm32_serial_putc(struct udevice *dev, const char c)
	56	{
60a996ba PC	57	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	58	bool stm32f4 = plat->uart_info->stm32f4;
	59	fdt_addr_t base = plat->base;
6a12cebd	60
60a996ba	61	if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
6a12cebd VM	62	return -EAGAIN;
6a12cebd VM	63
60a996ba	64	writel(c, base + TDR_OFFSET(stm32f4));
6a12cebd VM	65
	66	return 0;
	67	}
	68
	69	static int stm32_serial_pending(struct udevice *dev, bool input)
	70	{
60a996ba PC	71	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	72	bool stm32f4 = plat->uart_info->stm32f4;
	73	fdt_addr_t base = plat->base;
6a12cebd VM	74
6a12cebd VM	75	if (input)
60a996ba PC	76	return readl(base + ISR_OFFSET(stm32f4)) &
60a996ba PC	77	USART_SR_FLAG_RXNE ? 1 : 0;
6a12cebd	78	else
60a996ba PC	79	return readl(base + ISR_OFFSET(stm32f4)) &
60a996ba PC	80	USART_SR_FLAG_TXE ? 0 : 1;
6a12cebd VM	81	}
	82
	83	static int stm32_serial_probe(struct udevice *dev)
	84	{
60a996ba PC	85	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
	86	fdt_addr_t base = plat->base;
	87	bool stm32f4;
	88	u8 uart_enable_bit;
	89
	90	plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
	91	stm32f4 = plat->uart_info->stm32f4;
	92	uart_enable_bit = plat->uart_info->uart_enable_bit;
fd03b83a VM	93
	94	#ifdef CONFIG_CLK
	95	int ret;
	96	struct clk clk;
	97
	98	ret = clk_get_by_index(dev, 0, &clk);
	99	if (ret < 0)
	100	return ret;
	101
	102	ret = clk_enable(&clk);
	103	if (ret) {
	104	dev_err(dev, "failed to enable clock\n");
	105	return ret;
	106	}
	107	#endif
	108
27265cee PC	109	plat->clock_rate = clk_get_rate(&clk);
	110	if (plat->clock_rate < 0) {
	111	clk_disable(&clk);
	112	return plat->clock_rate;
	113	};
	114
60a996ba PC	115	/* Disable uart-> disable overrun-> enable uart */
	116	clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE \| USART_CR1_TE \|
	117	BIT(uart_enable_bit));
	118	if (plat->uart_info->has_overrun_disable)
	119	setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
	120	setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE \| USART_CR1_TE \|
	121	BIT(uart_enable_bit));
6a12cebd VM	122
	123	return 0;
	124	}
	125
42bf5e7c VM	126	#if CONFIG_IS_ENABLED(OF_CONTROL)
42bf5e7c VM	127	static const struct udevice_id stm32_serial_id[] = {
60a996ba PC	128	{ .compatible = "st,stm32f7-uart", .data = (ulong)&stm32x7_info},
60a996ba PC	129	{ .compatible = "st,stm32h7-uart", .data = (ulong)&stm32x7_info},
42bf5e7c VM	130	{}
	131	};
	132
	133	static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
	134	{
	135	struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
42bf5e7c	136
60a996ba PC	137	plat->base = devfdt_get_addr(dev);
60a996ba PC	138	if (plat->base == FDT_ADDR_T_NONE)
42bf5e7c VM	139	return -EINVAL;
42bf5e7c VM	140
42bf5e7c VM	141	return 0;
	142	}
	143	#endif
	144
6a12cebd VM	145	static const struct dm_serial_ops stm32_serial_ops = {
	146	.putc = stm32_serial_putc,
	147	.pending = stm32_serial_pending,
	148	.getc = stm32_serial_getc,
	149	.setbrg = stm32_serial_setbrg,
	150	};
	151
	152	U_BOOT_DRIVER(serial_stm32) = {
	153	.name = "serial_stm32x7",
	154	.id = UCLASS_SERIAL,
42bf5e7c VM	155	.of_match = of_match_ptr(stm32_serial_id),
	156	.ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
	157	.platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
6a12cebd VM	158	.ops = &stm32_serial_ops,
	159	.probe = stm32_serial_probe,
	160	.flags = DM_FLAG_PRE_RELOC,
	161	};