[people/ms/u-boot.git] / drivers / spi / exynos_spi.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Padmavathi Venna <padma.v@samsung.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <fdtdec.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/spi.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct exynos_spi_platdata {
	enum periph_id periph_id;
	s32 frequency;		/* Default clock frequency, -1 for none */
	struct exynos_spi *regs;
	uint deactivate_delay_us;	/* Delay to wait after deactivate */
};

struct exynos_spi_priv {
	struct exynos_spi *regs;
	unsigned int freq;		/* Default frequency */
	unsigned int mode;
	enum periph_id periph_id;	/* Peripheral ID for this device */
	unsigned int fifo_size;
	int skip_preamble;
	ulong last_transaction_us;	/* Time of last transaction end */
};

/**
 * Flush spi tx, rx fifos and reset the SPI controller
 *
 * @param regs	Pointer to SPI registers
 */
static void spi_flush_fifo(struct exynos_spi *regs)
{
	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
	setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
}

static void spi_get_fifo_levels(struct exynos_spi *regs,
	int *rx_lvl, int *tx_lvl)
{
	uint32_t spi_sts = readl(&regs->spi_sts);

	*rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
	*tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
}

/**
 * If there's something to transfer, do a software reset and set a
 * transaction size.
 *
 * @param regs	SPI peripheral registers
 * @param count	Number of bytes to transfer
 * @param step	Number of bytes to transfer in each packet (1 or 4)
 */
static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
{
	debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);

	/* For word address we need to swap bytes */
	if (step == 4) {
		setbits_le32(&regs->mode_cfg,
			     SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
		count /= 4;
		setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
			SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
			SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
	} else {
		/* Select byte access and clear the swap configuration */
		clrbits_le32(&regs->mode_cfg,
			     SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
		writel(0, &regs->swap_cfg);
	}

	assert(count && count < (1 << 16));
	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);

	writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
}

static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
			void **dinp, void const **doutp, unsigned long flags)
{
	struct exynos_spi *regs = priv->regs;
	uchar *rxp = *dinp;
	const uchar *txp = *doutp;
	int rx_lvl, tx_lvl;
	uint out_bytes, in_bytes;
	int toread;
	unsigned start = get_timer(0);
	int stopping;
	int step;

	out_bytes = in_bytes = todo;

	stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
					!(priv->mode & SPI_SLAVE);

	/*
	 * Try to transfer words if we can. This helps read performance at
	 * SPI clock speeds above about 20MHz.
	 */
	step = 1;
	if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
	    !priv->skip_preamble)
		step = 4;

	/*
	 * If there's something to send, do a software reset and set a
	 * transaction size.
	 */
	spi_request_bytes(regs, todo, step);

	/*
	 * Bytes are transmitted/received in pairs. Wait to receive all the
	 * data because then transmission will be done as well.
	 */
	toread = in_bytes;

	while (in_bytes) {
		int temp;

		/* Keep the fifos full/empty. */
		spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);

		/*
		 * Don't completely fill the txfifo, since we don't want our
		 * rxfifo to overflow, and it may already contain data.
		 */
		while (tx_lvl < priv->fifo_size/2 && out_bytes) {
			if (!txp)
				temp = -1;
			else if (step == 4)
				temp = *(uint32_t *)txp;
			else
				temp = *txp;
			writel(temp, &regs->tx_data);
			out_bytes -= step;
			if (txp)
				txp += step;
			tx_lvl += step;
		}
		if (rx_lvl >= step) {
			while (rx_lvl >= step) {
				temp = readl(&regs->rx_data);
				if (priv->skip_preamble) {
					if (temp == SPI_PREAMBLE_END_BYTE) {
						priv->skip_preamble = 0;
						stopping = 0;
					}
				} else {
					if (rxp || stopping) {
						if (step == 4)
							*(uint32_t *)rxp = temp;
						else
							*rxp = temp;
						rxp += step;
					}
					in_bytes -= step;
				}
				toread -= step;
				rx_lvl -= step;
			}
		} else if (!toread) {
			/*
			 * We have run out of input data, but haven't read
			 * enough bytes after the preamble yet. Read some more,
			 * and make sure that we transmit dummy bytes too, to
			 * keep things going.
			 */
			assert(!out_bytes);
			out_bytes = in_bytes;
			toread = in_bytes;
			txp = NULL;
			spi_request_bytes(regs, toread, step);
		}
		if (priv->skip_preamble && get_timer(start) > 100) {
			debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
			      in_bytes, out_bytes);
			return -ETIMEDOUT;
		}
	}

	*dinp = rxp;
	*doutp = txp;

	return 0;
}

/**
 * Activate the CS by driving it LOW
 *
 * @param slave	Pointer to spi_slave to which controller has to
 *		communicate with
 */
static void spi_cs_activate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
	struct exynos_spi_priv *priv = dev_get_priv(bus);

	/* If it's too soon to do another transaction, wait */
	if (pdata->deactivate_delay_us &&
	    priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < pdata->deactivate_delay_us)
			udelay(pdata->deactivate_delay_us - delay_us);
	}

	clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
	debug("Activate CS, bus '%s'\n", bus->name);
	priv->skip_preamble = priv->mode & SPI_PREAMBLE;
}

/**
 * Deactivate the CS by driving it HIGH
 *
 * @param slave	Pointer to spi_slave to which controller has to
 *		communicate with
 */
static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
	struct exynos_spi_priv *priv = dev_get_priv(bus);

	setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);

	/* Remember time of this transaction so we can honour the bus delay */
	if (pdata->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();

	debug("Deactivate CS, bus '%s'\n", bus->name);
}

static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
{
	struct exynos_spi_platdata *plat = bus->platdata;
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	plat->regs = (struct exynos_spi *)devfdt_get_addr(bus);
	plat->periph_id = pinmux_decode_periph_id(blob, node);

	if (plat->periph_id == PERIPH_ID_NONE) {
		debug("%s: Invalid peripheral ID %d\n", __func__,
			plat->periph_id);
		return -FDT_ERR_NOTFOUND;
	}

	/* Use 500KHz as a suitable default */
	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
					500000);
	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
					"spi-deactivate-delay", 0);
	debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, plat->regs, plat->periph_id, plat->frequency,
	      plat->deactivate_delay_us);

	return 0;
}

static int exynos_spi_probe(struct udevice *bus)
{
	struct exynos_spi_platdata *plat = dev_get_platdata(bus);
	struct exynos_spi_priv *priv = dev_get_priv(bus);

	priv->regs = plat->regs;
	if (plat->periph_id == PERIPH_ID_SPI1 ||
	    plat->periph_id == PERIPH_ID_SPI2)
		priv->fifo_size = 64;
	else
		priv->fifo_size = 256;

	priv->skip_preamble = 0;
	priv->last_transaction_us = timer_get_us();
	priv->freq = plat->frequency;
	priv->periph_id = plat->periph_id;

	return 0;
}

static int exynos_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct exynos_spi_priv *priv = dev_get_priv(bus);

	exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
	spi_flush_fifo(priv->regs);

	writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);

	return 0;
}

static int exynos_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct exynos_spi_priv *priv = dev_get_priv(bus);

	spi_flush_fifo(priv->regs);

	return 0;
}

static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
			   const void *dout, void *din, unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct exynos_spi_priv *priv = dev_get_priv(bus);
	int upto, todo;
	int bytelen;
	int ret = 0;

	/* spi core configured to do 8 bit transfers */
	if (bitlen % 8) {
		debug("Non byte aligned SPI transfer.\n");
		return -1;
	}

	/* Start the transaction, if necessary. */
	if ((flags & SPI_XFER_BEGIN))
		spi_cs_activate(dev);

	/*
	 * Exynos SPI limits each transfer to 65535 transfers. To keep
	 * things simple, allow a maximum of 65532 bytes. We could allow
	 * more in word mode, but the performance difference is small.
	 */
	bytelen = bitlen / 8;
	for (upto = 0; !ret && upto < bytelen; upto += todo) {
		todo = min(bytelen - upto, (1 << 16) - 4);
		ret = spi_rx_tx(priv, todo, &din, &dout, flags);
		if (ret)
			break;
	}

	/* Stop the transaction, if necessary. */
	if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
		spi_cs_deactivate(dev);
		if (priv->skip_preamble) {
			assert(!priv->skip_preamble);
			debug("Failed to complete premable transaction\n");
			ret = -1;
		}
	}

	return ret;
}

static int exynos_spi_set_speed(struct udevice *bus, uint speed)
{
	struct exynos_spi_platdata *plat = bus->platdata;
	struct exynos_spi_priv *priv = dev_get_priv(bus);
	int ret;

	if (speed > plat->frequency)
		speed = plat->frequency;
	ret = set_spi_clk(priv->periph_id, speed);
	if (ret)
		return ret;
	priv->freq = speed;
	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);

	return 0;
}

static int exynos_spi_set_mode(struct udevice *bus, uint mode)
{
	struct exynos_spi_priv *priv = dev_get_priv(bus);
	uint32_t reg;

	reg = readl(&priv->regs->ch_cfg);
	reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);

	if (mode & SPI_CPHA)
		reg |= SPI_CH_CPHA_B;

	if (mode & SPI_CPOL)
		reg |= SPI_CH_CPOL_L;

	writel(reg, &priv->regs->ch_cfg);
	priv->mode = mode;
	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops exynos_spi_ops = {
	.claim_bus	= exynos_spi_claim_bus,
	.release_bus	= exynos_spi_release_bus,
	.xfer		= exynos_spi_xfer,
	.set_speed	= exynos_spi_set_speed,
	.set_mode	= exynos_spi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id exynos_spi_ids[] = {
	{ .compatible = "samsung,exynos-spi" },
	{ }
};

U_BOOT_DRIVER(exynos_spi) = {
	.name	= "exynos_spi",
	.id	= UCLASS_SPI,
	.of_match = exynos_spi_ids,
	.ops	= &exynos_spi_ops,
	.ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
	.priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
	.probe	= exynos_spi_probe,
};
Commit	Line	Data
1bf43b82 RS	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Padmavathi Venna <padma.v@samsung.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
1bf43b82 RS	6	*/
	7
	8	#include <common.h>
73186c94 SG	9	#include <dm.h>
73186c94 SG	10	#include <errno.h>
1bf43b82 RS	11	#include <malloc.h>
1bf43b82 RS	12	#include <spi.h>
4d3acb9d	13	#include <fdtdec.h>
1bf43b82 RS	14	#include <asm/arch/clk.h>
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/cpu.h>
	17	#include <asm/arch/gpio.h>
	18	#include <asm/arch/pinmux.h>
77b55e8c	19	#include <asm/arch/spi.h>
1bf43b82 RS	20	#include <asm/io.h>
1bf43b82 RS	21
4d3acb9d RS	22	DECLARE_GLOBAL_DATA_PTR;
4d3acb9d RS	23
73186c94	24	struct exynos_spi_platdata {
1bf43b82 RS	25	enum periph_id periph_id;
	26	s32 frequency; /* Default clock frequency, -1 for none */
	27	struct exynos_spi *regs;
8d203afd	28	uint deactivate_delay_us; /* Delay to wait after deactivate */
1bf43b82 RS	29	};
1bf43b82 RS	30
73186c94	31	struct exynos_spi_priv {
1bf43b82 RS	32	struct exynos_spi *regs;
	33	unsigned int freq; /* Default frequency */
	34	unsigned int mode;
	35	enum periph_id periph_id; /* Peripheral ID for this device */
	36	unsigned int fifo_size;
e4eaef89	37	int skip_preamble;
8d203afd	38	ulong last_transaction_us; /* Time of last transaction end */
1bf43b82 RS	39	};
1bf43b82 RS	40
1bf43b82 RS	41	/**
	42	* Flush spi tx, rx fifos and reset the SPI controller
	43	*
73186c94	44	* @param regs Pointer to SPI registers
1bf43b82	45	*/
73186c94	46	static void spi_flush_fifo(struct exynos_spi *regs)
1bf43b82	47	{
1bf43b82 RS	48	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
	49	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
	50	setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON \| SPI_RX_CH_ON);
	51	}
	52
1bf43b82 RS	53	static void spi_get_fifo_levels(struct exynos_spi *regs,
	54	int rx_lvl, int tx_lvl)
	55	{
	56	uint32_t spi_sts = readl(&regs->spi_sts);
	57
	58	*rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
	59	*tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
	60	}
	61
	62	/**
	63	* If there's something to transfer, do a software reset and set a
	64	* transaction size.
	65	*
	66	* @param regs SPI peripheral registers
	67	* @param count Number of bytes to transfer
c4a79632	68	* @param step Number of bytes to transfer in each packet (1 or 4)
1bf43b82	69	*/
c4a79632	70	static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
1bf43b82	71	{
73186c94 SG	72	debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
73186c94 SG	73
c4a79632 RS	74	/* For word address we need to swap bytes */
	75	if (step == 4) {
	76	setbits_le32(&regs->mode_cfg,
	77	SPI_MODE_CH_WIDTH_WORD \| SPI_MODE_BUS_WIDTH_WORD);
	78	count /= 4;
	79	setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN \| SPI_RX_SWAP_EN \|
	80	SPI_TX_BYTE_SWAP \| SPI_RX_BYTE_SWAP \|
	81	SPI_TX_HWORD_SWAP \| SPI_RX_HWORD_SWAP);
	82	} else {
	83	/* Select byte access and clear the swap configuration */
	84	clrbits_le32(&regs->mode_cfg,
	85	SPI_MODE_CH_WIDTH_WORD \| SPI_MODE_BUS_WIDTH_WORD);
	86	writel(0, &regs->swap_cfg);
	87	}
	88
1bf43b82 RS	89	assert(count && count < (1 << 16));
	90	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
	91	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
c4a79632	92
1bf43b82 RS	93	writel(count \| SPI_PACKET_CNT_EN, &regs->pkt_cnt);
	94	}
	95
73186c94	96	static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
e4eaef89	97	void dinp, void const doutp, unsigned long flags)
1bf43b82	98	{
73186c94	99	struct exynos_spi *regs = priv->regs;
1bf43b82 RS	100	uchar rxp = dinp;
	101	const uchar txp = doutp;
	102	int rx_lvl, tx_lvl;
	103	uint out_bytes, in_bytes;
e4eaef89 RS	104	int toread;
	105	unsigned start = get_timer(0);
	106	int stopping;
c4a79632	107	int step;
1bf43b82 RS	108
	109	out_bytes = in_bytes = todo;
	110
73186c94 SG	111	stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
73186c94 SG	112	!(priv->mode & SPI_SLAVE);
e4eaef89	113
c4a79632 RS	114	/*
	115	* Try to transfer words if we can. This helps read performance at
	116	* SPI clock speeds above about 20MHz.
	117	*/
	118	step = 1;
	119	if (!((todo \| (uintptr_t)rxp \| (uintptr_t)txp) & 3) &&
73186c94	120	!priv->skip_preamble)
c4a79632 RS	121	step = 4;
c4a79632 RS	122
1bf43b82 RS	123	/*
	124	* If there's something to send, do a software reset and set a
	125	* transaction size.
	126	*/
c4a79632	127	spi_request_bytes(regs, todo, step);
1bf43b82 RS	128
	129	/*
	130	* Bytes are transmitted/received in pairs. Wait to receive all the
	131	* data because then transmission will be done as well.
	132	*/
e4eaef89 RS	133	toread = in_bytes;
e4eaef89 RS	134
1bf43b82 RS	135	while (in_bytes) {
	136	int temp;
	137
	138	/* Keep the fifos full/empty. */
	139	spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
c4a79632 RS	140
	141	/*
	142	* Don't completely fill the txfifo, since we don't want our
	143	* rxfifo to overflow, and it may already contain data.
	144	*/
73186c94	145	while (tx_lvl < priv->fifo_size/2 && out_bytes) {
c4a79632 RS	146	if (!txp)
	147	temp = -1;
	148	else if (step == 4)
	149	temp = (uint32_t )txp;
	150	else
	151	temp = *txp;
1bf43b82	152	writel(temp, &regs->tx_data);
c4a79632 RS	153	out_bytes -= step;
	154	if (txp)
	155	txp += step;
	156	tx_lvl += step;
1bf43b82	157	}
c4a79632 RS	158	if (rx_lvl >= step) {
c4a79632 RS	159	while (rx_lvl >= step) {
120af157	160	temp = readl(&regs->rx_data);
73186c94	161	if (priv->skip_preamble) {
120af157	162	if (temp == SPI_PREAMBLE_END_BYTE) {
73186c94	163	priv->skip_preamble = 0;
120af157 RS	164	stopping = 0;
	165	}
	166	} else {
c4a79632	167	if (rxp \|\| stopping) {
e76d2a81 AS	168	if (step == 4)
	169	(uint32_t )rxp = temp;
	170	else
	171	*rxp = temp;
c4a79632 RS	172	rxp += step;
	173	}
	174	in_bytes -= step;
e4eaef89	175	}
c4a79632 RS	176	toread -= step;
	177	rx_lvl -= step;
	178	}
e4eaef89 RS	179	} else if (!toread) {
	180	/*
	181	* We have run out of input data, but haven't read
	182	* enough bytes after the preamble yet. Read some more,
	183	* and make sure that we transmit dummy bytes too, to
	184	* keep things going.
	185	*/
	186	assert(!out_bytes);
	187	out_bytes = in_bytes;
	188	toread = in_bytes;
	189	txp = NULL;
c4a79632	190	spi_request_bytes(regs, toread, step);
e4eaef89	191	}
73186c94	192	if (priv->skip_preamble && get_timer(start) > 100) {
c7d50e7f SG	193	debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
	194	in_bytes, out_bytes);
	195	return -ETIMEDOUT;
1bf43b82 RS	196	}
1bf43b82 RS	197	}
e4eaef89	198
1bf43b82 RS	199	*dinp = rxp;
1bf43b82 RS	200	*doutp = txp;
e4eaef89 RS	201
e4eaef89 RS	202	return 0;
1bf43b82 RS	203	}
1bf43b82 RS	204
1bf43b82 RS	205	/**
	206	* Activate the CS by driving it LOW
	207	*
	208	* @param slave Pointer to spi_slave to which controller has to
	209	* communicate with
	210	*/
73186c94	211	static void spi_cs_activate(struct udevice *dev)
1bf43b82	212	{
73186c94 SG	213	struct udevice *bus = dev->parent;
	214	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
	215	struct exynos_spi_priv *priv = dev_get_priv(bus);
1bf43b82	216
8d203afd	217	/* If it's too soon to do another transaction, wait */
73186c94 SG	218	if (pdata->deactivate_delay_us &&
73186c94 SG	219	priv->last_transaction_us) {
8d203afd	220	ulong delay_us; /* The delay completed so far */
73186c94 SG	221	delay_us = timer_get_us() - priv->last_transaction_us;
	222	if (delay_us < pdata->deactivate_delay_us)
	223	udelay(pdata->deactivate_delay_us - delay_us);
8d203afd RS	224	}
8d203afd RS	225
73186c94 SG	226	clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
	227	debug("Activate CS, bus '%s'\n", bus->name);
	228	priv->skip_preamble = priv->mode & SPI_PREAMBLE;
1bf43b82 RS	229	}
	230
	231	/**
	232	* Deactivate the CS by driving it HIGH
	233	*
	234	* @param slave Pointer to spi_slave to which controller has to
	235	* communicate with
	236	*/
73186c94	237	static void spi_cs_deactivate(struct udevice *dev)
1bf43b82	238	{
73186c94 SG	239	struct udevice *bus = dev->parent;
	240	struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
	241	struct exynos_spi_priv *priv = dev_get_priv(bus);
1bf43b82	242
73186c94	243	setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
a4e29db2 SG	244
a4e29db2 SG	245	/* Remember time of this transaction so we can honour the bus delay */
73186c94 SG	246	if (pdata->deactivate_delay_us)
73186c94 SG	247	priv->last_transaction_us = timer_get_us();
a4e29db2	248
73186c94	249	debug("Deactivate CS, bus '%s'\n", bus->name);
1bf43b82 RS	250	}
1bf43b82 RS	251
73186c94	252	static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
1bf43b82	253	{
73186c94 SG	254	struct exynos_spi_platdata *plat = bus->platdata;
73186c94 SG	255	const void *blob = gd->fdt_blob;
e160f7d4	256	int node = dev_of_offset(bus);
1bf43b82	257
a821c4af	258	plat->regs = (struct exynos_spi *)devfdt_get_addr(bus);
73186c94	259	plat->periph_id = pinmux_decode_periph_id(blob, node);
4d3acb9d	260
73186c94	261	if (plat->periph_id == PERIPH_ID_NONE) {
4d3acb9d	262	debug("%s: Invalid peripheral ID %d\n", __func__,
73186c94	263	plat->periph_id);
4d3acb9d RS	264	return -FDT_ERR_NOTFOUND;
	265	}
	266
	267	/* Use 500KHz as a suitable default */
73186c94	268	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
4d3acb9d	269	500000);
73186c94	270	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
8d203afd	271	"spi-deactivate-delay", 0);
73186c94 SG	272	debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	273	__func__, plat->regs, plat->periph_id, plat->frequency,
	274	plat->deactivate_delay_us);
4d3acb9d RS	275
	276	return 0;
	277	}
	278
73186c94	279	static int exynos_spi_probe(struct udevice *bus)
4d3acb9d	280	{
73186c94 SG	281	struct exynos_spi_platdata *plat = dev_get_platdata(bus);
73186c94 SG	282	struct exynos_spi_priv *priv = dev_get_priv(bus);
4d3acb9d	283
73186c94 SG	284	priv->regs = plat->regs;
	285	if (plat->periph_id == PERIPH_ID_SPI1 \|\|
	286	plat->periph_id == PERIPH_ID_SPI2)
	287	priv->fifo_size = 64;
	288	else
	289	priv->fifo_size = 256;
4d3acb9d	290
73186c94 SG	291	priv->skip_preamble = 0;
	292	priv->last_transaction_us = timer_get_us();
	293	priv->freq = plat->frequency;
	294	priv->periph_id = plat->periph_id;
4d3acb9d	295
73186c94 SG	296	return 0;
73186c94 SG	297	}
4d3acb9d	298
9694b724	299	static int exynos_spi_claim_bus(struct udevice *dev)
73186c94	300	{
9694b724	301	struct udevice *bus = dev->parent;
73186c94 SG	302	struct exynos_spi_priv *priv = dev_get_priv(bus);
	303
	304	exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
	305	spi_flush_fifo(priv->regs);
	306
	307	writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
4d3acb9d RS	308
	309	return 0;
	310	}
	311
9694b724	312	static int exynos_spi_release_bus(struct udevice *dev)
f3424c55	313	{
9694b724	314	struct udevice *bus = dev->parent;
73186c94 SG	315	struct exynos_spi_priv *priv = dev_get_priv(bus);
	316
	317	spi_flush_fifo(priv->regs);
	318
	319	return 0;
	320	}
	321
	322	static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
	323	const void dout, void din, unsigned long flags)
	324	{
	325	struct udevice *bus = dev->parent;
	326	struct exynos_spi_priv *priv = dev_get_priv(bus);
	327	int upto, todo;
	328	int bytelen;
	329	int ret = 0;
	330
	331	/* spi core configured to do 8 bit transfers */
	332	if (bitlen % 8) {
	333	debug("Non byte aligned SPI transfer.\n");
	334	return -1;
	335	}
	336
	337	/* Start the transaction, if necessary. */
	338	if ((flags & SPI_XFER_BEGIN))
	339	spi_cs_activate(dev);
	340
	341	/*
	342	* Exynos SPI limits each transfer to 65535 transfers. To keep
	343	* things simple, allow a maximum of 65532 bytes. We could allow
	344	* more in word mode, but the performance difference is small.
	345	*/
	346	bytelen = bitlen / 8;
	347	for (upto = 0; !ret && upto < bytelen; upto += todo) {
	348	todo = min(bytelen - upto, (1 << 16) - 4);
	349	ret = spi_rx_tx(priv, todo, &din, &dout, flags);
	350	if (ret)
	351	break;
	352	}
f3424c55	353
73186c94 SG	354	/* Stop the transaction, if necessary. */
	355	if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
	356	spi_cs_deactivate(dev);
	357	if (priv->skip_preamble) {
	358	assert(!priv->skip_preamble);
	359	debug("Failed to complete premable transaction\n");
	360	ret = -1;
	361	}
f3424c55 HT	362	}
f3424c55 HT	363
73186c94	364	return ret;
f3424c55 HT	365	}
f3424c55 HT	366
73186c94	367	static int exynos_spi_set_speed(struct udevice *bus, uint speed)
1bf43b82	368	{
73186c94 SG	369	struct exynos_spi_platdata *plat = bus->platdata;
	370	struct exynos_spi_priv *priv = dev_get_priv(bus);
	371	int ret;
4d3acb9d	372
73186c94 SG	373	if (speed > plat->frequency)
	374	speed = plat->frequency;
	375	ret = set_spi_clk(priv->periph_id, speed);
	376	if (ret)
	377	return ret;
	378	priv->freq = speed;
	379	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
	380
	381	return 0;
	382	}
4d3acb9d	383
73186c94 SG	384	static int exynos_spi_set_mode(struct udevice *bus, uint mode)
	385	{
	386	struct exynos_spi_priv *priv = dev_get_priv(bus);
	387	uint32_t reg;
4d3acb9d	388
73186c94 SG	389	reg = readl(&priv->regs->ch_cfg);
73186c94 SG	390	reg &= ~(SPI_CH_CPHA_B \| SPI_CH_CPOL_L);
1bf43b82	391
73186c94 SG	392	if (mode & SPI_CPHA)
73186c94 SG	393	reg \|= SPI_CH_CPHA_B;
1bf43b82	394
73186c94 SG	395	if (mode & SPI_CPOL)
	396	reg \|= SPI_CH_CPOL_L;
	397
	398	writel(reg, &priv->regs->ch_cfg);
	399	priv->mode = mode;
	400	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
	401
	402	return 0;
1bf43b82	403	}
73186c94 SG	404
	405	static const struct dm_spi_ops exynos_spi_ops = {
	406	.claim_bus = exynos_spi_claim_bus,
	407	.release_bus = exynos_spi_release_bus,
	408	.xfer = exynos_spi_xfer,
	409	.set_speed = exynos_spi_set_speed,
	410	.set_mode = exynos_spi_set_mode,
	411	/*
	412	* cs_info is not needed, since we require all chip selects to be
	413	* in the device tree explicitly
	414	*/
	415	};
	416
	417	static const struct udevice_id exynos_spi_ids[] = {
	418	{ .compatible = "samsung,exynos-spi" },
	419	{ }
	420	};
	421
	422	U_BOOT_DRIVER(exynos_spi) = {
	423	.name = "exynos_spi",
	424	.id = UCLASS_SPI,
	425	.of_match = exynos_spi_ids,
	426	.ops = &exynos_spi_ops,
	427	.ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
	428	.platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
	429	.priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
73186c94 SG	430	.probe = exynos_spi_probe,
73186c94 SG	431	};