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1853030e SG |
1 | /* |
2 | * Copyright (c) 2011-12 The Chromium OS Authors. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
1853030e SG |
5 | * |
6 | * This file is derived from the flashrom project. | |
7 | */ | |
9eb4339b | 8 | |
1853030e | 9 | #include <common.h> |
ba457562 | 10 | #include <dm.h> |
5093badb | 11 | #include <errno.h> |
1853030e | 12 | #include <malloc.h> |
f2b85ab5 | 13 | #include <pch.h> |
1853030e SG |
14 | #include <pci.h> |
15 | #include <pci_ids.h> | |
f2b85ab5 | 16 | #include <spi.h> |
1853030e SG |
17 | #include <asm/io.h> |
18 | ||
19 | #include "ich.h" | |
20 | ||
1f9eb59d BM |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
fffe25db SG |
23 | #ifdef DEBUG_TRACE |
24 | #define debug_trace(fmt, args...) debug(fmt, ##args) | |
25 | #else | |
26 | #define debug_trace(x, args...) | |
27 | #endif | |
28 | ||
ba457562 | 29 | static u8 ich_readb(struct ich_spi_priv *priv, int reg) |
1853030e | 30 | { |
ba457562 | 31 | u8 value = readb(priv->base + reg); |
1853030e | 32 | |
fffe25db | 33 | debug_trace("read %2.2x from %4.4x\n", value, reg); |
1853030e SG |
34 | |
35 | return value; | |
36 | } | |
37 | ||
ba457562 | 38 | static u16 ich_readw(struct ich_spi_priv *priv, int reg) |
1853030e | 39 | { |
ba457562 | 40 | u16 value = readw(priv->base + reg); |
1853030e | 41 | |
fffe25db | 42 | debug_trace("read %4.4x from %4.4x\n", value, reg); |
1853030e SG |
43 | |
44 | return value; | |
45 | } | |
46 | ||
ba457562 | 47 | static u32 ich_readl(struct ich_spi_priv *priv, int reg) |
1853030e | 48 | { |
ba457562 | 49 | u32 value = readl(priv->base + reg); |
1853030e | 50 | |
fffe25db | 51 | debug_trace("read %8.8x from %4.4x\n", value, reg); |
1853030e SG |
52 | |
53 | return value; | |
54 | } | |
55 | ||
ba457562 | 56 | static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) |
1853030e | 57 | { |
ba457562 | 58 | writeb(value, priv->base + reg); |
fffe25db | 59 | debug_trace("wrote %2.2x to %4.4x\n", value, reg); |
1853030e SG |
60 | } |
61 | ||
ba457562 | 62 | static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) |
1853030e | 63 | { |
ba457562 | 64 | writew(value, priv->base + reg); |
fffe25db | 65 | debug_trace("wrote %4.4x to %4.4x\n", value, reg); |
1853030e SG |
66 | } |
67 | ||
ba457562 | 68 | static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) |
1853030e | 69 | { |
ba457562 | 70 | writel(value, priv->base + reg); |
fffe25db | 71 | debug_trace("wrote %8.8x to %4.4x\n", value, reg); |
1853030e SG |
72 | } |
73 | ||
ba457562 SG |
74 | static void write_reg(struct ich_spi_priv *priv, const void *value, |
75 | int dest_reg, uint32_t size) | |
1853030e | 76 | { |
ba457562 | 77 | memcpy_toio(priv->base + dest_reg, value, size); |
1853030e SG |
78 | } |
79 | ||
ba457562 SG |
80 | static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, |
81 | uint32_t size) | |
1853030e | 82 | { |
ba457562 | 83 | memcpy_fromio(value, priv->base + src_reg, size); |
1853030e SG |
84 | } |
85 | ||
ba457562 | 86 | static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) |
1853030e SG |
87 | { |
88 | const uint32_t bbar_mask = 0x00ffff00; | |
89 | uint32_t ichspi_bbar; | |
90 | ||
91 | minaddr &= bbar_mask; | |
ba457562 | 92 | ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; |
1853030e | 93 | ichspi_bbar |= minaddr; |
ba457562 | 94 | ich_writel(ctlr, ichspi_bbar, ctlr->bbar); |
1853030e SG |
95 | } |
96 | ||
1853030e | 97 | /* @return 1 if the SPI flash supports the 33MHz speed */ |
f2b85ab5 | 98 | static int ich9_can_do_33mhz(struct udevice *dev) |
1853030e SG |
99 | { |
100 | u32 fdod, speed; | |
101 | ||
102 | /* Observe SPI Descriptor Component Section 0 */ | |
f2b85ab5 | 103 | dm_pci_write_config32(dev->parent, 0xb0, 0x1000); |
1853030e SG |
104 | |
105 | /* Extract the Write/Erase SPI Frequency from descriptor */ | |
f2b85ab5 | 106 | dm_pci_read_config32(dev->parent, 0xb4, &fdod); |
1853030e SG |
107 | |
108 | /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ | |
109 | speed = (fdod >> 21) & 7; | |
110 | ||
111 | return speed == 1; | |
112 | } | |
113 | ||
f2b85ab5 SG |
114 | static int ich_init_controller(struct udevice *dev, |
115 | struct ich_spi_platdata *plat, | |
ba457562 | 116 | struct ich_spi_priv *ctlr) |
1853030e | 117 | { |
f2b85ab5 SG |
118 | ulong sbase_addr; |
119 | void *sbase; | |
5093badb SG |
120 | |
121 | /* SBASE is similar */ | |
3e389d8b | 122 | pch_get_spi_base(dev->parent, &sbase_addr); |
f2b85ab5 SG |
123 | sbase = (void *)sbase_addr; |
124 | debug("%s: sbase=%p\n", __func__, sbase); | |
5093badb | 125 | |
6e670b5c | 126 | if (plat->ich_version == ICHV_7) { |
f2b85ab5 | 127 | struct ich7_spi_regs *ich7_spi = sbase; |
1853030e | 128 | |
f2b85ab5 | 129 | ich7_spi = (struct ich7_spi_regs *)sbase; |
ba457562 SG |
130 | ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK; |
131 | ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); | |
1853030e | 132 | ctlr->menubytes = sizeof(ich7_spi->opmenu); |
ba457562 SG |
133 | ctlr->optype = offsetof(struct ich7_spi_regs, optype); |
134 | ctlr->addr = offsetof(struct ich7_spi_regs, spia); | |
135 | ctlr->data = offsetof(struct ich7_spi_regs, spid); | |
1853030e | 136 | ctlr->databytes = sizeof(ich7_spi->spid); |
ba457562 SG |
137 | ctlr->status = offsetof(struct ich7_spi_regs, spis); |
138 | ctlr->control = offsetof(struct ich7_spi_regs, spic); | |
139 | ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); | |
140 | ctlr->preop = offsetof(struct ich7_spi_regs, preop); | |
1853030e | 141 | ctlr->base = ich7_spi; |
6e670b5c | 142 | } else if (plat->ich_version == ICHV_9) { |
f2b85ab5 | 143 | struct ich9_spi_regs *ich9_spi = sbase; |
1853030e | 144 | |
ba457562 SG |
145 | ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
146 | ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); | |
1853030e | 147 | ctlr->menubytes = sizeof(ich9_spi->opmenu); |
ba457562 SG |
148 | ctlr->optype = offsetof(struct ich9_spi_regs, optype); |
149 | ctlr->addr = offsetof(struct ich9_spi_regs, faddr); | |
150 | ctlr->data = offsetof(struct ich9_spi_regs, fdata); | |
1853030e | 151 | ctlr->databytes = sizeof(ich9_spi->fdata); |
ba457562 SG |
152 | ctlr->status = offsetof(struct ich9_spi_regs, ssfs); |
153 | ctlr->control = offsetof(struct ich9_spi_regs, ssfc); | |
154 | ctlr->speed = ctlr->control + 2; | |
155 | ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); | |
156 | ctlr->preop = offsetof(struct ich9_spi_regs, preop); | |
50787928 | 157 | ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); |
1853030e SG |
158 | ctlr->pr = &ich9_spi->pr[0]; |
159 | ctlr->base = ich9_spi; | |
160 | } else { | |
ba457562 SG |
161 | debug("ICH SPI: Unrecognised ICH version %d\n", |
162 | plat->ich_version); | |
163 | return -EINVAL; | |
1853030e | 164 | } |
1853030e SG |
165 | |
166 | /* Work out the maximum speed we can support */ | |
167 | ctlr->max_speed = 20000000; | |
6e670b5c | 168 | if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) |
1853030e | 169 | ctlr->max_speed = 33000000; |
f2b85ab5 | 170 | debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", |
ba457562 | 171 | plat->ich_version, ctlr->base, ctlr->max_speed); |
1853030e SG |
172 | |
173 | ich_set_bbar(ctlr, 0); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
1853030e SG |
178 | static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) |
179 | { | |
180 | trans->out += bytes; | |
181 | trans->bytesout -= bytes; | |
182 | } | |
183 | ||
184 | static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) | |
185 | { | |
186 | trans->in += bytes; | |
187 | trans->bytesin -= bytes; | |
188 | } | |
189 | ||
190 | static void spi_setup_type(struct spi_trans *trans, int data_bytes) | |
191 | { | |
192 | trans->type = 0xFF; | |
193 | ||
9eb4339b | 194 | /* Try to guess spi type from read/write sizes */ |
1853030e SG |
195 | if (trans->bytesin == 0) { |
196 | if (trans->bytesout + data_bytes > 4) | |
197 | /* | |
198 | * If bytesin = 0 and bytesout > 4, we presume this is | |
199 | * a write data operation, which is accompanied by an | |
200 | * address. | |
201 | */ | |
202 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; | |
203 | else | |
204 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; | |
205 | return; | |
206 | } | |
207 | ||
208 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ | |
209 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; | |
210 | return; | |
211 | } | |
212 | ||
213 | if (trans->bytesout == 4) /* and bytesin is > 0 */ | |
214 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; | |
215 | ||
216 | /* Fast read command is called with 5 bytes instead of 4 */ | |
217 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { | |
218 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; | |
219 | --trans->bytesout; | |
220 | } | |
221 | } | |
222 | ||
ba457562 | 223 | static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans) |
1853030e SG |
224 | { |
225 | uint16_t optypes; | |
ba457562 | 226 | uint8_t opmenu[ctlr->menubytes]; |
1853030e SG |
227 | |
228 | trans->opcode = trans->out[0]; | |
229 | spi_use_out(trans, 1); | |
ba457562 | 230 | if (!ctlr->ichspi_lock) { |
1853030e | 231 | /* The lock is off, so just use index 0. */ |
ba457562 SG |
232 | ich_writeb(ctlr, trans->opcode, ctlr->opmenu); |
233 | optypes = ich_readw(ctlr, ctlr->optype); | |
1853030e | 234 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
ba457562 | 235 | ich_writew(ctlr, optypes, ctlr->optype); |
1853030e SG |
236 | return 0; |
237 | } else { | |
238 | /* The lock is on. See if what we need is on the menu. */ | |
239 | uint8_t optype; | |
240 | uint16_t opcode_index; | |
241 | ||
242 | /* Write Enable is handled as atomic prefix */ | |
243 | if (trans->opcode == SPI_OPCODE_WREN) | |
244 | return 0; | |
245 | ||
ba457562 SG |
246 | read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); |
247 | for (opcode_index = 0; opcode_index < ctlr->menubytes; | |
1853030e SG |
248 | opcode_index++) { |
249 | if (opmenu[opcode_index] == trans->opcode) | |
250 | break; | |
251 | } | |
252 | ||
ba457562 | 253 | if (opcode_index == ctlr->menubytes) { |
1853030e SG |
254 | printf("ICH SPI: Opcode %x not found\n", |
255 | trans->opcode); | |
ba457562 | 256 | return -EINVAL; |
1853030e SG |
257 | } |
258 | ||
ba457562 | 259 | optypes = ich_readw(ctlr, ctlr->optype); |
1853030e SG |
260 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
261 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && | |
262 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && | |
263 | trans->bytesout >= 3) { | |
264 | /* We guessed wrong earlier. Fix it up. */ | |
265 | trans->type = optype; | |
266 | } | |
267 | if (optype != trans->type) { | |
268 | printf("ICH SPI: Transaction doesn't fit type %d\n", | |
269 | optype); | |
ba457562 | 270 | return -ENOSPC; |
1853030e SG |
271 | } |
272 | return opcode_index; | |
273 | } | |
274 | } | |
275 | ||
276 | static int spi_setup_offset(struct spi_trans *trans) | |
277 | { | |
9eb4339b | 278 | /* Separate the SPI address and data */ |
1853030e SG |
279 | switch (trans->type) { |
280 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: | |
281 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: | |
282 | return 0; | |
283 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: | |
284 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: | |
285 | trans->offset = ((uint32_t)trans->out[0] << 16) | | |
286 | ((uint32_t)trans->out[1] << 8) | | |
287 | ((uint32_t)trans->out[2] << 0); | |
288 | spi_use_out(trans, 3); | |
289 | return 1; | |
290 | default: | |
291 | printf("Unrecognized SPI transaction type %#x\n", trans->type); | |
ba457562 | 292 | return -EPROTO; |
1853030e SG |
293 | } |
294 | } | |
295 | ||
296 | /* | |
297 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set | |
472d5460 | 298 | * below is true) or 0. In case the wait was for the bit(s) to set - write |
1853030e SG |
299 | * those bits back, which would cause resetting them. |
300 | * | |
301 | * Return the last read status value on success or -1 on failure. | |
302 | */ | |
ba457562 SG |
303 | static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, |
304 | int wait_til_set) | |
1853030e SG |
305 | { |
306 | int timeout = 600000; /* This will result in 6s */ | |
307 | u16 status = 0; | |
308 | ||
309 | while (timeout--) { | |
ba457562 | 310 | status = ich_readw(ctlr, ctlr->status); |
1853030e | 311 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
ba457562 SG |
312 | if (wait_til_set) { |
313 | ich_writew(ctlr, status & bitmask, | |
314 | ctlr->status); | |
315 | } | |
1853030e SG |
316 | return status; |
317 | } | |
318 | udelay(10); | |
319 | } | |
320 | ||
321 | printf("ICH SPI: SCIP timeout, read %x, expected %x\n", | |
322 | status, bitmask); | |
ba457562 | 323 | return -ETIMEDOUT; |
1853030e SG |
324 | } |
325 | ||
ba457562 SG |
326 | static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
327 | const void *dout, void *din, unsigned long flags) | |
1853030e | 328 | { |
ba457562 | 329 | struct udevice *bus = dev_get_parent(dev); |
e1e332c8 | 330 | struct ich_spi_platdata *plat = dev_get_platdata(bus); |
ba457562 | 331 | struct ich_spi_priv *ctlr = dev_get_priv(bus); |
1853030e SG |
332 | uint16_t control; |
333 | int16_t opcode_index; | |
334 | int with_address; | |
335 | int status; | |
336 | int bytes = bitlen / 8; | |
ba457562 | 337 | struct spi_trans *trans = &ctlr->trans; |
1853030e SG |
338 | unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); |
339 | int using_cmd = 0; | |
ba457562 | 340 | int ret; |
1853030e | 341 | |
5d4a757c | 342 | /* We don't support writing partial bytes */ |
1853030e SG |
343 | if (bitlen % 8) { |
344 | debug("ICH SPI: Accessing partial bytes not supported\n"); | |
ba457562 | 345 | return -EPROTONOSUPPORT; |
1853030e SG |
346 | } |
347 | ||
348 | /* An empty end transaction can be ignored */ | |
349 | if (type == SPI_XFER_END && !dout && !din) | |
350 | return 0; | |
351 | ||
352 | if (type & SPI_XFER_BEGIN) | |
353 | memset(trans, '\0', sizeof(*trans)); | |
354 | ||
355 | /* Dp we need to come back later to finish it? */ | |
356 | if (dout && type == SPI_XFER_BEGIN) { | |
357 | if (bytes > ICH_MAX_CMD_LEN) { | |
358 | debug("ICH SPI: Command length limit exceeded\n"); | |
ba457562 | 359 | return -ENOSPC; |
1853030e SG |
360 | } |
361 | memcpy(trans->cmd, dout, bytes); | |
362 | trans->cmd_len = bytes; | |
fffe25db | 363 | debug_trace("ICH SPI: Saved %d bytes\n", bytes); |
1853030e SG |
364 | return 0; |
365 | } | |
366 | ||
367 | /* | |
368 | * We process a 'middle' spi_xfer() call, which has no | |
369 | * SPI_XFER_BEGIN/END, as an independent transaction as if it had | |
370 | * an end. We therefore repeat the command. This is because ICH | |
371 | * seems to have no support for this, or because interest (in digging | |
372 | * out the details and creating a special case in the code) is low. | |
373 | */ | |
374 | if (trans->cmd_len) { | |
375 | trans->out = trans->cmd; | |
376 | trans->bytesout = trans->cmd_len; | |
377 | using_cmd = 1; | |
fffe25db | 378 | debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); |
1853030e SG |
379 | } else { |
380 | trans->out = dout; | |
381 | trans->bytesout = dout ? bytes : 0; | |
382 | } | |
383 | ||
384 | trans->in = din; | |
385 | trans->bytesin = din ? bytes : 0; | |
386 | ||
9eb4339b | 387 | /* There has to always at least be an opcode */ |
1853030e SG |
388 | if (!trans->bytesout) { |
389 | debug("ICH SPI: No opcode for transfer\n"); | |
ba457562 | 390 | return -EPROTO; |
1853030e SG |
391 | } |
392 | ||
ba457562 SG |
393 | ret = ich_status_poll(ctlr, SPIS_SCIP, 0); |
394 | if (ret < 0) | |
395 | return ret; | |
1853030e | 396 | |
6e670b5c | 397 | if (plat->ich_version == ICHV_7) |
e1e332c8 SG |
398 | ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); |
399 | else | |
400 | ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); | |
1853030e SG |
401 | |
402 | spi_setup_type(trans, using_cmd ? bytes : 0); | |
ba457562 | 403 | opcode_index = spi_setup_opcode(ctlr, trans); |
1853030e | 404 | if (opcode_index < 0) |
ba457562 | 405 | return -EINVAL; |
1853030e SG |
406 | with_address = spi_setup_offset(trans); |
407 | if (with_address < 0) | |
ba457562 | 408 | return -EINVAL; |
1853030e SG |
409 | |
410 | if (trans->opcode == SPI_OPCODE_WREN) { | |
411 | /* | |
412 | * Treat Write Enable as Atomic Pre-Op if possible | |
413 | * in order to prevent the Management Engine from | |
414 | * issuing a transaction between WREN and DATA. | |
415 | */ | |
ba457562 SG |
416 | if (!ctlr->ichspi_lock) |
417 | ich_writew(ctlr, trans->opcode, ctlr->preop); | |
1853030e SG |
418 | return 0; |
419 | } | |
420 | ||
ba457562 | 421 | if (ctlr->speed && ctlr->max_speed >= 33000000) { |
1853030e SG |
422 | int byte; |
423 | ||
ba457562 SG |
424 | byte = ich_readb(ctlr, ctlr->speed); |
425 | if (ctlr->cur_speed >= 33000000) | |
1853030e SG |
426 | byte |= SSFC_SCF_33MHZ; |
427 | else | |
428 | byte &= ~SSFC_SCF_33MHZ; | |
ba457562 | 429 | ich_writeb(ctlr, byte, ctlr->speed); |
1853030e SG |
430 | } |
431 | ||
432 | /* See if we have used up the command data */ | |
433 | if (using_cmd && dout && bytes) { | |
434 | trans->out = dout; | |
435 | trans->bytesout = bytes; | |
fffe25db | 436 | debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); |
1853030e SG |
437 | } |
438 | ||
439 | /* Preset control fields */ | |
ba457562 | 440 | control = ich_readw(ctlr, ctlr->control); |
1853030e SG |
441 | control &= ~SSFC_RESERVED; |
442 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); | |
443 | ||
444 | /* Issue atomic preop cycle if needed */ | |
ba457562 | 445 | if (ich_readw(ctlr, ctlr->preop)) |
1853030e SG |
446 | control |= SPIC_ACS; |
447 | ||
448 | if (!trans->bytesout && !trans->bytesin) { | |
449 | /* SPI addresses are 24 bit only */ | |
ba457562 SG |
450 | if (with_address) { |
451 | ich_writel(ctlr, trans->offset & 0x00FFFFFF, | |
452 | ctlr->addr); | |
453 | } | |
1853030e SG |
454 | /* |
455 | * This is a 'no data' command (like Write Enable), its | |
456 | * bitesout size was 1, decremented to zero while executing | |
457 | * spi_setup_opcode() above. Tell the chip to send the | |
458 | * command. | |
459 | */ | |
ba457562 | 460 | ich_writew(ctlr, control, ctlr->control); |
1853030e SG |
461 | |
462 | /* wait for the result */ | |
ba457562 SG |
463 | status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); |
464 | if (status < 0) | |
465 | return status; | |
1853030e SG |
466 | |
467 | if (status & SPIS_FCERR) { | |
468 | debug("ICH SPI: Command transaction error\n"); | |
ba457562 | 469 | return -EIO; |
1853030e SG |
470 | } |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | /* | |
476 | * Check if this is a write command atempting to transfer more bytes | |
477 | * than the controller can handle. Iterations for writes are not | |
478 | * supported here because each SPI write command needs to be preceded | |
479 | * and followed by other SPI commands, and this sequence is controlled | |
480 | * by the SPI chip driver. | |
481 | */ | |
ba457562 | 482 | if (trans->bytesout > ctlr->databytes) { |
1853030e | 483 | debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); |
ba457562 | 484 | return -EPROTO; |
1853030e SG |
485 | } |
486 | ||
487 | /* | |
488 | * Read or write up to databytes bytes at a time until everything has | |
489 | * been sent. | |
490 | */ | |
491 | while (trans->bytesout || trans->bytesin) { | |
492 | uint32_t data_length; | |
1853030e SG |
493 | |
494 | /* SPI addresses are 24 bit only */ | |
ba457562 | 495 | ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); |
1853030e SG |
496 | |
497 | if (trans->bytesout) | |
ba457562 | 498 | data_length = min(trans->bytesout, ctlr->databytes); |
1853030e | 499 | else |
ba457562 | 500 | data_length = min(trans->bytesin, ctlr->databytes); |
1853030e SG |
501 | |
502 | /* Program data into FDATA0 to N */ | |
503 | if (trans->bytesout) { | |
ba457562 | 504 | write_reg(ctlr, trans->out, ctlr->data, data_length); |
1853030e SG |
505 | spi_use_out(trans, data_length); |
506 | if (with_address) | |
507 | trans->offset += data_length; | |
508 | } | |
509 | ||
510 | /* Add proper control fields' values */ | |
ba457562 | 511 | control &= ~((ctlr->databytes - 1) << 8); |
1853030e SG |
512 | control |= SPIC_DS; |
513 | control |= (data_length - 1) << 8; | |
514 | ||
515 | /* write it */ | |
ba457562 | 516 | ich_writew(ctlr, control, ctlr->control); |
1853030e | 517 | |
9eb4339b | 518 | /* Wait for Cycle Done Status or Flash Cycle Error */ |
ba457562 SG |
519 | status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); |
520 | if (status < 0) | |
521 | return status; | |
1853030e SG |
522 | |
523 | if (status & SPIS_FCERR) { | |
5d4a757c | 524 | debug("ICH SPI: Data transaction error %x\n", status); |
ba457562 | 525 | return -EIO; |
1853030e SG |
526 | } |
527 | ||
528 | if (trans->bytesin) { | |
ba457562 | 529 | read_reg(ctlr, ctlr->data, trans->in, data_length); |
1853030e SG |
530 | spi_use_in(trans, data_length); |
531 | if (with_address) | |
532 | trans->offset += data_length; | |
533 | } | |
534 | } | |
535 | ||
536 | /* Clear atomic preop now that xfer is done */ | |
ba457562 | 537 | ich_writew(ctlr, 0, ctlr->preop); |
1853030e SG |
538 | |
539 | return 0; | |
540 | } | |
541 | ||
1853030e SG |
542 | /* |
543 | * This uses the SPI controller from the Intel Cougar Point and Panther Point | |
544 | * PCH to write-protect portions of the SPI flash until reboot. The changes | |
545 | * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's | |
546 | * done elsewhere. | |
547 | */ | |
ba457562 SG |
548 | int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit, |
549 | uint32_t length, int hint) | |
1853030e | 550 | { |
ba457562 SG |
551 | struct udevice *bus = dev->parent; |
552 | struct ich_spi_priv *ctlr = dev_get_priv(bus); | |
1853030e SG |
553 | uint32_t tmplong; |
554 | uint32_t upper_limit; | |
555 | ||
ba457562 | 556 | if (!ctlr->pr) { |
1853030e SG |
557 | printf("%s: operation not supported on this chipset\n", |
558 | __func__); | |
ba457562 | 559 | return -ENOSYS; |
1853030e SG |
560 | } |
561 | ||
562 | if (length == 0 || | |
563 | lower_limit > (0xFFFFFFFFUL - length) + 1 || | |
564 | hint < 0 || hint > 4) { | |
565 | printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, | |
566 | lower_limit, length, hint); | |
ba457562 | 567 | return -EPERM; |
1853030e SG |
568 | } |
569 | ||
570 | upper_limit = lower_limit + length - 1; | |
571 | ||
572 | /* | |
573 | * Determine bits to write, as follows: | |
574 | * 31 Write-protection enable (includes erase operation) | |
575 | * 30:29 reserved | |
576 | * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) | |
577 | * 15 Read-protection enable | |
578 | * 14:13 reserved | |
579 | * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) | |
580 | */ | |
581 | tmplong = 0x80000000 | | |
582 | ((upper_limit & 0x01fff000) << 4) | | |
583 | ((lower_limit & 0x01fff000) >> 12); | |
584 | ||
585 | printf("%s: writing 0x%08x to %p\n", __func__, tmplong, | |
ba457562 SG |
586 | &ctlr->pr[hint]); |
587 | ctlr->pr[hint] = tmplong; | |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
f2b85ab5 | 592 | static int ich_spi_probe(struct udevice *dev) |
ba457562 | 593 | { |
f2b85ab5 SG |
594 | struct ich_spi_platdata *plat = dev_get_platdata(dev); |
595 | struct ich_spi_priv *priv = dev_get_priv(dev); | |
ba457562 SG |
596 | uint8_t bios_cntl; |
597 | int ret; | |
598 | ||
f2b85ab5 | 599 | ret = ich_init_controller(dev, plat, priv); |
ba457562 SG |
600 | if (ret) |
601 | return ret; | |
f2b85ab5 SG |
602 | /* Disable the BIOS write protect so write commands are allowed */ |
603 | ret = pch_set_spi_protect(dev->parent, false); | |
604 | if (ret == -ENOSYS) { | |
50787928 | 605 | bios_cntl = ich_readb(priv, priv->bcr); |
69fd4c38 | 606 | bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ |
ba457562 | 607 | bios_cntl |= 1; /* Write Protect Disable (WPD) */ |
50787928 | 608 | ich_writeb(priv, bios_cntl, priv->bcr); |
f2b85ab5 SG |
609 | } else if (ret) { |
610 | debug("%s: Failed to disable write-protect: err=%d\n", | |
611 | __func__, ret); | |
612 | return ret; | |
ba457562 SG |
613 | } |
614 | ||
615 | priv->cur_speed = priv->max_speed; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
ba457562 SG |
620 | static int ich_spi_set_speed(struct udevice *bus, uint speed) |
621 | { | |
622 | struct ich_spi_priv *priv = dev_get_priv(bus); | |
623 | ||
624 | priv->cur_speed = speed; | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static int ich_spi_set_mode(struct udevice *bus, uint mode) | |
630 | { | |
631 | debug("%s: mode=%d\n", __func__, mode); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static int ich_spi_child_pre_probe(struct udevice *dev) | |
637 | { | |
638 | struct udevice *bus = dev_get_parent(dev); | |
639 | struct ich_spi_platdata *plat = dev_get_platdata(bus); | |
640 | struct ich_spi_priv *priv = dev_get_priv(bus); | |
bcbe3d15 | 641 | struct spi_slave *slave = dev_get_parent_priv(dev); |
ba457562 SG |
642 | |
643 | /* | |
644 | * Yes this controller can only write a small number of bytes at | |
645 | * once! The limit is typically 64 bytes. | |
646 | */ | |
647 | slave->max_write_size = priv->databytes; | |
648 | /* | |
649 | * ICH 7 SPI controller only supports array read command | |
650 | * and byte program command for SST flash | |
651 | */ | |
08fe9c29 JT |
652 | if (plat->ich_version == ICHV_7) |
653 | slave->mode = SPI_RX_SLOW | SPI_TX_BYTE; | |
ba457562 SG |
654 | |
655 | return 0; | |
656 | } | |
657 | ||
1f9eb59d BM |
658 | static int ich_spi_ofdata_to_platdata(struct udevice *dev) |
659 | { | |
660 | struct ich_spi_platdata *plat = dev_get_platdata(dev); | |
e160f7d4 | 661 | int node = dev_of_offset(dev); |
1f9eb59d BM |
662 | int ret; |
663 | ||
e160f7d4 | 664 | ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); |
1f9eb59d | 665 | if (ret == 0) { |
6e670b5c | 666 | plat->ich_version = ICHV_7; |
1f9eb59d | 667 | } else { |
e160f7d4 | 668 | ret = fdt_node_check_compatible(gd->fdt_blob, node, |
1f9eb59d BM |
669 | "intel,ich9-spi"); |
670 | if (ret == 0) | |
6e670b5c | 671 | plat->ich_version = ICHV_9; |
1f9eb59d BM |
672 | } |
673 | ||
674 | return ret; | |
675 | } | |
676 | ||
ba457562 SG |
677 | static const struct dm_spi_ops ich_spi_ops = { |
678 | .xfer = ich_spi_xfer, | |
679 | .set_speed = ich_spi_set_speed, | |
680 | .set_mode = ich_spi_set_mode, | |
681 | /* | |
682 | * cs_info is not needed, since we require all chip selects to be | |
683 | * in the device tree explicitly | |
684 | */ | |
685 | }; | |
686 | ||
687 | static const struct udevice_id ich_spi_ids[] = { | |
1f9eb59d BM |
688 | { .compatible = "intel,ich7-spi" }, |
689 | { .compatible = "intel,ich9-spi" }, | |
ba457562 SG |
690 | { } |
691 | }; | |
692 | ||
693 | U_BOOT_DRIVER(ich_spi) = { | |
694 | .name = "ich_spi", | |
695 | .id = UCLASS_SPI, | |
696 | .of_match = ich_spi_ids, | |
697 | .ops = &ich_spi_ops, | |
1f9eb59d | 698 | .ofdata_to_platdata = ich_spi_ofdata_to_platdata, |
ba457562 SG |
699 | .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), |
700 | .priv_auto_alloc_size = sizeof(struct ich_spi_priv), | |
701 | .child_pre_probe = ich_spi_child_pre_probe, | |
702 | .probe = ich_spi_probe, | |
703 | }; |