[people/ms/u-boot.git] / drivers / spi / mxc_spi.c

/*
 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <mxc_gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
 * datasheet, the correct one is in the Freescale's Linux driver */

#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."

#elif defined(CONFIG_MX31)

#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_SMC	(1 << 3)
#define MXC_CSPICTRL_POL	(1 << 4)
#define MXC_CSPICTRL_PHA	(1 << 5)
#define MXC_CSPICTRL_SSCTL	(1 << 6)
#define MXC_CSPICTRL_SSPOL	(1 << 7)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
#define MXC_CSPICTRL_TC		(1 << 8)
#define MXC_CSPICTRL_RXOVF	(1 << 6)
#define MXC_CSPICTRL_MAXBITS	0x1f

#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
#define MAX_SPI_BYTES	4

static unsigned long spi_bases[] = {
	0x43fa4000,
	0x50010000,
	0x53f84000,
};

#elif defined(CONFIG_MX51)

#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS	0xfff
#define MXC_CSPICTRL_TC		(1 << 7)
#define MXC_CSPICTRL_RXOVF	(1 << 6)

#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
#define MAX_SPI_BYTES	32

/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN	18

/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_POL		4
#define MXC_CSPICON_PHA		0
#define MXC_CSPICON_SSPOL	12

static unsigned long spi_bases[] = {
	CSPI1_BASE_ADDR,
	CSPI2_BASE_ADDR,
	CSPI3_BASE_ADDR,
};

#elif defined(CONFIG_MX35)

#define MXC_CSPICTRL_EN		(1 << 0)
#define MXC_CSPICTRL_MODE	(1 << 1)
#define MXC_CSPICTRL_XCH	(1 << 2)
#define MXC_CSPICTRL_SMC	(1 << 3)
#define MXC_CSPICTRL_POL	(1 << 4)
#define MXC_CSPICTRL_PHA	(1 << 5)
#define MXC_CSPICTRL_SSCTL	(1 << 6)
#define MXC_CSPICTRL_SSPOL	(1 << 7)
#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
#define MXC_CSPICTRL_TC		(1 << 7)
#define MXC_CSPICTRL_RXOVF	(1 << 6)
#define MXC_CSPICTRL_MAXBITS	0xfff

#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
#define MAX_SPI_BYTES	4

static unsigned long spi_bases[] = {
	0x43fa4000,
	0x50010000,
};

#else
#error "Unsupported architecture"
#endif

#define OUT	MXC_GPIO_DIRECTION_OUT

#define reg_read readl
#define reg_write(a, v) writel(v, a)

struct mxc_spi_slave {
	struct spi_slave slave;
	unsigned long	base;
	u32		ctrl_reg;
#if defined(CONFIG_MX51)
	u32		cfg_reg;
#endif
	int		gpio;
	int		ss_pol;
};

static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
{
	return container_of(slave, struct mxc_spi_slave, slave);
}

void spi_cs_activate(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	if (mxcs->gpio > 0)
		mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	if (mxcs->gpio > 0)
		mxc_gpio_set(mxcs->gpio,
			      !(mxcs->ss_pol));
}

u32 get_cspi_div(u32 div)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (div <= (4 << i))
			return i;
	}
	return i;
}

#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	unsigned int ctrl_reg;
	u32 clk_src;
	u32 div;

	clk_src = mxc_get_clock(MXC_CSPI_CLK);

	div = clk_src / max_hz;
	div = get_cspi_div(div);

	debug("clk %d Hz, div %d, real clk %d Hz\n",
		max_hz, div, clk_src / (4 << div));

	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
		MXC_CSPICTRL_DATARATE(div) |
		MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
		MXC_CSPICTRL_SSCTL |
#endif
		MXC_CSPICTRL_MODE;

	if (mode & SPI_CPHA)
		ctrl_reg |= MXC_CSPICTRL_PHA;
	if (mode & SPI_CPOL)
		ctrl_reg |= MXC_CSPICTRL_POL;
	if (mode & SPI_CS_HIGH)
		ctrl_reg |= MXC_CSPICTRL_SSPOL;
	mxcs->ctrl_reg = ctrl_reg;

	return 0;
}
#endif

#if defined(CONFIG_MX51)
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
		unsigned int max_hz, unsigned int mode)
{
	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	if (max_hz == 0) {
		printf("Error: desired clock is 0\n");
		return -1;
	}

	reg_ctrl = reg_read(&regs->ctrl);

	/* Reset spi */
	reg_write(&regs->ctrl, 0);
	reg_write(&regs->ctrl, (reg_ctrl | 0x1));

	/*
	 * The following computation is taken directly from Freescale's code.
	 */
	if (clk_src > max_hz) {
		pre_div = clk_src / max_hz;
		if (pre_div > 16) {
			post_div = pre_div / 16;
			pre_div = 15;
		}
		if (post_div != 0) {
			for (i = 0; i < 16; i++) {
				if ((1 << i) >= post_div)
					break;
			}
			if (i == 16) {
				printf("Error: no divider for the freq: %d\n",
					max_hz);
				return -1;
			}
			post_div = i;
		}
	}

	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
		MXC_CSPICTRL_SELCHAN(cs);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
		MXC_CSPICTRL_PREDIV(pre_div);
	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
		MXC_CSPICTRL_POSTDIV(post_div);

	/* always set to master mode */
	reg_ctrl |= 1 << (cs + 4);

	/* We need to disable SPI before changing registers */
	reg_ctrl &= ~MXC_CSPICTRL_EN;

	if (mode & SPI_CS_HIGH)
		ss_pol = 1;

	if (mode & SPI_CPOL)
		sclkpol = 1;

	if (mode & SPI_CPHA)
		sclkpha = 1;

	reg_config = reg_read(&regs->cfg);

	/*
	 * Configuration register setup
	 * The MX51 supports different setup for each SS
	 */
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
		(ss_pol << (cs + MXC_CSPICON_SSPOL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
		(sclkpol << (cs + MXC_CSPICON_POL));
	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
		(sclkpha << (cs + MXC_CSPICON_PHA));

	debug("reg_ctrl = 0x%x\n", reg_ctrl);
	reg_write(&regs->ctrl, reg_ctrl);
	debug("reg_config = 0x%x\n", reg_config);
	reg_write(&regs->cfg, reg_config);

	/* save config register and control register */
	mxcs->ctrl_reg = reg_ctrl;
	mxcs->cfg_reg = reg_config;

	/* clear interrupt reg */
	reg_write(&regs->intr, 0);
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	return 0;
}
#endif

int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
	const u8 *dout, u8 *din, unsigned long flags)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	int nbytes = (bitlen + 7) / 8;
	u32 data, cnt, i;
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
		__func__, bitlen, (u32)dout, (u32)din);

	mxcs->ctrl_reg = (mxcs->ctrl_reg &
		~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
		MXC_CSPICTRL_BITCOUNT(bitlen - 1);

	reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
#ifdef CONFIG_MX51
	reg_write(&regs->cfg, mxcs->cfg_reg);
#endif

	/* Clear interrupt register */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	/*
	 * The SPI controller works only with words,
	 * check if less than a word is sent.
	 * Access to the FIFO is only 32 bit
	 */
	if (bitlen % 32) {
		data = 0;
		cnt = (bitlen % 32) / 8;
		if (dout) {
			for (i = 0; i < cnt; i++) {
				data = (data << 8) | (*dout++ & 0xFF);
			}
		}
		debug("Sending SPI 0x%x\n", data);

		reg_write(&regs->txdata, data);
		nbytes -= cnt;
	}

	data = 0;

	while (nbytes > 0) {
		data = 0;
		if (dout) {
			/* Buffer is not 32-bit aligned */
			if ((unsigned long)dout & 0x03) {
				data = 0;
				for (i = 0; i < 4; i++)
					data = (data << 8) | (*dout++ & 0xFF);
			} else {
				data = *(u32 *)dout;
				data = cpu_to_be32(data);
			}
			dout += 4;
		}
		debug("Sending SPI 0x%x\n", data);
		reg_write(&regs->txdata, data);
		nbytes -= 4;
	}

	/* FIFO is written, now starts the transfer setting the XCH bit */
	reg_write(&regs->ctrl, mxcs->ctrl_reg |
		MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);

	/* Wait until the TC (Transfer completed) bit is set */
	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
		;

	/* Transfer completed, clear any pending request */
	reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);

	nbytes = (bitlen + 7) / 8;

	cnt = nbytes % 32;

	if (bitlen % 32) {
		data = reg_read(&regs->rxdata);
		cnt = (bitlen % 32) / 8;
		data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
		debug("SPI Rx unaligned: 0x%x\n", data);
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	while (nbytes > 0) {
		u32 tmp;
		tmp = reg_read(&regs->rxdata);
		data = cpu_to_be32(tmp);
		debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
		cnt = min(nbytes, sizeof(data));
		if (din) {
			memcpy(din, &data, cnt);
			din += cnt;
		}
		nbytes -= cnt;
	}

	return 0;

}

int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
		void *din, unsigned long flags)
{
	int n_bytes = (bitlen + 7) / 8;
	int n_bits;
	int ret;
	u32 blk_size;
	u8 *p_outbuf = (u8 *)dout;
	u8 *p_inbuf = (u8 *)din;

	if (!slave)
		return -1;

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(slave);

	while (n_bytes > 0) {
		if (n_bytes < MAX_SPI_BYTES)
			blk_size = n_bytes;
		else
			blk_size = MAX_SPI_BYTES;

		n_bits = blk_size * 8;

		ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);

		if (ret)
			return ret;
		if (dout)
			p_outbuf += blk_size;
		if (din)
			p_inbuf += blk_size;
		n_bytes -= blk_size;
	}

	if (flags & SPI_XFER_END) {
		spi_cs_deactivate(slave);
	}

	return 0;
}

void spi_init(void)
{
}

static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
{
	int ret;

	/*
	 * Some SPI devices require active chip-select over multiple
	 * transactions, we achieve this using a GPIO. Still, the SPI
	 * controller has to be configured to use one of its own chipselects.
	 * To use this feature you have to call spi_setup_slave() with
	 * cs = internal_cs | (gpio << 8), and you have to use some unused
	 * on this SPI controller cs between 0 and 3.
	 */
	if (cs > 3) {
		mxcs->gpio = cs >> 8;
		cs &= 3;
		ret = mxc_gpio_direction(mxcs->gpio, OUT);
		if (ret) {
			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
			return -EINVAL;
		}
	} else {
		mxcs->gpio = -1;
	}

	return cs;
}

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)
{
	struct mxc_spi_slave *mxcs;
	int ret;

	if (bus >= ARRAY_SIZE(spi_bases))
		return NULL;

	mxcs = malloc(sizeof(struct mxc_spi_slave));
	if (!mxcs) {
		puts("mxc_spi: SPI Slave not allocated !\n");
		return NULL;
	}

	ret = decode_cs(mxcs, cs);
	if (ret < 0) {
		free(mxcs);
		return NULL;
	}

	cs = ret;

	mxcs->slave.bus = bus;
	mxcs->slave.cs = cs;
	mxcs->base = spi_bases[bus];
	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;

	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
	if (ret) {
		printf("mxc_spi: cannot setup SPI controller\n");
		free(mxcs);
		return NULL;
	}
	return &mxcs->slave;
}

void spi_free_slave(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);

	free(mxcs);
}

int spi_claim_bus(struct spi_slave *slave)
{
	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;

	reg_write(&regs->rxdata, 1);
	udelay(1);
	reg_write(&regs->ctrl, mxcs->ctrl_reg);
	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	reg_write(&regs->intr, 0);

	return 0;
}

void spi_release_bus(struct spi_slave *slave)
{
	/* TODO: Shut the controller down */
}
Commit	Line	Data
38254f45 GL	1	/*
	2	* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	*/
	20
	21	#include <common.h>
d255bb0e	22	#include <malloc.h>
38254f45	23	#include <spi.h>
fc7a93c8	24	#include <asm/errno.h>
38254f45	25	#include <asm/io.h>
c4ea1424	26	#include <mxc_gpio.h>
86271115 SB	27	#include <asm/arch/imx-regs.h>
86271115 SB	28	#include <asm/arch/clock.h>
38254f45 GL	29
	30	#ifdef CONFIG_MX27
	31	/* i.MX27 has a completely wrong register layout and register definitions in the
	32	* datasheet, the correct one is in the Freescale's Linux driver */
	33
61a58a16	34	#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
38254f45 GL	35	"See linux mxc_spi driver from Freescale for details."
38254f45 GL	36
d205ddcf	37	#elif defined(CONFIG_MX31)
38254f45	38
38254f45 GL	39	#define MXC_CSPICTRL_EN (1 << 0)
	40	#define MXC_CSPICTRL_MODE (1 << 1)
	41	#define MXC_CSPICTRL_XCH (1 << 2)
	42	#define MXC_CSPICTRL_SMC (1 << 3)
	43	#define MXC_CSPICTRL_POL (1 << 4)
	44	#define MXC_CSPICTRL_PHA (1 << 5)
	45	#define MXC_CSPICTRL_SSCTL (1 << 6)
53677ef1	46	#define MXC_CSPICTRL_SSPOL (1 << 7)
38254f45 GL	47	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
	48	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
	49	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
d205ddcf SB	50	#define MXC_CSPICTRL_TC (1 << 8)
	51	#define MXC_CSPICTRL_RXOVF (1 << 6)
	52	#define MXC_CSPICTRL_MAXBITS 0x1f
38254f45 GL	53
38254f45 GL	54	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
2f721d17	55	#define MAX_SPI_BYTES 4
38254f45 GL	56
	57	static unsigned long spi_bases[] = {
	58	0x43fa4000,
	59	0x50010000,
	60	0x53f84000,
	61	};
	62
d205ddcf	63	#elif defined(CONFIG_MX51)
d205ddcf	64
d205ddcf SB	65	#define MXC_CSPICTRL_EN (1 << 0)
	66	#define MXC_CSPICTRL_MODE (1 << 1)
	67	#define MXC_CSPICTRL_XCH (1 << 2)
	68	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
	69	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
	70	#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
	71	#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
	72	#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
	73	#define MXC_CSPICTRL_MAXBITS 0xfff
	74	#define MXC_CSPICTRL_TC (1 << 7)
	75	#define MXC_CSPICTRL_RXOVF (1 << 6)
	76
	77	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
2f721d17	78	#define MAX_SPI_BYTES 32
d205ddcf SB	79
	80	/* Bit position inside CTRL register to be associated with SS */
	81	#define MXC_CSPICTRL_CHAN 18
	82
	83	/* Bit position inside CON register to be associated with SS */
	84	#define MXC_CSPICON_POL 4
	85	#define MXC_CSPICON_PHA 0
	86	#define MXC_CSPICON_SSPOL 12
	87
	88	static unsigned long spi_bases[] = {
	89	CSPI1_BASE_ADDR,
	90	CSPI2_BASE_ADDR,
	91	CSPI3_BASE_ADDR,
	92	};
c9d59c7f SB	93
	94	#elif defined(CONFIG_MX35)
	95
c9d59c7f SB	96	#define MXC_CSPICTRL_EN (1 << 0)
	97	#define MXC_CSPICTRL_MODE (1 << 1)
	98	#define MXC_CSPICTRL_XCH (1 << 2)
	99	#define MXC_CSPICTRL_SMC (1 << 3)
	100	#define MXC_CSPICTRL_POL (1 << 4)
	101	#define MXC_CSPICTRL_PHA (1 << 5)
	102	#define MXC_CSPICTRL_SSCTL (1 << 6)
	103	#define MXC_CSPICTRL_SSPOL (1 << 7)
	104	#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
	105	#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
	106	#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
	107	#define MXC_CSPICTRL_TC (1 << 7)
	108	#define MXC_CSPICTRL_RXOVF (1 << 6)
	109	#define MXC_CSPICTRL_MAXBITS 0xfff
	110
	111	#define MXC_CSPIPERIOD_32KHZ (1 << 15)
	112	#define MAX_SPI_BYTES 4
	113
	114	static unsigned long spi_bases[] = {
	115	0x43fa4000,
	116	0x50010000,
	117	};
	118
d205ddcf SB	119	#else
d205ddcf SB	120	#error "Unsupported architecture"
38254f45 GL	121	#endif
38254f45 GL	122
c4ea1424 SB	123	#define OUT MXC_GPIO_DIRECTION_OUT
c4ea1424 SB	124
ac87c17d SB	125	#define reg_read readl
	126	#define reg_write(a, v) writel(v, a)
	127
d255bb0e HS	128	struct mxc_spi_slave {
	129	struct spi_slave slave;
	130	unsigned long base;
	131	u32 ctrl_reg;
d205ddcf SB	132	#if defined(CONFIG_MX51)
	133	u32 cfg_reg;
	134	#endif
fc7a93c8	135	int gpio;
c4ea1424	136	int ss_pol;
38254f45	137	};
d255bb0e HS	138
	139	static inline struct mxc_spi_slave to_mxc_spi_slave(struct spi_slave slave)
	140	{
	141	return container_of(slave, struct mxc_spi_slave, slave);
	142	}
38254f45	143
d205ddcf SB	144	void spi_cs_activate(struct spi_slave *slave)
	145	{
	146	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	147	if (mxcs->gpio > 0)
c4ea1424	148	mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
d205ddcf SB	149	}
	150
	151	void spi_cs_deactivate(struct spi_slave *slave)
	152	{
	153	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	154	if (mxcs->gpio > 0)
	155	mxc_gpio_set(mxcs->gpio,
c4ea1424	156	!(mxcs->ss_pol));
d205ddcf SB	157	}
d205ddcf SB	158
afaa9f65 AG	159	u32 get_cspi_div(u32 div)
	160	{
	161	int i;
	162
	163	for (i = 0; i < 8; i++) {
	164	if (div <= (4 << i))
	165	return i;
	166	}
	167	return i;
	168	}
	169
c9d59c7f SB	170	#if defined(CONFIG_MX31) \|\| defined(CONFIG_MX35)
	171	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
	172	unsigned int max_hz, unsigned int mode)
	173	{
	174	unsigned int ctrl_reg;
afaa9f65 AG	175	u32 clk_src;
	176	u32 div;
	177
	178	clk_src = mxc_get_clock(MXC_CSPI_CLK);
	179
	180	div = clk_src / max_hz;
	181	div = get_cspi_div(div);
	182
	183	debug("clk %d Hz, div %d, real clk %d Hz\n",
	184	max_hz, div, clk_src / (4 << div));
c9d59c7f SB	185
	186	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) \|
	187	MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) \|
afaa9f65	188	MXC_CSPICTRL_DATARATE(div) \|
c9d59c7f SB	189	MXC_CSPICTRL_EN \|
	190	#ifdef CONFIG_MX35
	191	MXC_CSPICTRL_SSCTL \|
	192	#endif
	193	MXC_CSPICTRL_MODE;
	194
	195	if (mode & SPI_CPHA)
	196	ctrl_reg \|= MXC_CSPICTRL_PHA;
	197	if (mode & SPI_CPOL)
	198	ctrl_reg \|= MXC_CSPICTRL_POL;
	199	if (mode & SPI_CS_HIGH)
	200	ctrl_reg \|= MXC_CSPICTRL_SSPOL;
	201	mxcs->ctrl_reg = ctrl_reg;
	202
	203	return 0;
	204	}
	205	#endif
	206
	207	#if defined(CONFIG_MX51)
	208	static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
d205ddcf SB	209	unsigned int max_hz, unsigned int mode)
	210	{
	211	u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
	212	s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
	213	u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
ac87c17d	214	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
d205ddcf SB	215
	216	if (max_hz == 0) {
	217	printf("Error: desired clock is 0\n");
	218	return -1;
	219	}
	220
ac87c17d	221	reg_ctrl = reg_read(&regs->ctrl);
d205ddcf SB	222
d205ddcf SB	223	/* Reset spi */
ac87c17d SB	224	reg_write(&regs->ctrl, 0);
ac87c17d SB	225	reg_write(&regs->ctrl, (reg_ctrl \| 0x1));
d205ddcf SB	226
	227	/*
	228	* The following computation is taken directly from Freescale's code.
	229	*/
	230	if (clk_src > max_hz) {
	231	pre_div = clk_src / max_hz;
	232	if (pre_div > 16) {
	233	post_div = pre_div / 16;
	234	pre_div = 15;
	235	}
	236	if (post_div != 0) {
	237	for (i = 0; i < 16; i++) {
	238	if ((1 << i) >= post_div)
	239	break;
	240	}
	241	if (i == 16) {
	242	printf("Error: no divider for the freq: %d\n",
	243	max_hz);
	244	return -1;
	245	}
	246	post_div = i;
	247	}
	248	}
	249
	250	debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
	251	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) \|
	252	MXC_CSPICTRL_SELCHAN(cs);
	253	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) \|
	254	MXC_CSPICTRL_PREDIV(pre_div);
	255	reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) \|
	256	MXC_CSPICTRL_POSTDIV(post_div);
	257
	258	/* always set to master mode */
	259	reg_ctrl \|= 1 << (cs + 4);
	260
	261	/* We need to disable SPI before changing registers */
	262	reg_ctrl &= ~MXC_CSPICTRL_EN;
	263
	264	if (mode & SPI_CS_HIGH)
	265	ss_pol = 1;
	266
9f481e95	267	if (mode & SPI_CPOL)
d205ddcf SB	268	sclkpol = 1;
	269
	270	if (mode & SPI_CPHA)
	271	sclkpha = 1;
	272
ac87c17d	273	reg_config = reg_read(&regs->cfg);
d205ddcf SB	274
	275	/*
	276	* Configuration register setup
c9d59c7f	277	* The MX51 supports different setup for each SS
d205ddcf SB	278	*/
	279	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) \|
	280	(ss_pol << (cs + MXC_CSPICON_SSPOL));
	281	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) \|
	282	(sclkpol << (cs + MXC_CSPICON_POL));
	283	reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) \|
	284	(sclkpha << (cs + MXC_CSPICON_PHA));
	285
	286	debug("reg_ctrl = 0x%x\n", reg_ctrl);
ac87c17d	287	reg_write(&regs->ctrl, reg_ctrl);
d205ddcf	288	debug("reg_config = 0x%x\n", reg_config);
ac87c17d	289	reg_write(&regs->cfg, reg_config);
d205ddcf SB	290
	291	/* save config register and control register */
	292	mxcs->ctrl_reg = reg_ctrl;
	293	mxcs->cfg_reg = reg_config;
	294
	295	/* clear interrupt reg */
ac87c17d SB	296	reg_write(&regs->intr, 0);
ac87c17d SB	297	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf SB	298
	299	return 0;
	300	}
	301	#endif
	302
2f721d17 SB	303	int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
2f721d17 SB	304	const u8 dout, u8 din, unsigned long flags)
38254f45	305	{
d255bb0e	306	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
2f721d17 SB	307	int nbytes = (bitlen + 7) / 8;
2f721d17 SB	308	u32 data, cnt, i;
ac87c17d	309	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
38254f45	310
2f721d17 SB	311	debug("%s: bitlen %d dout 0x%x din 0x%x\n",
2f721d17 SB	312	__func__, bitlen, (u32)dout, (u32)din);
d205ddcf SB	313
	314	mxcs->ctrl_reg = (mxcs->ctrl_reg &
	315	~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) \|
f9b6a157	316	MXC_CSPICTRL_BITCOUNT(bitlen - 1);
38254f45	317
ac87c17d	318	reg_write(&regs->ctrl, mxcs->ctrl_reg \| MXC_CSPICTRL_EN);
d205ddcf	319	#ifdef CONFIG_MX51
ac87c17d	320	reg_write(&regs->cfg, mxcs->cfg_reg);
d205ddcf	321	#endif
38254f45	322
d205ddcf	323	/* Clear interrupt register */
ac87c17d	324	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
fc7a93c8	325
2f721d17 SB	326	/*
	327	* The SPI controller works only with words,
	328	* check if less than a word is sent.
	329	* Access to the FIFO is only 32 bit
	330	*/
	331	if (bitlen % 32) {
	332	data = 0;
	333	cnt = (bitlen % 32) / 8;
	334	if (dout) {
	335	for (i = 0; i < cnt; i++) {
	336	data = (data << 8) \| (*dout++ & 0xFF);
	337	}
	338	}
	339	debug("Sending SPI 0x%x\n", data);
	340
ac87c17d	341	reg_write(&regs->txdata, data);
2f721d17 SB	342	nbytes -= cnt;
	343	}
	344
	345	data = 0;
	346
	347	while (nbytes > 0) {
	348	data = 0;
	349	if (dout) {
	350	/* Buffer is not 32-bit aligned */
	351	if ((unsigned long)dout & 0x03) {
	352	data = 0;
dff01094	353	for (i = 0; i < 4; i++)
2f721d17	354	data = (data << 8) \| (*dout++ & 0xFF);
2f721d17 SB	355	} else {
	356	data = (u32 )dout;
	357	data = cpu_to_be32(data);
	358	}
	359	dout += 4;
	360	}
	361	debug("Sending SPI 0x%x\n", data);
ac87c17d	362	reg_write(&regs->txdata, data);
2f721d17 SB	363	nbytes -= 4;
2f721d17 SB	364	}
38254f45	365
d205ddcf	366	/* FIFO is written, now starts the transfer setting the XCH bit */
ac87c17d	367	reg_write(&regs->ctrl, mxcs->ctrl_reg \|
d205ddcf	368	MXC_CSPICTRL_EN \| MXC_CSPICTRL_XCH);
38254f45	369
d205ddcf	370	/* Wait until the TC (Transfer completed) bit is set */
ac87c17d	371	while ((reg_read(&regs->stat) & MXC_CSPICTRL_TC) == 0)
38254f45 GL	372	;
38254f45 GL	373
d205ddcf	374	/* Transfer completed, clear any pending request */
ac87c17d	375	reg_write(&regs->stat, MXC_CSPICTRL_TC \| MXC_CSPICTRL_RXOVF);
d205ddcf	376
2f721d17	377	nbytes = (bitlen + 7) / 8;
d205ddcf	378
2f721d17	379	cnt = nbytes % 32;
d205ddcf	380
2f721d17	381	if (bitlen % 32) {
ac87c17d	382	data = reg_read(&regs->rxdata);
2f721d17	383	cnt = (bitlen % 32) / 8;
dff01094	384	data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
2f721d17 SB	385	debug("SPI Rx unaligned: 0x%x\n", data);
2f721d17 SB	386	if (din) {
dff01094 AG	387	memcpy(din, &data, cnt);
dff01094 AG	388	din += cnt;
2f721d17 SB	389	}
	390	nbytes -= cnt;
	391	}
	392
	393	while (nbytes > 0) {
	394	u32 tmp;
ac87c17d	395	tmp = reg_read(&regs->rxdata);
2f721d17 SB	396	data = cpu_to_be32(tmp);
	397	debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
	398	cnt = min(nbytes, sizeof(data));
	399	if (din) {
	400	memcpy(din, &data, cnt);
	401	din += cnt;
	402	}
	403	nbytes -= cnt;
	404	}
	405
	406	return 0;
fc7a93c8	407
38254f45 GL	408	}
38254f45 GL	409
d255bb0e HS	410	int spi_xfer(struct spi_slave slave, unsigned int bitlen, const void dout,
d255bb0e HS	411	void *din, unsigned long flags)
38254f45	412	{
2f721d17 SB	413	int n_bytes = (bitlen + 7) / 8;
	414	int n_bits;
	415	int ret;
	416	u32 blk_size;
	417	u8 p_outbuf = (u8 )dout;
	418	u8 p_inbuf = (u8 )din;
38254f45	419
2f721d17 SB	420	if (!slave)
2f721d17 SB	421	return -1;
38254f45	422
2f721d17 SB	423	if (flags & SPI_XFER_BEGIN)
	424	spi_cs_activate(slave);
	425
	426	while (n_bytes > 0) {
2f721d17 SB	427	if (n_bytes < MAX_SPI_BYTES)
	428	blk_size = n_bytes;
	429	else
	430	blk_size = MAX_SPI_BYTES;
	431
	432	n_bits = blk_size * 8;
	433
	434	ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
	435
	436	if (ret)
	437	return ret;
	438	if (dout)
	439	p_outbuf += blk_size;
	440	if (din)
	441	p_inbuf += blk_size;
	442	n_bytes -= blk_size;
eff536be ML	443	}
eff536be ML	444
2f721d17 SB	445	if (flags & SPI_XFER_END) {
2f721d17 SB	446	spi_cs_deactivate(slave);
f9b6a157	447	}
38254f45 GL	448
	449	return 0;
	450	}
	451
	452	void spi_init(void)
	453	{
	454	}
	455
fc7a93c8 GL	456	static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
	457	{
	458	int ret;
	459
	460	/*
	461	* Some SPI devices require active chip-select over multiple
	462	* transactions, we achieve this using a GPIO. Still, the SPI
	463	* controller has to be configured to use one of its own chipselects.
	464	* To use this feature you have to call spi_setup_slave() with
	465	* cs = internal_cs \| (gpio << 8), and you have to use some unused
	466	* on this SPI controller cs between 0 and 3.
	467	*/
	468	if (cs > 3) {
	469	mxcs->gpio = cs >> 8;
	470	cs &= 3;
d205ddcf	471	ret = mxc_gpio_direction(mxcs->gpio, OUT);
fc7a93c8 GL	472	if (ret) {
	473	printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
	474	return -EINVAL;
	475	}
	476	} else {
	477	mxcs->gpio = -1;
	478	}
	479
	480	return cs;
	481	}
	482
d255bb0e HS	483	struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
d255bb0e HS	484	unsigned int max_hz, unsigned int mode)
38254f45	485	{
d255bb0e	486	struct mxc_spi_slave *mxcs;
fc7a93c8 GL	487	int ret;
	488
	489	if (bus >= ARRAY_SIZE(spi_bases))
	490	return NULL;
	491
	492	mxcs = malloc(sizeof(struct mxc_spi_slave));
2f721d17 SB	493	if (!mxcs) {
2f721d17 SB	494	puts("mxc_spi: SPI Slave not allocated !\n");
fc7a93c8	495	return NULL;
2f721d17	496	}
38254f45	497
fc7a93c8 GL	498	ret = decode_cs(mxcs, cs);
	499	if (ret < 0) {
	500	free(mxcs);
d255bb0e	501	return NULL;
fc7a93c8 GL	502	}
	503
	504	cs = ret;
38254f45	505
d205ddcf SB	506	mxcs->slave.bus = bus;
	507	mxcs->slave.cs = cs;
	508	mxcs->base = spi_bases[bus];
c4ea1424	509	mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
d205ddcf	510
c9d59c7f	511	ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
d205ddcf SB	512	if (ret) {
	513	printf("mxc_spi: cannot setup SPI controller\n");
	514	free(mxcs);
	515	return NULL;
	516	}
d255bb0e HS	517	return &mxcs->slave;
	518	}
	519
	520	void spi_free_slave(struct spi_slave *slave)
	521	{
f9b6a157 GL	522	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
	523
	524	free(mxcs);
d255bb0e HS	525	}
	526
	527	int spi_claim_bus(struct spi_slave *slave)
	528	{
	529	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
ac87c17d	530	struct cspi_regs regs = (struct cspi_regs )mxcs->base;
d255bb0e	531
ac87c17d	532	reg_write(&regs->rxdata, 1);
38254f45	533	udelay(1);
ac87c17d SB	534	reg_write(&regs->ctrl, mxcs->ctrl_reg);
	535	reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
	536	reg_write(&regs->intr, 0);
38254f45 GL	537
	538	return 0;
	539	}
d255bb0e HS	540
	541	void spi_release_bus(struct spi_slave *slave)
	542	{
	543	/* TODO: Shut the controller down */
	544	}